1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/apicdef.h> 10 #include <linux/atomic.h> 11 #include <asm/fixmap.h> 12 #include <asm/mpspec.h> 13 #include <asm/msr.h> 14 #include <asm/hardirq.h> 15 16 #define ARCH_APICTIMER_STOPS_ON_C3 1 17 18 /* 19 * Debugging macros 20 */ 21 #define APIC_QUIET 0 22 #define APIC_VERBOSE 1 23 #define APIC_DEBUG 2 24 25 /* Macros for apic_extnmi which controls external NMI masking */ 26 #define APIC_EXTNMI_BSP 0 /* Default */ 27 #define APIC_EXTNMI_ALL 1 28 #define APIC_EXTNMI_NONE 2 29 30 /* 31 * Define the default level of output to be very little 32 * This can be turned up by using apic=verbose for more 33 * information and apic=debug for _lots_ of information. 34 * apic_verbosity is defined in apic.c 35 */ 36 #define apic_printk(v, s, a...) do { \ 37 if ((v) <= apic_verbosity) \ 38 printk(s, ##a); \ 39 } while (0) 40 41 42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 43 extern void x86_32_probe_apic(void); 44 #else 45 static inline void x86_32_probe_apic(void) { } 46 #endif 47 48 #ifdef CONFIG_X86_LOCAL_APIC 49 50 extern int apic_verbosity; 51 extern int local_apic_timer_c2_ok; 52 53 extern bool apic_is_disabled; 54 extern unsigned int lapic_timer_period; 55 56 extern int cpuid_to_apicid[]; 57 58 extern enum apic_intr_mode_id apic_intr_mode; 59 enum apic_intr_mode_id { 60 APIC_PIC, 61 APIC_VIRTUAL_WIRE, 62 APIC_VIRTUAL_WIRE_NO_CONFIG, 63 APIC_SYMMETRIC_IO, 64 APIC_SYMMETRIC_IO_NO_ROUTING 65 }; 66 67 /* 68 * With 82489DX we can't rely on apic feature bit 69 * retrieved via cpuid but still have to deal with 70 * such an apic chip so we assume that SMP configuration 71 * is found from MP table (64bit case uses ACPI mostly 72 * which set smp presence flag as well so we are safe 73 * to use this helper too). 74 */ 75 static inline bool apic_from_smp_config(void) 76 { 77 return smp_found_config && !apic_is_disabled; 78 } 79 80 /* 81 * Basic functions accessing APICs. 82 */ 83 #ifdef CONFIG_PARAVIRT 84 #include <asm/paravirt.h> 85 #endif 86 87 static inline void native_apic_mem_write(u32 reg, u32 v) 88 { 89 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 90 91 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 92 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 93 ASM_OUTPUT2("0" (v), "m" (*addr))); 94 } 95 96 static inline u32 native_apic_mem_read(u32 reg) 97 { 98 return *((volatile u32 *)(APIC_BASE + reg)); 99 } 100 101 extern u32 native_safe_apic_wait_icr_idle(void); 102 extern void native_apic_icr_write(u32 low, u32 id); 103 extern u64 native_apic_icr_read(void); 104 105 static inline bool apic_is_x2apic_enabled(void) 106 { 107 u64 msr; 108 109 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 110 return false; 111 return msr & X2APIC_ENABLE; 112 } 113 114 extern void enable_IR_x2apic(void); 115 116 extern int get_physical_broadcast(void); 117 118 extern int lapic_get_maxlvt(void); 119 extern void clear_local_APIC(void); 120 extern void disconnect_bsp_APIC(int virt_wire_setup); 121 extern void disable_local_APIC(void); 122 extern void apic_soft_disable(void); 123 extern void lapic_shutdown(void); 124 extern void sync_Arb_IDs(void); 125 extern void init_bsp_APIC(void); 126 extern void apic_intr_mode_select(void); 127 extern void apic_intr_mode_init(void); 128 extern void init_apic_mappings(void); 129 void register_lapic_address(unsigned long address); 130 extern void setup_boot_APIC_clock(void); 131 extern void setup_secondary_APIC_clock(void); 132 extern void lapic_update_tsc_freq(void); 133 134 #ifdef CONFIG_X86_64 135 static inline bool apic_force_enable(unsigned long addr) 136 { 137 return false; 138 } 139 #else 140 extern bool apic_force_enable(unsigned long addr); 141 #endif 142 143 extern void apic_ap_setup(void); 144 145 /* 146 * On 32bit this is mach-xxx local 147 */ 148 #ifdef CONFIG_X86_64 149 extern int apic_is_clustered_box(void); 150 #else 151 static inline int apic_is_clustered_box(void) 152 { 153 return 0; 154 } 155 #endif 156 157 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 158 extern void lapic_assign_system_vectors(void); 159 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 160 extern void lapic_update_legacy_vectors(void); 161 extern void lapic_online(void); 162 extern void lapic_offline(void); 163 extern bool apic_needs_pit(void); 164 165 extern void apic_send_IPI_allbutself(unsigned int vector); 166 167 #else /* !CONFIG_X86_LOCAL_APIC */ 168 static inline void lapic_shutdown(void) { } 169 #define local_apic_timer_c2_ok 1 170 static inline void init_apic_mappings(void) { } 171 static inline void disable_local_APIC(void) { } 172 # define setup_boot_APIC_clock x86_init_noop 173 # define setup_secondary_APIC_clock x86_init_noop 174 static inline void lapic_update_tsc_freq(void) { } 175 static inline void init_bsp_APIC(void) { } 176 static inline void apic_intr_mode_select(void) { } 177 static inline void apic_intr_mode_init(void) { } 178 static inline void lapic_assign_system_vectors(void) { } 179 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 180 static inline bool apic_needs_pit(void) { return true; } 181 #endif /* !CONFIG_X86_LOCAL_APIC */ 182 183 #ifdef CONFIG_X86_X2APIC 184 static inline void native_apic_msr_write(u32 reg, u32 v) 185 { 186 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 187 reg == APIC_LVR) 188 return; 189 190 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 191 } 192 193 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 194 { 195 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 196 } 197 198 static inline u32 native_apic_msr_read(u32 reg) 199 { 200 u64 msr; 201 202 if (reg == APIC_DFR) 203 return -1; 204 205 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 206 return (u32)msr; 207 } 208 209 static inline void native_x2apic_wait_icr_idle(void) 210 { 211 /* no need to wait for icr idle in x2apic */ 212 return; 213 } 214 215 static inline u32 native_safe_x2apic_wait_icr_idle(void) 216 { 217 /* no need to wait for icr idle in x2apic */ 218 return 0; 219 } 220 221 static inline void native_x2apic_icr_write(u32 low, u32 id) 222 { 223 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 224 } 225 226 static inline u64 native_x2apic_icr_read(void) 227 { 228 unsigned long val; 229 230 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 231 return val; 232 } 233 234 extern int x2apic_mode; 235 extern int x2apic_phys; 236 extern void __init x2apic_set_max_apicid(u32 apicid); 237 extern void x2apic_setup(void); 238 static inline int x2apic_enabled(void) 239 { 240 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 241 } 242 243 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 244 #else /* !CONFIG_X86_X2APIC */ 245 static inline void x2apic_setup(void) { } 246 static inline int x2apic_enabled(void) { return 0; } 247 static inline u32 native_apic_msr_read(u32 reg) { BUG(); } 248 #define x2apic_mode (0) 249 #define x2apic_supported() (0) 250 #endif /* !CONFIG_X86_X2APIC */ 251 extern void __init check_x2apic(void); 252 253 struct irq_data; 254 255 /* 256 * Copyright 2004 James Cleverdon, IBM. 257 * 258 * Generic APIC sub-arch data struct. 259 * 260 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 261 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 262 * James Cleverdon. 263 */ 264 struct apic { 265 /* Hotpath functions first */ 266 void (*eoi_write)(u32 reg, u32 v); 267 void (*native_eoi_write)(u32 reg, u32 v); 268 void (*write)(u32 reg, u32 v); 269 u32 (*read)(u32 reg); 270 271 /* IPI related functions */ 272 void (*wait_icr_idle)(void); 273 u32 (*safe_wait_icr_idle)(void); 274 275 void (*send_IPI)(int cpu, int vector); 276 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 277 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 278 void (*send_IPI_allbutself)(int vector); 279 void (*send_IPI_all)(int vector); 280 void (*send_IPI_self)(int vector); 281 282 u32 disable_esr; 283 284 enum apic_delivery_modes delivery_mode; 285 bool dest_mode_logical; 286 287 u32 (*calc_dest_apicid)(unsigned int cpu); 288 289 /* ICR related functions */ 290 u64 (*icr_read)(void); 291 void (*icr_write)(u32 low, u32 high); 292 293 /* Probe, setup and smpboot functions */ 294 int (*probe)(void); 295 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 296 int (*apic_id_valid)(u32 apicid); 297 bool (*apic_id_registered)(void); 298 299 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 300 void (*init_apic_ldr)(void); 301 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 302 int (*cpu_present_to_apicid)(int mps_cpu); 303 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 304 305 u32 (*get_apic_id)(unsigned long x); 306 u32 (*set_apic_id)(unsigned int id); 307 308 /* wakeup_secondary_cpu */ 309 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 310 /* wakeup secondary CPU using 64-bit wakeup point */ 311 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); 312 313 char *name; 314 }; 315 316 /* 317 * Pointer to the local APIC driver in use on this system (there's 318 * always just one such driver in use - the kernel decides via an 319 * early probing process which one it picks - and then sticks to it): 320 */ 321 extern struct apic *apic; 322 323 /* 324 * APIC drivers are probed based on how they are listed in the .apicdrivers 325 * section. So the order is important and enforced by the ordering 326 * of different apic driver files in the Makefile. 327 * 328 * For the files having two apic drivers, we use apic_drivers() 329 * to enforce the order with in them. 330 */ 331 #define apic_driver(sym) \ 332 static const struct apic *__apicdrivers_##sym __used \ 333 __aligned(sizeof(struct apic *)) \ 334 __section(".apicdrivers") = { &sym } 335 336 #define apic_drivers(sym1, sym2) \ 337 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 338 __aligned(sizeof(struct apic *)) \ 339 __section(".apicdrivers") = { &sym1, &sym2 } 340 341 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 342 343 /* 344 * APIC functionality to boot other CPUs - only used on SMP: 345 */ 346 #ifdef CONFIG_SMP 347 extern int lapic_can_unplug_cpu(void); 348 #endif 349 350 #ifdef CONFIG_X86_LOCAL_APIC 351 352 static inline u32 apic_read(u32 reg) 353 { 354 return apic->read(reg); 355 } 356 357 static inline void apic_write(u32 reg, u32 val) 358 { 359 apic->write(reg, val); 360 } 361 362 static inline void apic_eoi(void) 363 { 364 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 365 } 366 367 static inline u64 apic_icr_read(void) 368 { 369 return apic->icr_read(); 370 } 371 372 static inline void apic_icr_write(u32 low, u32 high) 373 { 374 apic->icr_write(low, high); 375 } 376 377 static inline void apic_wait_icr_idle(void) 378 { 379 apic->wait_icr_idle(); 380 } 381 382 static inline u32 safe_apic_wait_icr_idle(void) 383 { 384 return apic->safe_wait_icr_idle(); 385 } 386 387 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 388 389 #else /* CONFIG_X86_LOCAL_APIC */ 390 391 static inline u32 apic_read(u32 reg) { return 0; } 392 static inline void apic_write(u32 reg, u32 val) { } 393 static inline void apic_eoi(void) { } 394 static inline u64 apic_icr_read(void) { return 0; } 395 static inline void apic_icr_write(u32 low, u32 high) { } 396 static inline void apic_wait_icr_idle(void) { } 397 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 398 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 399 400 #endif /* CONFIG_X86_LOCAL_APIC */ 401 402 extern void apic_ack_irq(struct irq_data *data); 403 404 static inline void ack_APIC_irq(void) 405 { 406 /* 407 * ack_APIC_irq() actually gets compiled as a single instruction 408 * ... yummie. 409 */ 410 apic_eoi(); 411 } 412 413 414 static inline bool lapic_vector_set_in_irr(unsigned int vector) 415 { 416 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 417 418 return !!(irr & (1U << (vector % 32))); 419 } 420 421 static inline unsigned default_get_apic_id(unsigned long x) 422 { 423 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 424 425 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 426 return (x >> 24) & 0xFF; 427 else 428 return (x >> 24) & 0x0F; 429 } 430 431 /* 432 * Warm reset vector position: 433 */ 434 #define TRAMPOLINE_PHYS_LOW 0x467 435 #define TRAMPOLINE_PHYS_HIGH 0x469 436 437 extern void generic_bigsmp_probe(void); 438 439 #ifdef CONFIG_X86_LOCAL_APIC 440 441 #include <asm/smp.h> 442 443 extern struct apic apic_noop; 444 445 static inline unsigned int read_apic_id(void) 446 { 447 unsigned int reg = apic_read(APIC_ID); 448 449 return apic->get_apic_id(reg); 450 } 451 452 #ifdef CONFIG_X86_64 453 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 454 extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); 455 extern int default_acpi_madt_oem_check(char *, char *); 456 extern void x86_64_probe_apic(void); 457 #else 458 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } 459 static inline void x86_64_probe_apic(void) { } 460 #endif 461 462 extern int default_apic_id_valid(u32 apicid); 463 464 extern u32 apic_default_calc_apicid(unsigned int cpu); 465 extern u32 apic_flat_calc_apicid(unsigned int cpu); 466 467 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 468 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 469 extern int default_cpu_present_to_apicid(int mps_cpu); 470 471 #else /* CONFIG_X86_LOCAL_APIC */ 472 473 static inline unsigned int read_apic_id(void) { return 0; } 474 475 #endif /* !CONFIG_X86_LOCAL_APIC */ 476 477 #ifdef CONFIG_SMP 478 void apic_smt_update(void); 479 #else 480 static inline void apic_smt_update(void) { } 481 #endif 482 483 struct msi_msg; 484 struct irq_cfg; 485 486 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 487 bool dmar); 488 489 extern void ioapic_zap_locks(void); 490 491 #endif /* _ASM_X86_APIC_H */ 492