1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/delay.h> 6 #include <linux/pm.h> 7 8 #include <asm/alternative.h> 9 #include <asm/cpufeature.h> 10 #include <asm/processor.h> 11 #include <asm/apicdef.h> 12 #include <asm/atomic.h> 13 #include <asm/fixmap.h> 14 #include <asm/mpspec.h> 15 #include <asm/system.h> 16 #include <asm/msr.h> 17 18 #define ARCH_APICTIMER_STOPS_ON_C3 1 19 20 /* 21 * Debugging macros 22 */ 23 #define APIC_QUIET 0 24 #define APIC_VERBOSE 1 25 #define APIC_DEBUG 2 26 27 /* 28 * Define the default level of output to be very little 29 * This can be turned up by using apic=verbose for more 30 * information and apic=debug for _lots_ of information. 31 * apic_verbosity is defined in apic.c 32 */ 33 #define apic_printk(v, s, a...) do { \ 34 if ((v) <= apic_verbosity) \ 35 printk(s, ##a); \ 36 } while (0) 37 38 39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 40 extern void generic_apic_probe(void); 41 #else 42 static inline void generic_apic_probe(void) 43 { 44 } 45 #endif 46 47 #ifdef CONFIG_X86_LOCAL_APIC 48 49 extern unsigned int apic_verbosity; 50 extern int local_apic_timer_c2_ok; 51 52 extern int disable_apic; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * Basic functions accessing APICs. 70 */ 71 #ifdef CONFIG_PARAVIRT 72 #include <asm/paravirt.h> 73 #else 74 #define setup_boot_clock setup_boot_APIC_clock 75 #define setup_secondary_clock setup_secondary_APIC_clock 76 #endif 77 78 #ifdef CONFIG_X86_VSMP 79 extern int is_vsmp_box(void); 80 #else 81 static inline int is_vsmp_box(void) 82 { 83 return 0; 84 } 85 #endif 86 extern void xapic_wait_icr_idle(void); 87 extern u32 safe_xapic_wait_icr_idle(void); 88 extern void xapic_icr_write(u32, u32); 89 extern int setup_profiling_timer(unsigned int); 90 91 static inline void native_apic_mem_write(u32 reg, u32 v) 92 { 93 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 94 95 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 96 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 97 ASM_OUTPUT2("0" (v), "m" (*addr))); 98 } 99 100 static inline u32 native_apic_mem_read(u32 reg) 101 { 102 return *((volatile u32 *)(APIC_BASE + reg)); 103 } 104 105 extern void native_apic_wait_icr_idle(void); 106 extern u32 native_safe_apic_wait_icr_idle(void); 107 extern void native_apic_icr_write(u32 low, u32 id); 108 extern u64 native_apic_icr_read(void); 109 110 #ifdef CONFIG_X86_X2APIC 111 /* 112 * Make previous memory operations globally visible before 113 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 114 * mfence for this. 115 */ 116 static inline void x2apic_wrmsr_fence(void) 117 { 118 asm volatile("mfence" : : : "memory"); 119 } 120 121 static inline void native_apic_msr_write(u32 reg, u32 v) 122 { 123 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 124 reg == APIC_LVR) 125 return; 126 127 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 128 } 129 130 static inline u32 native_apic_msr_read(u32 reg) 131 { 132 u32 low, high; 133 134 if (reg == APIC_DFR) 135 return -1; 136 137 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); 138 return low; 139 } 140 141 static inline void native_x2apic_wait_icr_idle(void) 142 { 143 /* no need to wait for icr idle in x2apic */ 144 return; 145 } 146 147 static inline u32 native_safe_x2apic_wait_icr_idle(void) 148 { 149 /* no need to wait for icr idle in x2apic */ 150 return 0; 151 } 152 153 static inline void native_x2apic_icr_write(u32 low, u32 id) 154 { 155 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 156 } 157 158 static inline u64 native_x2apic_icr_read(void) 159 { 160 unsigned long val; 161 162 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 163 return val; 164 } 165 166 extern int x2apic, x2apic_phys; 167 extern void check_x2apic(void); 168 extern void enable_x2apic(void); 169 extern void enable_IR_x2apic(void); 170 extern void x2apic_icr_write(u32 low, u32 id); 171 static inline int x2apic_enabled(void) 172 { 173 int msr, msr2; 174 175 if (!cpu_has_x2apic) 176 return 0; 177 178 rdmsr(MSR_IA32_APICBASE, msr, msr2); 179 if (msr & X2APIC_ENABLE) 180 return 1; 181 return 0; 182 } 183 #else 184 static inline void check_x2apic(void) 185 { 186 } 187 static inline void enable_x2apic(void) 188 { 189 } 190 static inline void enable_IR_x2apic(void) 191 { 192 } 193 static inline int x2apic_enabled(void) 194 { 195 return 0; 196 } 197 198 #define x2apic 0 199 200 #endif 201 202 extern int get_physical_broadcast(void); 203 204 #ifdef CONFIG_X86_X2APIC 205 static inline void ack_x2APIC_irq(void) 206 { 207 /* Docs say use 0 for future compatibility */ 208 native_apic_msr_write(APIC_EOI, 0); 209 } 210 #endif 211 212 extern int lapic_get_maxlvt(void); 213 extern void clear_local_APIC(void); 214 extern void connect_bsp_APIC(void); 215 extern void disconnect_bsp_APIC(int virt_wire_setup); 216 extern void disable_local_APIC(void); 217 extern void lapic_shutdown(void); 218 extern int verify_local_APIC(void); 219 extern void cache_APIC_registers(void); 220 extern void sync_Arb_IDs(void); 221 extern void init_bsp_APIC(void); 222 extern void setup_local_APIC(void); 223 extern void end_local_APIC_setup(void); 224 extern void init_apic_mappings(void); 225 extern void setup_boot_APIC_clock(void); 226 extern void setup_secondary_APIC_clock(void); 227 extern int APIC_init_uniprocessor(void); 228 extern void enable_NMI_through_LVT0(void); 229 230 /* 231 * On 32bit this is mach-xxx local 232 */ 233 #ifdef CONFIG_X86_64 234 extern void early_init_lapic_mapping(void); 235 extern int apic_is_clustered_box(void); 236 #else 237 static inline int apic_is_clustered_box(void) 238 { 239 return 0; 240 } 241 #endif 242 243 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 244 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 245 246 247 #else /* !CONFIG_X86_LOCAL_APIC */ 248 static inline void lapic_shutdown(void) { } 249 #define local_apic_timer_c2_ok 1 250 static inline void init_apic_mappings(void) { } 251 static inline void disable_local_APIC(void) { } 252 253 #endif /* !CONFIG_X86_LOCAL_APIC */ 254 255 #ifdef CONFIG_X86_64 256 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 257 #else 258 259 #endif 260 261 /* 262 * Copyright 2004 James Cleverdon, IBM. 263 * Subject to the GNU Public License, v.2 264 * 265 * Generic APIC sub-arch data struct. 266 * 267 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 268 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 269 * James Cleverdon. 270 */ 271 struct apic { 272 char *name; 273 274 int (*probe)(void); 275 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 276 int (*apic_id_registered)(void); 277 278 u32 irq_delivery_mode; 279 u32 irq_dest_mode; 280 281 const struct cpumask *(*target_cpus)(void); 282 283 int disable_esr; 284 285 int dest_logical; 286 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid); 287 unsigned long (*check_apicid_present)(int apicid); 288 289 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 290 void (*init_apic_ldr)(void); 291 292 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map); 293 294 void (*setup_apic_routing)(void); 295 int (*multi_timer_check)(int apic, int irq); 296 int (*apicid_to_node)(int logical_apicid); 297 int (*cpu_to_logical_apicid)(int cpu); 298 int (*cpu_present_to_apicid)(int mps_cpu); 299 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid); 300 void (*setup_portio_remap)(void); 301 int (*check_phys_apicid_present)(int boot_cpu_physical_apicid); 302 void (*enable_apic_mode)(void); 303 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 304 305 /* 306 * When one of the next two hooks returns 1 the apic 307 * is switched to this. Essentially they are additional 308 * probe functions: 309 */ 310 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 311 312 unsigned int (*get_apic_id)(unsigned long x); 313 unsigned long (*set_apic_id)(unsigned int id); 314 unsigned long apic_id_mask; 315 316 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 317 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 318 const struct cpumask *andmask); 319 320 /* ipi */ 321 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 322 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 323 int vector); 324 void (*send_IPI_allbutself)(int vector); 325 void (*send_IPI_all)(int vector); 326 void (*send_IPI_self)(int vector); 327 328 /* wakeup_secondary_cpu */ 329 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 330 331 int trampoline_phys_low; 332 int trampoline_phys_high; 333 334 void (*wait_for_init_deassert)(atomic_t *deassert); 335 void (*smp_callin_clear_local_apic)(void); 336 void (*inquire_remote_apic)(int apicid); 337 338 /* apic ops */ 339 u32 (*read)(u32 reg); 340 void (*write)(u32 reg, u32 v); 341 u64 (*icr_read)(void); 342 void (*icr_write)(u32 low, u32 high); 343 void (*wait_icr_idle)(void); 344 u32 (*safe_wait_icr_idle)(void); 345 }; 346 347 /* 348 * Pointer to the local APIC driver in use on this system (there's 349 * always just one such driver in use - the kernel decides via an 350 * early probing process which one it picks - and then sticks to it): 351 */ 352 extern struct apic *apic; 353 354 /* 355 * APIC functionality to boot other CPUs - only used on SMP: 356 */ 357 #ifdef CONFIG_SMP 358 extern atomic_t init_deasserted; 359 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 360 #endif 361 362 static inline u32 apic_read(u32 reg) 363 { 364 return apic->read(reg); 365 } 366 367 static inline void apic_write(u32 reg, u32 val) 368 { 369 apic->write(reg, val); 370 } 371 372 static inline u64 apic_icr_read(void) 373 { 374 return apic->icr_read(); 375 } 376 377 static inline void apic_icr_write(u32 low, u32 high) 378 { 379 apic->icr_write(low, high); 380 } 381 382 static inline void apic_wait_icr_idle(void) 383 { 384 apic->wait_icr_idle(); 385 } 386 387 static inline u32 safe_apic_wait_icr_idle(void) 388 { 389 return apic->safe_wait_icr_idle(); 390 } 391 392 393 static inline void ack_APIC_irq(void) 394 { 395 #ifdef CONFIG_X86_LOCAL_APIC 396 /* 397 * ack_APIC_irq() actually gets compiled as a single instruction 398 * ... yummie. 399 */ 400 401 /* Docs say use 0 for future compatibility */ 402 apic_write(APIC_EOI, 0); 403 #endif 404 } 405 406 static inline unsigned default_get_apic_id(unsigned long x) 407 { 408 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 409 410 if (APIC_XAPIC(ver)) 411 return (x >> 24) & 0xFF; 412 else 413 return (x >> 24) & 0x0F; 414 } 415 416 /* 417 * Warm reset vector default position: 418 */ 419 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 420 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 421 422 #ifdef CONFIG_X86_64 423 extern struct apic apic_flat; 424 extern struct apic apic_physflat; 425 extern struct apic apic_x2apic_cluster; 426 extern struct apic apic_x2apic_phys; 427 extern int default_acpi_madt_oem_check(char *, char *); 428 429 extern void apic_send_IPI_self(int vector); 430 431 extern struct apic apic_x2apic_uv_x; 432 DECLARE_PER_CPU(int, x2apic_extra_bits); 433 434 extern int default_cpu_present_to_apicid(int mps_cpu); 435 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); 436 #endif 437 438 static inline void default_wait_for_init_deassert(atomic_t *deassert) 439 { 440 while (!atomic_read(deassert)) 441 cpu_relax(); 442 return; 443 } 444 445 extern void generic_bigsmp_probe(void); 446 447 448 #ifdef CONFIG_X86_LOCAL_APIC 449 450 #include <asm/smp.h> 451 452 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 453 454 static inline const struct cpumask *default_target_cpus(void) 455 { 456 #ifdef CONFIG_SMP 457 return cpu_online_mask; 458 #else 459 return cpumask_of(0); 460 #endif 461 } 462 463 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 464 465 466 static inline unsigned int read_apic_id(void) 467 { 468 unsigned int reg; 469 470 reg = apic_read(APIC_ID); 471 472 return apic->get_apic_id(reg); 473 } 474 475 extern void default_setup_apic_routing(void); 476 477 #ifdef CONFIG_X86_32 478 /* 479 * Set up the logical destination ID. 480 * 481 * Intel recommends to set DFR, LDR and TPR before enabling 482 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 483 * document number 292116). So here it goes... 484 */ 485 extern void default_init_apic_ldr(void); 486 487 static inline int default_apic_id_registered(void) 488 { 489 return physid_isset(read_apic_id(), phys_cpu_present_map); 490 } 491 492 static inline unsigned int 493 default_cpu_mask_to_apicid(const struct cpumask *cpumask) 494 { 495 return cpumask_bits(cpumask)[0]; 496 } 497 498 static inline unsigned int 499 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 500 const struct cpumask *andmask) 501 { 502 unsigned long mask1 = cpumask_bits(cpumask)[0]; 503 unsigned long mask2 = cpumask_bits(andmask)[0]; 504 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 505 506 return (unsigned int)(mask1 & mask2 & mask3); 507 } 508 509 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 510 { 511 return cpuid_apic >> index_msb; 512 } 513 514 extern int default_apicid_to_node(int logical_apicid); 515 516 #endif 517 518 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) 519 { 520 return physid_isset(apicid, bitmap); 521 } 522 523 static inline unsigned long default_check_apicid_present(int bit) 524 { 525 return physid_isset(bit, phys_cpu_present_map); 526 } 527 528 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) 529 { 530 return phys_map; 531 } 532 533 /* Mapping from cpu number to logical apicid */ 534 static inline int default_cpu_to_logical_apicid(int cpu) 535 { 536 return 1 << cpu; 537 } 538 539 static inline int __default_cpu_present_to_apicid(int mps_cpu) 540 { 541 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 542 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 543 else 544 return BAD_APICID; 545 } 546 547 static inline int 548 __default_check_phys_apicid_present(int boot_cpu_physical_apicid) 549 { 550 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); 551 } 552 553 #ifdef CONFIG_X86_32 554 static inline int default_cpu_present_to_apicid(int mps_cpu) 555 { 556 return __default_cpu_present_to_apicid(mps_cpu); 557 } 558 559 static inline int 560 default_check_phys_apicid_present(int boot_cpu_physical_apicid) 561 { 562 return __default_check_phys_apicid_present(boot_cpu_physical_apicid); 563 } 564 #else 565 extern int default_cpu_present_to_apicid(int mps_cpu); 566 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); 567 #endif 568 569 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) 570 { 571 return physid_mask_of_physid(phys_apicid); 572 } 573 574 #endif /* CONFIG_X86_LOCAL_APIC */ 575 576 #ifdef CONFIG_X86_32 577 extern u8 cpu_2_logical_apicid[NR_CPUS]; 578 #endif 579 580 #endif /* _ASM_X86_APIC_H */ 581