1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 6 #include <asm/alternative.h> 7 #include <asm/cpufeature.h> 8 #include <asm/apicdef.h> 9 #include <linux/atomic.h> 10 #include <asm/fixmap.h> 11 #include <asm/mpspec.h> 12 #include <asm/msr.h> 13 14 #define ARCH_APICTIMER_STOPS_ON_C3 1 15 16 /* 17 * Debugging macros 18 */ 19 #define APIC_QUIET 0 20 #define APIC_VERBOSE 1 21 #define APIC_DEBUG 2 22 23 /* Macros for apic_extnmi which controls external NMI masking */ 24 #define APIC_EXTNMI_BSP 0 /* Default */ 25 #define APIC_EXTNMI_ALL 1 26 #define APIC_EXTNMI_NONE 2 27 28 /* 29 * Define the default level of output to be very little 30 * This can be turned up by using apic=verbose for more 31 * information and apic=debug for _lots_ of information. 32 * apic_verbosity is defined in apic.c 33 */ 34 #define apic_printk(v, s, a...) do { \ 35 if ((v) <= apic_verbosity) \ 36 printk(s, ##a); \ 37 } while (0) 38 39 40 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 41 extern void generic_apic_probe(void); 42 #else 43 static inline void generic_apic_probe(void) 44 { 45 } 46 #endif 47 48 #ifdef CONFIG_X86_LOCAL_APIC 49 50 extern unsigned int apic_verbosity; 51 extern int local_apic_timer_c2_ok; 52 53 extern int disable_apic; 54 extern unsigned int lapic_timer_frequency; 55 56 extern enum apic_intr_mode_id apic_intr_mode; 57 enum apic_intr_mode_id { 58 APIC_PIC, 59 APIC_VIRTUAL_WIRE, 60 APIC_VIRTUAL_WIRE_NO_CONFIG, 61 APIC_SYMMETRIC_IO, 62 APIC_SYMMETRIC_IO_NO_ROUTING 63 }; 64 65 #ifdef CONFIG_SMP 66 extern void __inquire_remote_apic(int apicid); 67 #else /* CONFIG_SMP */ 68 static inline void __inquire_remote_apic(int apicid) 69 { 70 } 71 #endif /* CONFIG_SMP */ 72 73 static inline void default_inquire_remote_apic(int apicid) 74 { 75 if (apic_verbosity >= APIC_DEBUG) 76 __inquire_remote_apic(apicid); 77 } 78 79 /* 80 * With 82489DX we can't rely on apic feature bit 81 * retrieved via cpuid but still have to deal with 82 * such an apic chip so we assume that SMP configuration 83 * is found from MP table (64bit case uses ACPI mostly 84 * which set smp presence flag as well so we are safe 85 * to use this helper too). 86 */ 87 static inline bool apic_from_smp_config(void) 88 { 89 return smp_found_config && !disable_apic; 90 } 91 92 /* 93 * Basic functions accessing APICs. 94 */ 95 #ifdef CONFIG_PARAVIRT 96 #include <asm/paravirt.h> 97 #endif 98 99 extern int setup_profiling_timer(unsigned int); 100 101 static inline void native_apic_mem_write(u32 reg, u32 v) 102 { 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108 } 109 110 static inline u32 native_apic_mem_read(u32 reg) 111 { 112 return *((volatile u32 *)(APIC_BASE + reg)); 113 } 114 115 extern void native_apic_wait_icr_idle(void); 116 extern u32 native_safe_apic_wait_icr_idle(void); 117 extern void native_apic_icr_write(u32 low, u32 id); 118 extern u64 native_apic_icr_read(void); 119 120 static inline bool apic_is_x2apic_enabled(void) 121 { 122 u64 msr; 123 124 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 125 return false; 126 return msr & X2APIC_ENABLE; 127 } 128 129 extern void enable_IR_x2apic(void); 130 131 extern int get_physical_broadcast(void); 132 133 extern int lapic_get_maxlvt(void); 134 extern void clear_local_APIC(void); 135 extern void disconnect_bsp_APIC(int virt_wire_setup); 136 extern void disable_local_APIC(void); 137 extern void lapic_shutdown(void); 138 extern void sync_Arb_IDs(void); 139 extern void init_bsp_APIC(void); 140 extern void apic_intr_mode_init(void); 141 extern void setup_local_APIC(void); 142 extern void init_apic_mappings(void); 143 void register_lapic_address(unsigned long address); 144 extern void setup_boot_APIC_clock(void); 145 extern void setup_secondary_APIC_clock(void); 146 extern void lapic_update_tsc_freq(void); 147 148 #ifdef CONFIG_X86_64 149 static inline int apic_force_enable(unsigned long addr) 150 { 151 return -1; 152 } 153 #else 154 extern int apic_force_enable(unsigned long addr); 155 #endif 156 157 extern void apic_bsp_setup(bool upmode); 158 extern void apic_ap_setup(void); 159 160 /* 161 * On 32bit this is mach-xxx local 162 */ 163 #ifdef CONFIG_X86_64 164 extern int apic_is_clustered_box(void); 165 #else 166 static inline int apic_is_clustered_box(void) 167 { 168 return 0; 169 } 170 #endif 171 172 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 173 extern void lapic_assign_system_vectors(void); 174 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 175 extern void lapic_online(void); 176 extern void lapic_offline(void); 177 178 #else /* !CONFIG_X86_LOCAL_APIC */ 179 static inline void lapic_shutdown(void) { } 180 #define local_apic_timer_c2_ok 1 181 static inline void init_apic_mappings(void) { } 182 static inline void disable_local_APIC(void) { } 183 # define setup_boot_APIC_clock x86_init_noop 184 # define setup_secondary_APIC_clock x86_init_noop 185 static inline void lapic_update_tsc_freq(void) { } 186 static inline void init_bsp_APIC(void) { } 187 static inline void apic_intr_mode_init(void) { } 188 static inline void lapic_assign_system_vectors(void) { } 189 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 190 #endif /* !CONFIG_X86_LOCAL_APIC */ 191 192 #ifdef CONFIG_X86_X2APIC 193 /* 194 * Make previous memory operations globally visible before 195 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 196 * mfence for this. 197 */ 198 static inline void x2apic_wrmsr_fence(void) 199 { 200 asm volatile("mfence" : : : "memory"); 201 } 202 203 static inline void native_apic_msr_write(u32 reg, u32 v) 204 { 205 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 206 reg == APIC_LVR) 207 return; 208 209 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 210 } 211 212 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 213 { 214 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 215 } 216 217 static inline u32 native_apic_msr_read(u32 reg) 218 { 219 u64 msr; 220 221 if (reg == APIC_DFR) 222 return -1; 223 224 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 225 return (u32)msr; 226 } 227 228 static inline void native_x2apic_wait_icr_idle(void) 229 { 230 /* no need to wait for icr idle in x2apic */ 231 return; 232 } 233 234 static inline u32 native_safe_x2apic_wait_icr_idle(void) 235 { 236 /* no need to wait for icr idle in x2apic */ 237 return 0; 238 } 239 240 static inline void native_x2apic_icr_write(u32 low, u32 id) 241 { 242 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 243 } 244 245 static inline u64 native_x2apic_icr_read(void) 246 { 247 unsigned long val; 248 249 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 250 return val; 251 } 252 253 extern int x2apic_mode; 254 extern int x2apic_phys; 255 extern void __init check_x2apic(void); 256 extern void x2apic_setup(void); 257 static inline int x2apic_enabled(void) 258 { 259 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 260 } 261 262 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 263 #else /* !CONFIG_X86_X2APIC */ 264 static inline void check_x2apic(void) { } 265 static inline void x2apic_setup(void) { } 266 static inline int x2apic_enabled(void) { return 0; } 267 268 #define x2apic_mode (0) 269 #define x2apic_supported() (0) 270 #endif /* !CONFIG_X86_X2APIC */ 271 272 struct irq_data; 273 274 /* 275 * Copyright 2004 James Cleverdon, IBM. 276 * Subject to the GNU Public License, v.2 277 * 278 * Generic APIC sub-arch data struct. 279 * 280 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 281 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 282 * James Cleverdon. 283 */ 284 struct apic { 285 /* Hotpath functions first */ 286 void (*eoi_write)(u32 reg, u32 v); 287 void (*native_eoi_write)(u32 reg, u32 v); 288 void (*write)(u32 reg, u32 v); 289 u32 (*read)(u32 reg); 290 291 /* IPI related functions */ 292 void (*wait_icr_idle)(void); 293 u32 (*safe_wait_icr_idle)(void); 294 295 void (*send_IPI)(int cpu, int vector); 296 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 297 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 298 void (*send_IPI_allbutself)(int vector); 299 void (*send_IPI_all)(int vector); 300 void (*send_IPI_self)(int vector); 301 302 /* dest_logical is used by the IPI functions */ 303 u32 dest_logical; 304 u32 disable_esr; 305 u32 irq_delivery_mode; 306 u32 irq_dest_mode; 307 308 /* Functions and data related to vector allocation */ 309 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 310 const struct cpumask *mask); 311 int (*cpu_mask_to_apicid)(const struct cpumask *cpumask, 312 struct irq_data *irqdata, 313 unsigned int *apicid); 314 u32 (*calc_dest_apicid)(unsigned int cpu); 315 316 /* ICR related functions */ 317 u64 (*icr_read)(void); 318 void (*icr_write)(u32 low, u32 high); 319 320 /* Probe, setup and smpboot functions */ 321 int (*probe)(void); 322 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 323 int (*apic_id_valid)(int apicid); 324 int (*apic_id_registered)(void); 325 326 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 327 void (*init_apic_ldr)(void); 328 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 329 void (*setup_apic_routing)(void); 330 int (*cpu_present_to_apicid)(int mps_cpu); 331 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 332 int (*check_phys_apicid_present)(int phys_apicid); 333 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 334 335 u32 (*get_apic_id)(unsigned long x); 336 u32 (*set_apic_id)(unsigned int id); 337 338 /* wakeup_secondary_cpu */ 339 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 340 341 void (*inquire_remote_apic)(int apicid); 342 343 #ifdef CONFIG_X86_32 344 /* 345 * Called very early during boot from get_smp_config(). It should 346 * return the logical apicid. x86_[bios]_cpu_to_apicid is 347 * initialized before this function is called. 348 * 349 * If logical apicid can't be determined that early, the function 350 * may return BAD_APICID. Logical apicid will be configured after 351 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 352 * won't be applied properly during early boot in this case. 353 */ 354 int (*x86_32_early_logical_apicid)(int cpu); 355 #endif 356 char *name; 357 }; 358 359 /* 360 * Pointer to the local APIC driver in use on this system (there's 361 * always just one such driver in use - the kernel decides via an 362 * early probing process which one it picks - and then sticks to it): 363 */ 364 extern struct apic *apic; 365 366 /* 367 * APIC drivers are probed based on how they are listed in the .apicdrivers 368 * section. So the order is important and enforced by the ordering 369 * of different apic driver files in the Makefile. 370 * 371 * For the files having two apic drivers, we use apic_drivers() 372 * to enforce the order with in them. 373 */ 374 #define apic_driver(sym) \ 375 static const struct apic *__apicdrivers_##sym __used \ 376 __aligned(sizeof(struct apic *)) \ 377 __section(.apicdrivers) = { &sym } 378 379 #define apic_drivers(sym1, sym2) \ 380 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 381 __aligned(sizeof(struct apic *)) \ 382 __section(.apicdrivers) = { &sym1, &sym2 } 383 384 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 385 386 /* 387 * APIC functionality to boot other CPUs - only used on SMP: 388 */ 389 #ifdef CONFIG_SMP 390 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 391 extern int lapic_can_unplug_cpu(void); 392 #endif 393 394 #ifdef CONFIG_X86_LOCAL_APIC 395 396 static inline u32 apic_read(u32 reg) 397 { 398 return apic->read(reg); 399 } 400 401 static inline void apic_write(u32 reg, u32 val) 402 { 403 apic->write(reg, val); 404 } 405 406 static inline void apic_eoi(void) 407 { 408 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 409 } 410 411 static inline u64 apic_icr_read(void) 412 { 413 return apic->icr_read(); 414 } 415 416 static inline void apic_icr_write(u32 low, u32 high) 417 { 418 apic->icr_write(low, high); 419 } 420 421 static inline void apic_wait_icr_idle(void) 422 { 423 apic->wait_icr_idle(); 424 } 425 426 static inline u32 safe_apic_wait_icr_idle(void) 427 { 428 return apic->safe_wait_icr_idle(); 429 } 430 431 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 432 433 #else /* CONFIG_X86_LOCAL_APIC */ 434 435 static inline u32 apic_read(u32 reg) { return 0; } 436 static inline void apic_write(u32 reg, u32 val) { } 437 static inline void apic_eoi(void) { } 438 static inline u64 apic_icr_read(void) { return 0; } 439 static inline void apic_icr_write(u32 low, u32 high) { } 440 static inline void apic_wait_icr_idle(void) { } 441 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 442 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 443 444 #endif /* CONFIG_X86_LOCAL_APIC */ 445 446 static inline void ack_APIC_irq(void) 447 { 448 /* 449 * ack_APIC_irq() actually gets compiled as a single instruction 450 * ... yummie. 451 */ 452 apic_eoi(); 453 } 454 455 static inline unsigned default_get_apic_id(unsigned long x) 456 { 457 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 458 459 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 460 return (x >> 24) & 0xFF; 461 else 462 return (x >> 24) & 0x0F; 463 } 464 465 /* 466 * Warm reset vector position: 467 */ 468 #define TRAMPOLINE_PHYS_LOW 0x467 469 #define TRAMPOLINE_PHYS_HIGH 0x469 470 471 #ifdef CONFIG_X86_64 472 extern void apic_send_IPI_self(int vector); 473 474 DECLARE_PER_CPU(int, x2apic_extra_bits); 475 #endif 476 477 extern void generic_bigsmp_probe(void); 478 479 #ifdef CONFIG_X86_LOCAL_APIC 480 481 #include <asm/smp.h> 482 483 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 484 485 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 486 487 extern struct apic apic_noop; 488 489 static inline unsigned int read_apic_id(void) 490 { 491 unsigned int reg = apic_read(APIC_ID); 492 493 return apic->get_apic_id(reg); 494 } 495 496 extern int default_apic_id_valid(int apicid); 497 extern int default_acpi_madt_oem_check(char *, char *); 498 extern void default_setup_apic_routing(void); 499 500 extern u32 apic_default_calc_apicid(unsigned int cpu); 501 extern u32 apic_flat_calc_apicid(unsigned int cpu); 502 503 extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask, 504 struct irq_data *irqdata, 505 unsigned int *apicid); 506 extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask, 507 struct irq_data *irqdata, 508 unsigned int *apicid); 509 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 510 extern void flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 511 const struct cpumask *mask); 512 extern void default_vector_allocation_domain(int cpu, struct cpumask *retmask, 513 const struct cpumask *mask); 514 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 515 extern int default_cpu_present_to_apicid(int mps_cpu); 516 extern int default_check_phys_apicid_present(int phys_apicid); 517 518 #endif /* CONFIG_X86_LOCAL_APIC */ 519 520 extern void irq_enter(void); 521 extern void irq_exit(void); 522 523 static inline void entering_irq(void) 524 { 525 irq_enter(); 526 } 527 528 static inline void entering_ack_irq(void) 529 { 530 entering_irq(); 531 ack_APIC_irq(); 532 } 533 534 static inline void ipi_entering_ack_irq(void) 535 { 536 irq_enter(); 537 ack_APIC_irq(); 538 } 539 540 static inline void exiting_irq(void) 541 { 542 irq_exit(); 543 } 544 545 static inline void exiting_ack_irq(void) 546 { 547 ack_APIC_irq(); 548 irq_exit(); 549 } 550 551 extern void ioapic_zap_locks(void); 552 553 #endif /* _ASM_X86_APIC_H */ 554