1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/pm.h> 5 #include <linux/delay.h> 6 7 #include <asm/alternative.h> 8 #include <asm/fixmap.h> 9 #include <asm/apicdef.h> 10 #include <asm/processor.h> 11 #include <asm/system.h> 12 #include <asm/cpufeature.h> 13 #include <asm/msr.h> 14 15 #define ARCH_APICTIMER_STOPS_ON_C3 1 16 17 /* 18 * Debugging macros 19 */ 20 #define APIC_QUIET 0 21 #define APIC_VERBOSE 1 22 #define APIC_DEBUG 2 23 24 /* 25 * Define the default level of output to be very little 26 * This can be turned up by using apic=verbose for more 27 * information and apic=debug for _lots_ of information. 28 * apic_verbosity is defined in apic.c 29 */ 30 #define apic_printk(v, s, a...) do { \ 31 if ((v) <= apic_verbosity) \ 32 printk(s, ##a); \ 33 } while (0) 34 35 36 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 37 extern void generic_apic_probe(void); 38 #else 39 static inline void generic_apic_probe(void) 40 { 41 } 42 #endif 43 44 #ifdef CONFIG_X86_LOCAL_APIC 45 46 extern unsigned int apic_verbosity; 47 extern int local_apic_timer_c2_ok; 48 49 extern int disable_apic; 50 51 #ifdef CONFIG_SMP 52 extern void __inquire_remote_apic(int apicid); 53 #else /* CONFIG_SMP */ 54 static inline void __inquire_remote_apic(int apicid) 55 { 56 } 57 #endif /* CONFIG_SMP */ 58 59 static inline void default_inquire_remote_apic(int apicid) 60 { 61 if (apic_verbosity >= APIC_DEBUG) 62 __inquire_remote_apic(apicid); 63 } 64 65 /* 66 * Basic functions accessing APICs. 67 */ 68 #ifdef CONFIG_PARAVIRT 69 #include <asm/paravirt.h> 70 #else 71 #define setup_boot_clock setup_boot_APIC_clock 72 #define setup_secondary_clock setup_secondary_APIC_clock 73 #endif 74 75 extern int is_vsmp_box(void); 76 extern void xapic_wait_icr_idle(void); 77 extern u32 safe_xapic_wait_icr_idle(void); 78 extern void xapic_icr_write(u32, u32); 79 extern int setup_profiling_timer(unsigned int); 80 81 static inline void native_apic_mem_write(u32 reg, u32 v) 82 { 83 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 84 85 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 86 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 87 ASM_OUTPUT2("0" (v), "m" (*addr))); 88 } 89 90 static inline u32 native_apic_mem_read(u32 reg) 91 { 92 return *((volatile u32 *)(APIC_BASE + reg)); 93 } 94 95 extern void native_apic_wait_icr_idle(void); 96 extern u32 native_safe_apic_wait_icr_idle(void); 97 extern void native_apic_icr_write(u32 low, u32 id); 98 extern u64 native_apic_icr_read(void); 99 100 #ifdef CONFIG_X86_X2APIC 101 static inline void native_apic_msr_write(u32 reg, u32 v) 102 { 103 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 104 reg == APIC_LVR) 105 return; 106 107 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 108 } 109 110 static inline u32 native_apic_msr_read(u32 reg) 111 { 112 u32 low, high; 113 114 if (reg == APIC_DFR) 115 return -1; 116 117 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); 118 return low; 119 } 120 121 static inline void native_x2apic_wait_icr_idle(void) 122 { 123 /* no need to wait for icr idle in x2apic */ 124 return; 125 } 126 127 static inline u32 native_safe_x2apic_wait_icr_idle(void) 128 { 129 /* no need to wait for icr idle in x2apic */ 130 return 0; 131 } 132 133 static inline void native_x2apic_icr_write(u32 low, u32 id) 134 { 135 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 136 } 137 138 static inline u64 native_x2apic_icr_read(void) 139 { 140 unsigned long val; 141 142 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 143 return val; 144 } 145 146 extern int x2apic; 147 extern void check_x2apic(void); 148 extern void enable_x2apic(void); 149 extern void enable_IR_x2apic(void); 150 extern void x2apic_icr_write(u32 low, u32 id); 151 static inline int x2apic_enabled(void) 152 { 153 int msr, msr2; 154 155 if (!cpu_has_x2apic) 156 return 0; 157 158 rdmsr(MSR_IA32_APICBASE, msr, msr2); 159 if (msr & X2APIC_ENABLE) 160 return 1; 161 return 0; 162 } 163 #else 164 static inline void check_x2apic(void) 165 { 166 } 167 static inline void enable_x2apic(void) 168 { 169 } 170 static inline void enable_IR_x2apic(void) 171 { 172 } 173 static inline int x2apic_enabled(void) 174 { 175 return 0; 176 } 177 #endif 178 179 extern int get_physical_broadcast(void); 180 181 #ifdef CONFIG_X86_X2APIC 182 static inline void ack_x2APIC_irq(void) 183 { 184 /* Docs say use 0 for future compatibility */ 185 native_apic_msr_write(APIC_EOI, 0); 186 } 187 #endif 188 189 extern int lapic_get_maxlvt(void); 190 extern void clear_local_APIC(void); 191 extern void connect_bsp_APIC(void); 192 extern void disconnect_bsp_APIC(int virt_wire_setup); 193 extern void disable_local_APIC(void); 194 extern void lapic_shutdown(void); 195 extern int verify_local_APIC(void); 196 extern void cache_APIC_registers(void); 197 extern void sync_Arb_IDs(void); 198 extern void init_bsp_APIC(void); 199 extern void setup_local_APIC(void); 200 extern void end_local_APIC_setup(void); 201 extern void init_apic_mappings(void); 202 extern void setup_boot_APIC_clock(void); 203 extern void setup_secondary_APIC_clock(void); 204 extern int APIC_init_uniprocessor(void); 205 extern void enable_NMI_through_LVT0(void); 206 207 /* 208 * On 32bit this is mach-xxx local 209 */ 210 #ifdef CONFIG_X86_64 211 extern void early_init_lapic_mapping(void); 212 extern int apic_is_clustered_box(void); 213 #else 214 static inline int apic_is_clustered_box(void) 215 { 216 return 0; 217 } 218 #endif 219 220 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 221 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 222 223 224 #else /* !CONFIG_X86_LOCAL_APIC */ 225 static inline void lapic_shutdown(void) { } 226 #define local_apic_timer_c2_ok 1 227 static inline void init_apic_mappings(void) { } 228 static inline void disable_local_APIC(void) { } 229 230 #endif /* !CONFIG_X86_LOCAL_APIC */ 231 232 #ifdef CONFIG_X86_64 233 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 234 #else 235 236 #endif 237 238 #endif /* _ASM_X86_APIC_H */ 239