1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/idle.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* Macros for apic_extnmi which controls external NMI masking */ 27 #define APIC_EXTNMI_BSP 0 /* Default */ 28 #define APIC_EXTNMI_ALL 1 29 #define APIC_EXTNMI_NONE 2 30 31 /* 32 * Define the default level of output to be very little 33 * This can be turned up by using apic=verbose for more 34 * information and apic=debug for _lots_ of information. 35 * apic_verbosity is defined in apic.c 36 */ 37 #define apic_printk(v, s, a...) do { \ 38 if ((v) <= apic_verbosity) \ 39 printk(s, ##a); \ 40 } while (0) 41 42 43 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 44 extern void generic_apic_probe(void); 45 #else 46 static inline void generic_apic_probe(void) 47 { 48 } 49 #endif 50 51 #ifdef CONFIG_X86_LOCAL_APIC 52 53 extern unsigned int apic_verbosity; 54 extern int local_apic_timer_c2_ok; 55 56 extern int disable_apic; 57 extern unsigned int lapic_timer_frequency; 58 59 #ifdef CONFIG_SMP 60 extern void __inquire_remote_apic(int apicid); 61 #else /* CONFIG_SMP */ 62 static inline void __inquire_remote_apic(int apicid) 63 { 64 } 65 #endif /* CONFIG_SMP */ 66 67 static inline void default_inquire_remote_apic(int apicid) 68 { 69 if (apic_verbosity >= APIC_DEBUG) 70 __inquire_remote_apic(apicid); 71 } 72 73 /* 74 * With 82489DX we can't rely on apic feature bit 75 * retrieved via cpuid but still have to deal with 76 * such an apic chip so we assume that SMP configuration 77 * is found from MP table (64bit case uses ACPI mostly 78 * which set smp presence flag as well so we are safe 79 * to use this helper too). 80 */ 81 static inline bool apic_from_smp_config(void) 82 { 83 return smp_found_config && !disable_apic; 84 } 85 86 /* 87 * Basic functions accessing APICs. 88 */ 89 #ifdef CONFIG_PARAVIRT 90 #include <asm/paravirt.h> 91 #endif 92 93 extern int setup_profiling_timer(unsigned int); 94 95 static inline void native_apic_mem_write(u32 reg, u32 v) 96 { 97 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 98 99 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 100 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 101 ASM_OUTPUT2("0" (v), "m" (*addr))); 102 } 103 104 static inline u32 native_apic_mem_read(u32 reg) 105 { 106 return *((volatile u32 *)(APIC_BASE + reg)); 107 } 108 109 extern void native_apic_wait_icr_idle(void); 110 extern u32 native_safe_apic_wait_icr_idle(void); 111 extern void native_apic_icr_write(u32 low, u32 id); 112 extern u64 native_apic_icr_read(void); 113 114 static inline bool apic_is_x2apic_enabled(void) 115 { 116 u64 msr; 117 118 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 119 return false; 120 return msr & X2APIC_ENABLE; 121 } 122 123 extern void enable_IR_x2apic(void); 124 125 extern int get_physical_broadcast(void); 126 127 extern int lapic_get_maxlvt(void); 128 extern void clear_local_APIC(void); 129 extern void disconnect_bsp_APIC(int virt_wire_setup); 130 extern void disable_local_APIC(void); 131 extern void lapic_shutdown(void); 132 extern void sync_Arb_IDs(void); 133 extern void init_bsp_APIC(void); 134 extern void setup_local_APIC(void); 135 extern void init_apic_mappings(void); 136 void register_lapic_address(unsigned long address); 137 extern void setup_boot_APIC_clock(void); 138 extern void setup_secondary_APIC_clock(void); 139 extern int APIC_init_uniprocessor(void); 140 141 #ifdef CONFIG_X86_64 142 static inline int apic_force_enable(unsigned long addr) 143 { 144 return -1; 145 } 146 #else 147 extern int apic_force_enable(unsigned long addr); 148 #endif 149 150 extern int apic_bsp_setup(bool upmode); 151 extern void apic_ap_setup(void); 152 153 /* 154 * On 32bit this is mach-xxx local 155 */ 156 #ifdef CONFIG_X86_64 157 extern int apic_is_clustered_box(void); 158 #else 159 static inline int apic_is_clustered_box(void) 160 { 161 return 0; 162 } 163 #endif 164 165 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 166 167 #else /* !CONFIG_X86_LOCAL_APIC */ 168 static inline void lapic_shutdown(void) { } 169 #define local_apic_timer_c2_ok 1 170 static inline void init_apic_mappings(void) { } 171 static inline void disable_local_APIC(void) { } 172 # define setup_boot_APIC_clock x86_init_noop 173 # define setup_secondary_APIC_clock x86_init_noop 174 #endif /* !CONFIG_X86_LOCAL_APIC */ 175 176 #ifdef CONFIG_X86_X2APIC 177 /* 178 * Make previous memory operations globally visible before 179 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 180 * mfence for this. 181 */ 182 static inline void x2apic_wrmsr_fence(void) 183 { 184 asm volatile("mfence" : : : "memory"); 185 } 186 187 static inline void native_apic_msr_write(u32 reg, u32 v) 188 { 189 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 190 reg == APIC_LVR) 191 return; 192 193 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 194 } 195 196 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 197 { 198 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 199 } 200 201 static inline u32 native_apic_msr_read(u32 reg) 202 { 203 u64 msr; 204 205 if (reg == APIC_DFR) 206 return -1; 207 208 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 209 return (u32)msr; 210 } 211 212 static inline void native_x2apic_wait_icr_idle(void) 213 { 214 /* no need to wait for icr idle in x2apic */ 215 return; 216 } 217 218 static inline u32 native_safe_x2apic_wait_icr_idle(void) 219 { 220 /* no need to wait for icr idle in x2apic */ 221 return 0; 222 } 223 224 static inline void native_x2apic_icr_write(u32 low, u32 id) 225 { 226 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 227 } 228 229 static inline u64 native_x2apic_icr_read(void) 230 { 231 unsigned long val; 232 233 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 234 return val; 235 } 236 237 extern int x2apic_mode; 238 extern int x2apic_phys; 239 extern void __init check_x2apic(void); 240 extern void x2apic_setup(void); 241 static inline int x2apic_enabled(void) 242 { 243 return cpu_has_x2apic && apic_is_x2apic_enabled(); 244 } 245 246 #define x2apic_supported() (cpu_has_x2apic) 247 #else /* !CONFIG_X86_X2APIC */ 248 static inline void check_x2apic(void) { } 249 static inline void x2apic_setup(void) { } 250 static inline int x2apic_enabled(void) { return 0; } 251 252 #define x2apic_mode (0) 253 #define x2apic_supported() (0) 254 #endif /* !CONFIG_X86_X2APIC */ 255 256 #ifdef CONFIG_X86_64 257 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 258 #else 259 260 #endif 261 262 /* 263 * Copyright 2004 James Cleverdon, IBM. 264 * Subject to the GNU Public License, v.2 265 * 266 * Generic APIC sub-arch data struct. 267 * 268 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 269 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 270 * James Cleverdon. 271 */ 272 struct apic { 273 char *name; 274 275 int (*probe)(void); 276 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 277 int (*apic_id_valid)(int apicid); 278 int (*apic_id_registered)(void); 279 280 u32 irq_delivery_mode; 281 u32 irq_dest_mode; 282 283 const struct cpumask *(*target_cpus)(void); 284 285 int disable_esr; 286 287 int dest_logical; 288 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 289 290 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 291 const struct cpumask *mask); 292 void (*init_apic_ldr)(void); 293 294 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 295 296 void (*setup_apic_routing)(void); 297 int (*cpu_present_to_apicid)(int mps_cpu); 298 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 299 int (*check_phys_apicid_present)(int phys_apicid); 300 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 301 302 unsigned int (*get_apic_id)(unsigned long x); 303 unsigned long (*set_apic_id)(unsigned int id); 304 unsigned long apic_id_mask; 305 306 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 307 const struct cpumask *andmask, 308 unsigned int *apicid); 309 310 /* ipi */ 311 void (*send_IPI)(int cpu, int vector); 312 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 313 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 314 int vector); 315 void (*send_IPI_allbutself)(int vector); 316 void (*send_IPI_all)(int vector); 317 void (*send_IPI_self)(int vector); 318 319 /* wakeup_secondary_cpu */ 320 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 321 322 void (*inquire_remote_apic)(int apicid); 323 324 /* apic ops */ 325 u32 (*read)(u32 reg); 326 void (*write)(u32 reg, u32 v); 327 /* 328 * ->eoi_write() has the same signature as ->write(). 329 * 330 * Drivers can support both ->eoi_write() and ->write() by passing the same 331 * callback value. Kernel can override ->eoi_write() and fall back 332 * on write for EOI. 333 */ 334 void (*eoi_write)(u32 reg, u32 v); 335 u64 (*icr_read)(void); 336 void (*icr_write)(u32 low, u32 high); 337 void (*wait_icr_idle)(void); 338 u32 (*safe_wait_icr_idle)(void); 339 340 #ifdef CONFIG_X86_32 341 /* 342 * Called very early during boot from get_smp_config(). It should 343 * return the logical apicid. x86_[bios]_cpu_to_apicid is 344 * initialized before this function is called. 345 * 346 * If logical apicid can't be determined that early, the function 347 * may return BAD_APICID. Logical apicid will be configured after 348 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 349 * won't be applied properly during early boot in this case. 350 */ 351 int (*x86_32_early_logical_apicid)(int cpu); 352 #endif 353 }; 354 355 /* 356 * Pointer to the local APIC driver in use on this system (there's 357 * always just one such driver in use - the kernel decides via an 358 * early probing process which one it picks - and then sticks to it): 359 */ 360 extern struct apic *apic; 361 362 /* 363 * APIC drivers are probed based on how they are listed in the .apicdrivers 364 * section. So the order is important and enforced by the ordering 365 * of different apic driver files in the Makefile. 366 * 367 * For the files having two apic drivers, we use apic_drivers() 368 * to enforce the order with in them. 369 */ 370 #define apic_driver(sym) \ 371 static const struct apic *__apicdrivers_##sym __used \ 372 __aligned(sizeof(struct apic *)) \ 373 __section(.apicdrivers) = { &sym } 374 375 #define apic_drivers(sym1, sym2) \ 376 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 377 __aligned(sizeof(struct apic *)) \ 378 __section(.apicdrivers) = { &sym1, &sym2 } 379 380 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 381 382 /* 383 * APIC functionality to boot other CPUs - only used on SMP: 384 */ 385 #ifdef CONFIG_SMP 386 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 387 #endif 388 389 #ifdef CONFIG_X86_LOCAL_APIC 390 391 static inline u32 apic_read(u32 reg) 392 { 393 return apic->read(reg); 394 } 395 396 static inline void apic_write(u32 reg, u32 val) 397 { 398 apic->write(reg, val); 399 } 400 401 static inline void apic_eoi(void) 402 { 403 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 404 } 405 406 static inline u64 apic_icr_read(void) 407 { 408 return apic->icr_read(); 409 } 410 411 static inline void apic_icr_write(u32 low, u32 high) 412 { 413 apic->icr_write(low, high); 414 } 415 416 static inline void apic_wait_icr_idle(void) 417 { 418 apic->wait_icr_idle(); 419 } 420 421 static inline u32 safe_apic_wait_icr_idle(void) 422 { 423 return apic->safe_wait_icr_idle(); 424 } 425 426 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 427 428 #else /* CONFIG_X86_LOCAL_APIC */ 429 430 static inline u32 apic_read(u32 reg) { return 0; } 431 static inline void apic_write(u32 reg, u32 val) { } 432 static inline void apic_eoi(void) { } 433 static inline u64 apic_icr_read(void) { return 0; } 434 static inline void apic_icr_write(u32 low, u32 high) { } 435 static inline void apic_wait_icr_idle(void) { } 436 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 437 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 438 439 #endif /* CONFIG_X86_LOCAL_APIC */ 440 441 static inline void ack_APIC_irq(void) 442 { 443 /* 444 * ack_APIC_irq() actually gets compiled as a single instruction 445 * ... yummie. 446 */ 447 apic_eoi(); 448 } 449 450 static inline unsigned default_get_apic_id(unsigned long x) 451 { 452 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 453 454 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 455 return (x >> 24) & 0xFF; 456 else 457 return (x >> 24) & 0x0F; 458 } 459 460 /* 461 * Warm reset vector position: 462 */ 463 #define TRAMPOLINE_PHYS_LOW 0x467 464 #define TRAMPOLINE_PHYS_HIGH 0x469 465 466 #ifdef CONFIG_X86_64 467 extern void apic_send_IPI_self(int vector); 468 469 DECLARE_PER_CPU(int, x2apic_extra_bits); 470 471 extern int default_cpu_present_to_apicid(int mps_cpu); 472 extern int default_check_phys_apicid_present(int phys_apicid); 473 #endif 474 475 extern void generic_bigsmp_probe(void); 476 477 478 #ifdef CONFIG_X86_LOCAL_APIC 479 480 #include <asm/smp.h> 481 482 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 483 484 static inline const struct cpumask *default_target_cpus(void) 485 { 486 #ifdef CONFIG_SMP 487 return cpu_online_mask; 488 #else 489 return cpumask_of(0); 490 #endif 491 } 492 493 static inline const struct cpumask *online_target_cpus(void) 494 { 495 return cpu_online_mask; 496 } 497 498 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 499 500 501 static inline unsigned int read_apic_id(void) 502 { 503 unsigned int reg; 504 505 reg = apic_read(APIC_ID); 506 507 return apic->get_apic_id(reg); 508 } 509 510 static inline int default_apic_id_valid(int apicid) 511 { 512 return (apicid < 255); 513 } 514 515 extern int default_acpi_madt_oem_check(char *, char *); 516 517 extern void default_setup_apic_routing(void); 518 519 extern struct apic apic_noop; 520 521 #ifdef CONFIG_X86_32 522 523 static inline int noop_x86_32_early_logical_apicid(int cpu) 524 { 525 return BAD_APICID; 526 } 527 528 /* 529 * Set up the logical destination ID. 530 * 531 * Intel recommends to set DFR, LDR and TPR before enabling 532 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 533 * document number 292116). So here it goes... 534 */ 535 extern void default_init_apic_ldr(void); 536 537 static inline int default_apic_id_registered(void) 538 { 539 return physid_isset(read_apic_id(), phys_cpu_present_map); 540 } 541 542 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 543 { 544 return cpuid_apic >> index_msb; 545 } 546 547 #endif 548 549 static inline int 550 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 551 const struct cpumask *andmask, 552 unsigned int *apicid) 553 { 554 unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 555 cpumask_bits(andmask)[0] & 556 cpumask_bits(cpu_online_mask)[0] & 557 APIC_ALL_CPUS; 558 559 if (likely(cpu_mask)) { 560 *apicid = (unsigned int)cpu_mask; 561 return 0; 562 } else { 563 return -EINVAL; 564 } 565 } 566 567 extern int 568 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 569 const struct cpumask *andmask, 570 unsigned int *apicid); 571 572 static inline void 573 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 574 const struct cpumask *mask) 575 { 576 /* Careful. Some cpus do not strictly honor the set of cpus 577 * specified in the interrupt destination when using lowest 578 * priority interrupt delivery mode. 579 * 580 * In particular there was a hyperthreading cpu observed to 581 * deliver interrupts to the wrong hyperthread when only one 582 * hyperthread was specified in the interrupt desitination. 583 */ 584 cpumask_clear(retmask); 585 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 586 } 587 588 static inline void 589 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 590 const struct cpumask *mask) 591 { 592 cpumask_copy(retmask, cpumask_of(cpu)); 593 } 594 595 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 596 { 597 return physid_isset(apicid, *map); 598 } 599 600 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 601 { 602 *retmap = *phys_map; 603 } 604 605 static inline int __default_cpu_present_to_apicid(int mps_cpu) 606 { 607 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 608 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 609 else 610 return BAD_APICID; 611 } 612 613 static inline int 614 __default_check_phys_apicid_present(int phys_apicid) 615 { 616 return physid_isset(phys_apicid, phys_cpu_present_map); 617 } 618 619 #ifdef CONFIG_X86_32 620 static inline int default_cpu_present_to_apicid(int mps_cpu) 621 { 622 return __default_cpu_present_to_apicid(mps_cpu); 623 } 624 625 static inline int 626 default_check_phys_apicid_present(int phys_apicid) 627 { 628 return __default_check_phys_apicid_present(phys_apicid); 629 } 630 #else 631 extern int default_cpu_present_to_apicid(int mps_cpu); 632 extern int default_check_phys_apicid_present(int phys_apicid); 633 #endif 634 635 #endif /* CONFIG_X86_LOCAL_APIC */ 636 extern void irq_enter(void); 637 extern void irq_exit(void); 638 639 static inline void entering_irq(void) 640 { 641 irq_enter(); 642 exit_idle(); 643 } 644 645 static inline void entering_ack_irq(void) 646 { 647 ack_APIC_irq(); 648 entering_irq(); 649 } 650 651 static inline void ipi_entering_ack_irq(void) 652 { 653 ack_APIC_irq(); 654 irq_enter(); 655 } 656 657 static inline void exiting_irq(void) 658 { 659 irq_exit(); 660 } 661 662 static inline void exiting_ack_irq(void) 663 { 664 irq_exit(); 665 /* Ack only at the end to avoid potential reentry */ 666 ack_APIC_irq(); 667 } 668 669 extern void ioapic_zap_locks(void); 670 671 #endif /* _ASM_X86_APIC_H */ 672