1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 6 #include <asm/alternative.h> 7 #include <asm/cpufeature.h> 8 #include <asm/apicdef.h> 9 #include <linux/atomic.h> 10 #include <asm/fixmap.h> 11 #include <asm/mpspec.h> 12 #include <asm/msr.h> 13 14 #define ARCH_APICTIMER_STOPS_ON_C3 1 15 16 /* 17 * Debugging macros 18 */ 19 #define APIC_QUIET 0 20 #define APIC_VERBOSE 1 21 #define APIC_DEBUG 2 22 23 /* Macros for apic_extnmi which controls external NMI masking */ 24 #define APIC_EXTNMI_BSP 0 /* Default */ 25 #define APIC_EXTNMI_ALL 1 26 #define APIC_EXTNMI_NONE 2 27 28 /* 29 * Define the default level of output to be very little 30 * This can be turned up by using apic=verbose for more 31 * information and apic=debug for _lots_ of information. 32 * apic_verbosity is defined in apic.c 33 */ 34 #define apic_printk(v, s, a...) do { \ 35 if ((v) <= apic_verbosity) \ 36 printk(s, ##a); \ 37 } while (0) 38 39 40 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 41 extern void generic_apic_probe(void); 42 #else 43 static inline void generic_apic_probe(void) 44 { 45 } 46 #endif 47 48 #ifdef CONFIG_X86_LOCAL_APIC 49 50 extern unsigned int apic_verbosity; 51 extern int local_apic_timer_c2_ok; 52 53 extern int disable_apic; 54 extern unsigned int lapic_timer_frequency; 55 56 extern enum apic_intr_mode_id apic_intr_mode; 57 enum apic_intr_mode_id { 58 APIC_PIC, 59 APIC_VIRTUAL_WIRE, 60 APIC_VIRTUAL_WIRE_NO_CONFIG, 61 APIC_SYMMETRIC_IO, 62 APIC_SYMMETRIC_IO_NO_ROUTING 63 }; 64 65 #ifdef CONFIG_SMP 66 extern void __inquire_remote_apic(int apicid); 67 #else /* CONFIG_SMP */ 68 static inline void __inquire_remote_apic(int apicid) 69 { 70 } 71 #endif /* CONFIG_SMP */ 72 73 static inline void default_inquire_remote_apic(int apicid) 74 { 75 if (apic_verbosity >= APIC_DEBUG) 76 __inquire_remote_apic(apicid); 77 } 78 79 /* 80 * With 82489DX we can't rely on apic feature bit 81 * retrieved via cpuid but still have to deal with 82 * such an apic chip so we assume that SMP configuration 83 * is found from MP table (64bit case uses ACPI mostly 84 * which set smp presence flag as well so we are safe 85 * to use this helper too). 86 */ 87 static inline bool apic_from_smp_config(void) 88 { 89 return smp_found_config && !disable_apic; 90 } 91 92 /* 93 * Basic functions accessing APICs. 94 */ 95 #ifdef CONFIG_PARAVIRT 96 #include <asm/paravirt.h> 97 #endif 98 99 extern int setup_profiling_timer(unsigned int); 100 101 static inline void native_apic_mem_write(u32 reg, u32 v) 102 { 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108 } 109 110 static inline u32 native_apic_mem_read(u32 reg) 111 { 112 return *((volatile u32 *)(APIC_BASE + reg)); 113 } 114 115 extern void native_apic_wait_icr_idle(void); 116 extern u32 native_safe_apic_wait_icr_idle(void); 117 extern void native_apic_icr_write(u32 low, u32 id); 118 extern u64 native_apic_icr_read(void); 119 120 static inline bool apic_is_x2apic_enabled(void) 121 { 122 u64 msr; 123 124 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 125 return false; 126 return msr & X2APIC_ENABLE; 127 } 128 129 extern void enable_IR_x2apic(void); 130 131 extern int get_physical_broadcast(void); 132 133 extern int lapic_get_maxlvt(void); 134 extern void clear_local_APIC(void); 135 extern void disconnect_bsp_APIC(int virt_wire_setup); 136 extern void disable_local_APIC(void); 137 extern void lapic_shutdown(void); 138 extern void sync_Arb_IDs(void); 139 extern void init_bsp_APIC(void); 140 extern void apic_intr_mode_init(void); 141 extern void init_apic_mappings(void); 142 void register_lapic_address(unsigned long address); 143 extern void setup_boot_APIC_clock(void); 144 extern void setup_secondary_APIC_clock(void); 145 extern void lapic_update_tsc_freq(void); 146 147 #ifdef CONFIG_X86_64 148 static inline int apic_force_enable(unsigned long addr) 149 { 150 return -1; 151 } 152 #else 153 extern int apic_force_enable(unsigned long addr); 154 #endif 155 156 extern void apic_bsp_setup(bool upmode); 157 extern void apic_ap_setup(void); 158 159 /* 160 * On 32bit this is mach-xxx local 161 */ 162 #ifdef CONFIG_X86_64 163 extern int apic_is_clustered_box(void); 164 #else 165 static inline int apic_is_clustered_box(void) 166 { 167 return 0; 168 } 169 #endif 170 171 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 172 extern void lapic_assign_system_vectors(void); 173 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 174 extern void lapic_online(void); 175 extern void lapic_offline(void); 176 177 #else /* !CONFIG_X86_LOCAL_APIC */ 178 static inline void lapic_shutdown(void) { } 179 #define local_apic_timer_c2_ok 1 180 static inline void init_apic_mappings(void) { } 181 static inline void disable_local_APIC(void) { } 182 # define setup_boot_APIC_clock x86_init_noop 183 # define setup_secondary_APIC_clock x86_init_noop 184 static inline void lapic_update_tsc_freq(void) { } 185 static inline void init_bsp_APIC(void) { } 186 static inline void apic_intr_mode_init(void) { } 187 static inline void lapic_assign_system_vectors(void) { } 188 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 189 #endif /* !CONFIG_X86_LOCAL_APIC */ 190 191 #ifdef CONFIG_X86_X2APIC 192 /* 193 * Make previous memory operations globally visible before 194 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 195 * mfence for this. 196 */ 197 static inline void x2apic_wrmsr_fence(void) 198 { 199 asm volatile("mfence" : : : "memory"); 200 } 201 202 static inline void native_apic_msr_write(u32 reg, u32 v) 203 { 204 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 205 reg == APIC_LVR) 206 return; 207 208 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 209 } 210 211 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 212 { 213 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 214 } 215 216 static inline u32 native_apic_msr_read(u32 reg) 217 { 218 u64 msr; 219 220 if (reg == APIC_DFR) 221 return -1; 222 223 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 224 return (u32)msr; 225 } 226 227 static inline void native_x2apic_wait_icr_idle(void) 228 { 229 /* no need to wait for icr idle in x2apic */ 230 return; 231 } 232 233 static inline u32 native_safe_x2apic_wait_icr_idle(void) 234 { 235 /* no need to wait for icr idle in x2apic */ 236 return 0; 237 } 238 239 static inline void native_x2apic_icr_write(u32 low, u32 id) 240 { 241 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 242 } 243 244 static inline u64 native_x2apic_icr_read(void) 245 { 246 unsigned long val; 247 248 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 249 return val; 250 } 251 252 extern int x2apic_mode; 253 extern int x2apic_phys; 254 extern void __init check_x2apic(void); 255 extern void x2apic_setup(void); 256 static inline int x2apic_enabled(void) 257 { 258 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 259 } 260 261 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 262 #else /* !CONFIG_X86_X2APIC */ 263 static inline void check_x2apic(void) { } 264 static inline void x2apic_setup(void) { } 265 static inline int x2apic_enabled(void) { return 0; } 266 267 #define x2apic_mode (0) 268 #define x2apic_supported() (0) 269 #endif /* !CONFIG_X86_X2APIC */ 270 271 struct irq_data; 272 273 /* 274 * Copyright 2004 James Cleverdon, IBM. 275 * Subject to the GNU Public License, v.2 276 * 277 * Generic APIC sub-arch data struct. 278 * 279 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 280 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 281 * James Cleverdon. 282 */ 283 struct apic { 284 /* Hotpath functions first */ 285 void (*eoi_write)(u32 reg, u32 v); 286 void (*native_eoi_write)(u32 reg, u32 v); 287 void (*write)(u32 reg, u32 v); 288 u32 (*read)(u32 reg); 289 290 /* IPI related functions */ 291 void (*wait_icr_idle)(void); 292 u32 (*safe_wait_icr_idle)(void); 293 294 void (*send_IPI)(int cpu, int vector); 295 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 296 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 297 void (*send_IPI_allbutself)(int vector); 298 void (*send_IPI_all)(int vector); 299 void (*send_IPI_self)(int vector); 300 301 /* dest_logical is used by the IPI functions */ 302 u32 dest_logical; 303 u32 disable_esr; 304 u32 irq_delivery_mode; 305 u32 irq_dest_mode; 306 307 /* Functions and data related to vector allocation */ 308 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 309 const struct cpumask *mask); 310 int (*cpu_mask_to_apicid)(const struct cpumask *cpumask, 311 struct irq_data *irqdata, 312 unsigned int *apicid); 313 u32 (*calc_dest_apicid)(unsigned int cpu); 314 315 /* ICR related functions */ 316 u64 (*icr_read)(void); 317 void (*icr_write)(u32 low, u32 high); 318 319 /* Probe, setup and smpboot functions */ 320 int (*probe)(void); 321 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 322 int (*apic_id_valid)(int apicid); 323 int (*apic_id_registered)(void); 324 325 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 326 void (*init_apic_ldr)(void); 327 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 328 void (*setup_apic_routing)(void); 329 int (*cpu_present_to_apicid)(int mps_cpu); 330 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 331 int (*check_phys_apicid_present)(int phys_apicid); 332 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 333 334 u32 (*get_apic_id)(unsigned long x); 335 u32 (*set_apic_id)(unsigned int id); 336 337 /* wakeup_secondary_cpu */ 338 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 339 340 void (*inquire_remote_apic)(int apicid); 341 342 #ifdef CONFIG_X86_32 343 /* 344 * Called very early during boot from get_smp_config(). It should 345 * return the logical apicid. x86_[bios]_cpu_to_apicid is 346 * initialized before this function is called. 347 * 348 * If logical apicid can't be determined that early, the function 349 * may return BAD_APICID. Logical apicid will be configured after 350 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 351 * won't be applied properly during early boot in this case. 352 */ 353 int (*x86_32_early_logical_apicid)(int cpu); 354 #endif 355 char *name; 356 }; 357 358 /* 359 * Pointer to the local APIC driver in use on this system (there's 360 * always just one such driver in use - the kernel decides via an 361 * early probing process which one it picks - and then sticks to it): 362 */ 363 extern struct apic *apic; 364 365 /* 366 * APIC drivers are probed based on how they are listed in the .apicdrivers 367 * section. So the order is important and enforced by the ordering 368 * of different apic driver files in the Makefile. 369 * 370 * For the files having two apic drivers, we use apic_drivers() 371 * to enforce the order with in them. 372 */ 373 #define apic_driver(sym) \ 374 static const struct apic *__apicdrivers_##sym __used \ 375 __aligned(sizeof(struct apic *)) \ 376 __section(.apicdrivers) = { &sym } 377 378 #define apic_drivers(sym1, sym2) \ 379 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 380 __aligned(sizeof(struct apic *)) \ 381 __section(.apicdrivers) = { &sym1, &sym2 } 382 383 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 384 385 /* 386 * APIC functionality to boot other CPUs - only used on SMP: 387 */ 388 #ifdef CONFIG_SMP 389 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 390 extern int lapic_can_unplug_cpu(void); 391 #endif 392 393 #ifdef CONFIG_X86_LOCAL_APIC 394 395 static inline u32 apic_read(u32 reg) 396 { 397 return apic->read(reg); 398 } 399 400 static inline void apic_write(u32 reg, u32 val) 401 { 402 apic->write(reg, val); 403 } 404 405 static inline void apic_eoi(void) 406 { 407 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 408 } 409 410 static inline u64 apic_icr_read(void) 411 { 412 return apic->icr_read(); 413 } 414 415 static inline void apic_icr_write(u32 low, u32 high) 416 { 417 apic->icr_write(low, high); 418 } 419 420 static inline void apic_wait_icr_idle(void) 421 { 422 apic->wait_icr_idle(); 423 } 424 425 static inline u32 safe_apic_wait_icr_idle(void) 426 { 427 return apic->safe_wait_icr_idle(); 428 } 429 430 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 431 432 #else /* CONFIG_X86_LOCAL_APIC */ 433 434 static inline u32 apic_read(u32 reg) { return 0; } 435 static inline void apic_write(u32 reg, u32 val) { } 436 static inline void apic_eoi(void) { } 437 static inline u64 apic_icr_read(void) { return 0; } 438 static inline void apic_icr_write(u32 low, u32 high) { } 439 static inline void apic_wait_icr_idle(void) { } 440 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 441 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 442 443 #endif /* CONFIG_X86_LOCAL_APIC */ 444 445 static inline void ack_APIC_irq(void) 446 { 447 /* 448 * ack_APIC_irq() actually gets compiled as a single instruction 449 * ... yummie. 450 */ 451 apic_eoi(); 452 } 453 454 static inline unsigned default_get_apic_id(unsigned long x) 455 { 456 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 457 458 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 459 return (x >> 24) & 0xFF; 460 else 461 return (x >> 24) & 0x0F; 462 } 463 464 /* 465 * Warm reset vector position: 466 */ 467 #define TRAMPOLINE_PHYS_LOW 0x467 468 #define TRAMPOLINE_PHYS_HIGH 0x469 469 470 #ifdef CONFIG_X86_64 471 extern void apic_send_IPI_self(int vector); 472 473 DECLARE_PER_CPU(int, x2apic_extra_bits); 474 #endif 475 476 extern void generic_bigsmp_probe(void); 477 478 #ifdef CONFIG_X86_LOCAL_APIC 479 480 #include <asm/smp.h> 481 482 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 483 484 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 485 486 extern struct apic apic_noop; 487 488 static inline unsigned int read_apic_id(void) 489 { 490 unsigned int reg = apic_read(APIC_ID); 491 492 return apic->get_apic_id(reg); 493 } 494 495 extern int default_apic_id_valid(int apicid); 496 extern int default_acpi_madt_oem_check(char *, char *); 497 extern void default_setup_apic_routing(void); 498 499 extern u32 apic_default_calc_apicid(unsigned int cpu); 500 extern u32 apic_flat_calc_apicid(unsigned int cpu); 501 502 extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask, 503 struct irq_data *irqdata, 504 unsigned int *apicid); 505 extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask, 506 struct irq_data *irqdata, 507 unsigned int *apicid); 508 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 509 extern void flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 510 const struct cpumask *mask); 511 extern void default_vector_allocation_domain(int cpu, struct cpumask *retmask, 512 const struct cpumask *mask); 513 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 514 extern int default_cpu_present_to_apicid(int mps_cpu); 515 extern int default_check_phys_apicid_present(int phys_apicid); 516 517 #endif /* CONFIG_X86_LOCAL_APIC */ 518 519 extern void irq_enter(void); 520 extern void irq_exit(void); 521 522 static inline void entering_irq(void) 523 { 524 irq_enter(); 525 } 526 527 static inline void entering_ack_irq(void) 528 { 529 entering_irq(); 530 ack_APIC_irq(); 531 } 532 533 static inline void ipi_entering_ack_irq(void) 534 { 535 irq_enter(); 536 ack_APIC_irq(); 537 } 538 539 static inline void exiting_irq(void) 540 { 541 irq_exit(); 542 } 543 544 static inline void exiting_ack_irq(void) 545 { 546 ack_APIC_irq(); 547 irq_exit(); 548 } 549 550 extern void ioapic_zap_locks(void); 551 552 #endif /* _ASM_X86_APIC_H */ 553