1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/system.h> 15 #include <asm/msr.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* 27 * Define the default level of output to be very little 28 * This can be turned up by using apic=verbose for more 29 * information and apic=debug for _lots_ of information. 30 * apic_verbosity is defined in apic.c 31 */ 32 #define apic_printk(v, s, a...) do { \ 33 if ((v) <= apic_verbosity) \ 34 printk(s, ##a); \ 35 } while (0) 36 37 38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39 extern void generic_apic_probe(void); 40 #else 41 static inline void generic_apic_probe(void) 42 { 43 } 44 #endif 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 48 extern unsigned int apic_verbosity; 49 extern int local_apic_timer_c2_ok; 50 51 extern int disable_apic; 52 extern unsigned int lapic_timer_frequency; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 #ifdef CONFIG_X86_64 89 extern int is_vsmp_box(void); 90 #else 91 static inline int is_vsmp_box(void) 92 { 93 return 0; 94 } 95 #endif 96 extern void xapic_wait_icr_idle(void); 97 extern u32 safe_xapic_wait_icr_idle(void); 98 extern void xapic_icr_write(u32, u32); 99 extern int setup_profiling_timer(unsigned int); 100 101 static inline void native_apic_mem_write(u32 reg, u32 v) 102 { 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108 } 109 110 static inline u32 native_apic_mem_read(u32 reg) 111 { 112 return *((volatile u32 *)(APIC_BASE + reg)); 113 } 114 115 extern void native_apic_wait_icr_idle(void); 116 extern u32 native_safe_apic_wait_icr_idle(void); 117 extern void native_apic_icr_write(u32 low, u32 id); 118 extern u64 native_apic_icr_read(void); 119 120 extern int x2apic_mode; 121 122 #ifdef CONFIG_X86_X2APIC 123 /* 124 * Make previous memory operations globally visible before 125 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 126 * mfence for this. 127 */ 128 static inline void x2apic_wrmsr_fence(void) 129 { 130 asm volatile("mfence" : : : "memory"); 131 } 132 133 static inline void native_apic_msr_write(u32 reg, u32 v) 134 { 135 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 136 reg == APIC_LVR) 137 return; 138 139 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 140 } 141 142 static inline u32 native_apic_msr_read(u32 reg) 143 { 144 u64 msr; 145 146 if (reg == APIC_DFR) 147 return -1; 148 149 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 150 return (u32)msr; 151 } 152 153 static inline void native_x2apic_wait_icr_idle(void) 154 { 155 /* no need to wait for icr idle in x2apic */ 156 return; 157 } 158 159 static inline u32 native_safe_x2apic_wait_icr_idle(void) 160 { 161 /* no need to wait for icr idle in x2apic */ 162 return 0; 163 } 164 165 static inline void native_x2apic_icr_write(u32 low, u32 id) 166 { 167 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 168 } 169 170 static inline u64 native_x2apic_icr_read(void) 171 { 172 unsigned long val; 173 174 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 175 return val; 176 } 177 178 extern int x2apic_phys; 179 extern void check_x2apic(void); 180 extern void enable_x2apic(void); 181 extern void x2apic_icr_write(u32 low, u32 id); 182 static inline int x2apic_enabled(void) 183 { 184 u64 msr; 185 186 if (!cpu_has_x2apic) 187 return 0; 188 189 rdmsrl(MSR_IA32_APICBASE, msr); 190 if (msr & X2APIC_ENABLE) 191 return 1; 192 return 0; 193 } 194 195 #define x2apic_supported() (cpu_has_x2apic) 196 static inline void x2apic_force_phys(void) 197 { 198 x2apic_phys = 1; 199 } 200 #else 201 static inline void check_x2apic(void) 202 { 203 } 204 static inline void enable_x2apic(void) 205 { 206 } 207 static inline int x2apic_enabled(void) 208 { 209 return 0; 210 } 211 static inline void x2apic_force_phys(void) 212 { 213 } 214 215 #define x2apic_preenabled 0 216 #define x2apic_supported() 0 217 #endif 218 219 extern void enable_IR_x2apic(void); 220 221 extern int get_physical_broadcast(void); 222 223 extern int lapic_get_maxlvt(void); 224 extern void clear_local_APIC(void); 225 extern void connect_bsp_APIC(void); 226 extern void disconnect_bsp_APIC(int virt_wire_setup); 227 extern void disable_local_APIC(void); 228 extern void lapic_shutdown(void); 229 extern int verify_local_APIC(void); 230 extern void sync_Arb_IDs(void); 231 extern void init_bsp_APIC(void); 232 extern void setup_local_APIC(void); 233 extern void end_local_APIC_setup(void); 234 extern void bsp_end_local_APIC_setup(void); 235 extern void init_apic_mappings(void); 236 void register_lapic_address(unsigned long address); 237 extern void setup_boot_APIC_clock(void); 238 extern void setup_secondary_APIC_clock(void); 239 extern int APIC_init_uniprocessor(void); 240 extern int apic_force_enable(unsigned long addr); 241 242 /* 243 * On 32bit this is mach-xxx local 244 */ 245 #ifdef CONFIG_X86_64 246 extern int apic_is_clustered_box(void); 247 #else 248 static inline int apic_is_clustered_box(void) 249 { 250 return 0; 251 } 252 #endif 253 254 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 255 256 #else /* !CONFIG_X86_LOCAL_APIC */ 257 static inline void lapic_shutdown(void) { } 258 #define local_apic_timer_c2_ok 1 259 static inline void init_apic_mappings(void) { } 260 static inline void disable_local_APIC(void) { } 261 # define setup_boot_APIC_clock x86_init_noop 262 # define setup_secondary_APIC_clock x86_init_noop 263 #endif /* !CONFIG_X86_LOCAL_APIC */ 264 265 #ifdef CONFIG_X86_64 266 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 267 #else 268 269 #endif 270 271 /* 272 * Copyright 2004 James Cleverdon, IBM. 273 * Subject to the GNU Public License, v.2 274 * 275 * Generic APIC sub-arch data struct. 276 * 277 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 278 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 279 * James Cleverdon. 280 */ 281 struct apic { 282 char *name; 283 284 int (*probe)(void); 285 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 286 int (*apic_id_registered)(void); 287 288 u32 irq_delivery_mode; 289 u32 irq_dest_mode; 290 291 const struct cpumask *(*target_cpus)(void); 292 293 int disable_esr; 294 295 int dest_logical; 296 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 297 unsigned long (*check_apicid_present)(int apicid); 298 299 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 300 void (*init_apic_ldr)(void); 301 302 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 303 304 void (*setup_apic_routing)(void); 305 int (*multi_timer_check)(int apic, int irq); 306 int (*cpu_present_to_apicid)(int mps_cpu); 307 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 308 void (*setup_portio_remap)(void); 309 int (*check_phys_apicid_present)(int phys_apicid); 310 void (*enable_apic_mode)(void); 311 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 312 313 /* 314 * When one of the next two hooks returns 1 the apic 315 * is switched to this. Essentially they are additional 316 * probe functions: 317 */ 318 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 319 320 unsigned int (*get_apic_id)(unsigned long x); 321 unsigned long (*set_apic_id)(unsigned int id); 322 unsigned long apic_id_mask; 323 324 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 325 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 326 const struct cpumask *andmask); 327 328 /* ipi */ 329 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 330 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 331 int vector); 332 void (*send_IPI_allbutself)(int vector); 333 void (*send_IPI_all)(int vector); 334 void (*send_IPI_self)(int vector); 335 336 /* wakeup_secondary_cpu */ 337 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 338 339 int trampoline_phys_low; 340 int trampoline_phys_high; 341 342 void (*wait_for_init_deassert)(atomic_t *deassert); 343 void (*smp_callin_clear_local_apic)(void); 344 void (*inquire_remote_apic)(int apicid); 345 346 /* apic ops */ 347 u32 (*read)(u32 reg); 348 void (*write)(u32 reg, u32 v); 349 u64 (*icr_read)(void); 350 void (*icr_write)(u32 low, u32 high); 351 void (*wait_icr_idle)(void); 352 u32 (*safe_wait_icr_idle)(void); 353 354 #ifdef CONFIG_X86_32 355 /* 356 * Called very early during boot from get_smp_config(). It should 357 * return the logical apicid. x86_[bios]_cpu_to_apicid is 358 * initialized before this function is called. 359 * 360 * If logical apicid can't be determined that early, the function 361 * may return BAD_APICID. Logical apicid will be configured after 362 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 363 * won't be applied properly during early boot in this case. 364 */ 365 int (*x86_32_early_logical_apicid)(int cpu); 366 367 /* 368 * Optional method called from setup_local_APIC() after logical 369 * apicid is guaranteed to be known to initialize apicid -> node 370 * mapping if NUMA initialization hasn't done so already. Don't 371 * add new users. 372 */ 373 int (*x86_32_numa_cpu_node)(int cpu); 374 #endif 375 }; 376 377 /* 378 * Pointer to the local APIC driver in use on this system (there's 379 * always just one such driver in use - the kernel decides via an 380 * early probing process which one it picks - and then sticks to it): 381 */ 382 extern struct apic *apic; 383 384 /* 385 * APIC drivers are probed based on how they are listed in the .apicdrivers 386 * section. So the order is important and enforced by the ordering 387 * of different apic driver files in the Makefile. 388 * 389 * For the files having two apic drivers, we use apic_drivers() 390 * to enforce the order with in them. 391 */ 392 #define apic_driver(sym) \ 393 static struct apic *__apicdrivers_##sym __used \ 394 __aligned(sizeof(struct apic *)) \ 395 __section(.apicdrivers) = { &sym } 396 397 #define apic_drivers(sym1, sym2) \ 398 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 399 __aligned(sizeof(struct apic *)) \ 400 __section(.apicdrivers) = { &sym1, &sym2 } 401 402 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 403 404 /* 405 * APIC functionality to boot other CPUs - only used on SMP: 406 */ 407 #ifdef CONFIG_SMP 408 extern atomic_t init_deasserted; 409 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 410 #endif 411 412 #ifdef CONFIG_X86_LOCAL_APIC 413 414 static inline u32 apic_read(u32 reg) 415 { 416 return apic->read(reg); 417 } 418 419 static inline void apic_write(u32 reg, u32 val) 420 { 421 apic->write(reg, val); 422 } 423 424 static inline u64 apic_icr_read(void) 425 { 426 return apic->icr_read(); 427 } 428 429 static inline void apic_icr_write(u32 low, u32 high) 430 { 431 apic->icr_write(low, high); 432 } 433 434 static inline void apic_wait_icr_idle(void) 435 { 436 apic->wait_icr_idle(); 437 } 438 439 static inline u32 safe_apic_wait_icr_idle(void) 440 { 441 return apic->safe_wait_icr_idle(); 442 } 443 444 #else /* CONFIG_X86_LOCAL_APIC */ 445 446 static inline u32 apic_read(u32 reg) { return 0; } 447 static inline void apic_write(u32 reg, u32 val) { } 448 static inline u64 apic_icr_read(void) { return 0; } 449 static inline void apic_icr_write(u32 low, u32 high) { } 450 static inline void apic_wait_icr_idle(void) { } 451 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 452 453 #endif /* CONFIG_X86_LOCAL_APIC */ 454 455 static inline void ack_APIC_irq(void) 456 { 457 /* 458 * ack_APIC_irq() actually gets compiled as a single instruction 459 * ... yummie. 460 */ 461 462 /* Docs say use 0 for future compatibility */ 463 apic_write(APIC_EOI, 0); 464 } 465 466 static inline unsigned default_get_apic_id(unsigned long x) 467 { 468 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 469 470 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 471 return (x >> 24) & 0xFF; 472 else 473 return (x >> 24) & 0x0F; 474 } 475 476 /* 477 * Warm reset vector default position: 478 */ 479 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 480 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 481 482 #ifdef CONFIG_X86_64 483 extern int default_acpi_madt_oem_check(char *, char *); 484 485 extern void apic_send_IPI_self(int vector); 486 487 DECLARE_PER_CPU(int, x2apic_extra_bits); 488 489 extern int default_cpu_present_to_apicid(int mps_cpu); 490 extern int default_check_phys_apicid_present(int phys_apicid); 491 #endif 492 493 static inline void default_wait_for_init_deassert(atomic_t *deassert) 494 { 495 while (!atomic_read(deassert)) 496 cpu_relax(); 497 return; 498 } 499 500 extern void generic_bigsmp_probe(void); 501 502 503 #ifdef CONFIG_X86_LOCAL_APIC 504 505 #include <asm/smp.h> 506 507 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 508 509 static inline const struct cpumask *default_target_cpus(void) 510 { 511 #ifdef CONFIG_SMP 512 return cpu_online_mask; 513 #else 514 return cpumask_of(0); 515 #endif 516 } 517 518 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 519 520 521 static inline unsigned int read_apic_id(void) 522 { 523 unsigned int reg; 524 525 reg = apic_read(APIC_ID); 526 527 return apic->get_apic_id(reg); 528 } 529 530 extern void default_setup_apic_routing(void); 531 532 extern struct apic apic_noop; 533 534 #ifdef CONFIG_X86_32 535 536 static inline int noop_x86_32_early_logical_apicid(int cpu) 537 { 538 return BAD_APICID; 539 } 540 541 /* 542 * Set up the logical destination ID. 543 * 544 * Intel recommends to set DFR, LDR and TPR before enabling 545 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 546 * document number 292116). So here it goes... 547 */ 548 extern void default_init_apic_ldr(void); 549 550 static inline int default_apic_id_registered(void) 551 { 552 return physid_isset(read_apic_id(), phys_cpu_present_map); 553 } 554 555 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 556 { 557 return cpuid_apic >> index_msb; 558 } 559 560 #endif 561 562 static inline unsigned int 563 default_cpu_mask_to_apicid(const struct cpumask *cpumask) 564 { 565 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 566 } 567 568 static inline unsigned int 569 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 570 const struct cpumask *andmask) 571 { 572 unsigned long mask1 = cpumask_bits(cpumask)[0]; 573 unsigned long mask2 = cpumask_bits(andmask)[0]; 574 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 575 576 return (unsigned int)(mask1 & mask2 & mask3); 577 } 578 579 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 580 { 581 return physid_isset(apicid, *map); 582 } 583 584 static inline unsigned long default_check_apicid_present(int bit) 585 { 586 return physid_isset(bit, phys_cpu_present_map); 587 } 588 589 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 590 { 591 *retmap = *phys_map; 592 } 593 594 static inline int __default_cpu_present_to_apicid(int mps_cpu) 595 { 596 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 597 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 598 else 599 return BAD_APICID; 600 } 601 602 static inline int 603 __default_check_phys_apicid_present(int phys_apicid) 604 { 605 return physid_isset(phys_apicid, phys_cpu_present_map); 606 } 607 608 #ifdef CONFIG_X86_32 609 static inline int default_cpu_present_to_apicid(int mps_cpu) 610 { 611 return __default_cpu_present_to_apicid(mps_cpu); 612 } 613 614 static inline int 615 default_check_phys_apicid_present(int phys_apicid) 616 { 617 return __default_check_phys_apicid_present(phys_apicid); 618 } 619 #else 620 extern int default_cpu_present_to_apicid(int mps_cpu); 621 extern int default_check_phys_apicid_present(int phys_apicid); 622 #endif 623 624 #endif /* CONFIG_X86_LOCAL_APIC */ 625 626 #endif /* _ASM_X86_APIC_H */ 627