1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 6 #include <asm/alternative.h> 7 #include <asm/cpufeature.h> 8 #include <asm/apicdef.h> 9 #include <linux/atomic.h> 10 #include <asm/fixmap.h> 11 #include <asm/mpspec.h> 12 #include <asm/msr.h> 13 14 #define ARCH_APICTIMER_STOPS_ON_C3 1 15 16 /* 17 * Debugging macros 18 */ 19 #define APIC_QUIET 0 20 #define APIC_VERBOSE 1 21 #define APIC_DEBUG 2 22 23 /* Macros for apic_extnmi which controls external NMI masking */ 24 #define APIC_EXTNMI_BSP 0 /* Default */ 25 #define APIC_EXTNMI_ALL 1 26 #define APIC_EXTNMI_NONE 2 27 28 /* 29 * Define the default level of output to be very little 30 * This can be turned up by using apic=verbose for more 31 * information and apic=debug for _lots_ of information. 32 * apic_verbosity is defined in apic.c 33 */ 34 #define apic_printk(v, s, a...) do { \ 35 if ((v) <= apic_verbosity) \ 36 printk(s, ##a); \ 37 } while (0) 38 39 40 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 41 extern void generic_apic_probe(void); 42 #else 43 static inline void generic_apic_probe(void) 44 { 45 } 46 #endif 47 48 #ifdef CONFIG_X86_LOCAL_APIC 49 50 extern unsigned int apic_verbosity; 51 extern int local_apic_timer_c2_ok; 52 53 extern int disable_apic; 54 extern unsigned int lapic_timer_frequency; 55 56 extern enum apic_intr_mode_id apic_intr_mode; 57 enum apic_intr_mode_id { 58 APIC_PIC, 59 APIC_VIRTUAL_WIRE, 60 APIC_VIRTUAL_WIRE_NO_CONFIG, 61 APIC_SYMMETRIC_IO, 62 APIC_SYMMETRIC_IO_NO_ROUTING 63 }; 64 65 #ifdef CONFIG_SMP 66 extern void __inquire_remote_apic(int apicid); 67 #else /* CONFIG_SMP */ 68 static inline void __inquire_remote_apic(int apicid) 69 { 70 } 71 #endif /* CONFIG_SMP */ 72 73 static inline void default_inquire_remote_apic(int apicid) 74 { 75 if (apic_verbosity >= APIC_DEBUG) 76 __inquire_remote_apic(apicid); 77 } 78 79 /* 80 * With 82489DX we can't rely on apic feature bit 81 * retrieved via cpuid but still have to deal with 82 * such an apic chip so we assume that SMP configuration 83 * is found from MP table (64bit case uses ACPI mostly 84 * which set smp presence flag as well so we are safe 85 * to use this helper too). 86 */ 87 static inline bool apic_from_smp_config(void) 88 { 89 return smp_found_config && !disable_apic; 90 } 91 92 /* 93 * Basic functions accessing APICs. 94 */ 95 #ifdef CONFIG_PARAVIRT 96 #include <asm/paravirt.h> 97 #endif 98 99 extern int setup_profiling_timer(unsigned int); 100 101 static inline void native_apic_mem_write(u32 reg, u32 v) 102 { 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108 } 109 110 static inline u32 native_apic_mem_read(u32 reg) 111 { 112 return *((volatile u32 *)(APIC_BASE + reg)); 113 } 114 115 extern void native_apic_wait_icr_idle(void); 116 extern u32 native_safe_apic_wait_icr_idle(void); 117 extern void native_apic_icr_write(u32 low, u32 id); 118 extern u64 native_apic_icr_read(void); 119 120 static inline bool apic_is_x2apic_enabled(void) 121 { 122 u64 msr; 123 124 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 125 return false; 126 return msr & X2APIC_ENABLE; 127 } 128 129 extern void enable_IR_x2apic(void); 130 131 extern int get_physical_broadcast(void); 132 133 extern int lapic_get_maxlvt(void); 134 extern void clear_local_APIC(void); 135 extern void disconnect_bsp_APIC(int virt_wire_setup); 136 extern void disable_local_APIC(void); 137 extern void lapic_shutdown(void); 138 extern void sync_Arb_IDs(void); 139 extern void apic_intr_mode_init(void); 140 extern void setup_local_APIC(void); 141 extern void init_apic_mappings(void); 142 void register_lapic_address(unsigned long address); 143 extern void setup_boot_APIC_clock(void); 144 extern void setup_secondary_APIC_clock(void); 145 extern void lapic_update_tsc_freq(void); 146 147 #ifdef CONFIG_X86_64 148 static inline int apic_force_enable(unsigned long addr) 149 { 150 return -1; 151 } 152 #else 153 extern int apic_force_enable(unsigned long addr); 154 #endif 155 156 extern void apic_bsp_setup(bool upmode); 157 extern void apic_ap_setup(void); 158 159 /* 160 * On 32bit this is mach-xxx local 161 */ 162 #ifdef CONFIG_X86_64 163 extern int apic_is_clustered_box(void); 164 #else 165 static inline int apic_is_clustered_box(void) 166 { 167 return 0; 168 } 169 #endif 170 171 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 172 173 #else /* !CONFIG_X86_LOCAL_APIC */ 174 static inline void lapic_shutdown(void) { } 175 #define local_apic_timer_c2_ok 1 176 static inline void init_apic_mappings(void) { } 177 static inline void disable_local_APIC(void) { } 178 # define setup_boot_APIC_clock x86_init_noop 179 # define setup_secondary_APIC_clock x86_init_noop 180 static inline void lapic_update_tsc_freq(void) { } 181 static inline void apic_intr_mode_init(void) { } 182 #endif /* !CONFIG_X86_LOCAL_APIC */ 183 184 #ifdef CONFIG_X86_X2APIC 185 /* 186 * Make previous memory operations globally visible before 187 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 188 * mfence for this. 189 */ 190 static inline void x2apic_wrmsr_fence(void) 191 { 192 asm volatile("mfence" : : : "memory"); 193 } 194 195 static inline void native_apic_msr_write(u32 reg, u32 v) 196 { 197 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 198 reg == APIC_LVR) 199 return; 200 201 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 202 } 203 204 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 205 { 206 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 207 } 208 209 static inline u32 native_apic_msr_read(u32 reg) 210 { 211 u64 msr; 212 213 if (reg == APIC_DFR) 214 return -1; 215 216 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 217 return (u32)msr; 218 } 219 220 static inline void native_x2apic_wait_icr_idle(void) 221 { 222 /* no need to wait for icr idle in x2apic */ 223 return; 224 } 225 226 static inline u32 native_safe_x2apic_wait_icr_idle(void) 227 { 228 /* no need to wait for icr idle in x2apic */ 229 return 0; 230 } 231 232 static inline void native_x2apic_icr_write(u32 low, u32 id) 233 { 234 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 235 } 236 237 static inline u64 native_x2apic_icr_read(void) 238 { 239 unsigned long val; 240 241 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 242 return val; 243 } 244 245 extern int x2apic_mode; 246 extern int x2apic_phys; 247 extern void __init check_x2apic(void); 248 extern void x2apic_setup(void); 249 static inline int x2apic_enabled(void) 250 { 251 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 252 } 253 254 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 255 #else /* !CONFIG_X86_X2APIC */ 256 static inline void check_x2apic(void) { } 257 static inline void x2apic_setup(void) { } 258 static inline int x2apic_enabled(void) { return 0; } 259 260 #define x2apic_mode (0) 261 #define x2apic_supported() (0) 262 #endif /* !CONFIG_X86_X2APIC */ 263 264 struct irq_data; 265 266 /* 267 * Copyright 2004 James Cleverdon, IBM. 268 * Subject to the GNU Public License, v.2 269 * 270 * Generic APIC sub-arch data struct. 271 * 272 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 273 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 274 * James Cleverdon. 275 */ 276 struct apic { 277 char *name; 278 279 int (*probe)(void); 280 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 281 int (*apic_id_valid)(int apicid); 282 int (*apic_id_registered)(void); 283 284 u32 irq_delivery_mode; 285 u32 irq_dest_mode; 286 287 const struct cpumask *(*target_cpus)(void); 288 289 int disable_esr; 290 291 int dest_logical; 292 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 293 294 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 295 const struct cpumask *mask); 296 void (*init_apic_ldr)(void); 297 298 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 299 300 void (*setup_apic_routing)(void); 301 int (*cpu_present_to_apicid)(int mps_cpu); 302 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 303 int (*check_phys_apicid_present)(int phys_apicid); 304 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 305 306 unsigned int (*get_apic_id)(unsigned long x); 307 /* Can't be NULL on 64-bit */ 308 unsigned long (*set_apic_id)(unsigned int id); 309 310 int (*cpu_mask_to_apicid)(const struct cpumask *cpumask, 311 struct irq_data *irqdata, 312 unsigned int *apicid); 313 314 /* ipi */ 315 void (*send_IPI)(int cpu, int vector); 316 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 317 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 318 int vector); 319 void (*send_IPI_allbutself)(int vector); 320 void (*send_IPI_all)(int vector); 321 void (*send_IPI_self)(int vector); 322 323 /* wakeup_secondary_cpu */ 324 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 325 326 void (*inquire_remote_apic)(int apicid); 327 328 /* apic ops */ 329 u32 (*read)(u32 reg); 330 void (*write)(u32 reg, u32 v); 331 /* 332 * ->eoi_write() has the same signature as ->write(). 333 * 334 * Drivers can support both ->eoi_write() and ->write() by passing the same 335 * callback value. Kernel can override ->eoi_write() and fall back 336 * on write for EOI. 337 */ 338 void (*eoi_write)(u32 reg, u32 v); 339 void (*native_eoi_write)(u32 reg, u32 v); 340 u64 (*icr_read)(void); 341 void (*icr_write)(u32 low, u32 high); 342 void (*wait_icr_idle)(void); 343 u32 (*safe_wait_icr_idle)(void); 344 345 #ifdef CONFIG_X86_32 346 /* 347 * Called very early during boot from get_smp_config(). It should 348 * return the logical apicid. x86_[bios]_cpu_to_apicid is 349 * initialized before this function is called. 350 * 351 * If logical apicid can't be determined that early, the function 352 * may return BAD_APICID. Logical apicid will be configured after 353 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 354 * won't be applied properly during early boot in this case. 355 */ 356 int (*x86_32_early_logical_apicid)(int cpu); 357 #endif 358 }; 359 360 /* 361 * Pointer to the local APIC driver in use on this system (there's 362 * always just one such driver in use - the kernel decides via an 363 * early probing process which one it picks - and then sticks to it): 364 */ 365 extern struct apic *apic; 366 367 /* 368 * APIC drivers are probed based on how they are listed in the .apicdrivers 369 * section. So the order is important and enforced by the ordering 370 * of different apic driver files in the Makefile. 371 * 372 * For the files having two apic drivers, we use apic_drivers() 373 * to enforce the order with in them. 374 */ 375 #define apic_driver(sym) \ 376 static const struct apic *__apicdrivers_##sym __used \ 377 __aligned(sizeof(struct apic *)) \ 378 __section(.apicdrivers) = { &sym } 379 380 #define apic_drivers(sym1, sym2) \ 381 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 382 __aligned(sizeof(struct apic *)) \ 383 __section(.apicdrivers) = { &sym1, &sym2 } 384 385 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 386 387 /* 388 * APIC functionality to boot other CPUs - only used on SMP: 389 */ 390 #ifdef CONFIG_SMP 391 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 392 #endif 393 394 #ifdef CONFIG_X86_LOCAL_APIC 395 396 static inline u32 apic_read(u32 reg) 397 { 398 return apic->read(reg); 399 } 400 401 static inline void apic_write(u32 reg, u32 val) 402 { 403 apic->write(reg, val); 404 } 405 406 static inline void apic_eoi(void) 407 { 408 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 409 } 410 411 static inline u64 apic_icr_read(void) 412 { 413 return apic->icr_read(); 414 } 415 416 static inline void apic_icr_write(u32 low, u32 high) 417 { 418 apic->icr_write(low, high); 419 } 420 421 static inline void apic_wait_icr_idle(void) 422 { 423 apic->wait_icr_idle(); 424 } 425 426 static inline u32 safe_apic_wait_icr_idle(void) 427 { 428 return apic->safe_wait_icr_idle(); 429 } 430 431 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 432 433 #else /* CONFIG_X86_LOCAL_APIC */ 434 435 static inline u32 apic_read(u32 reg) { return 0; } 436 static inline void apic_write(u32 reg, u32 val) { } 437 static inline void apic_eoi(void) { } 438 static inline u64 apic_icr_read(void) { return 0; } 439 static inline void apic_icr_write(u32 low, u32 high) { } 440 static inline void apic_wait_icr_idle(void) { } 441 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 442 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 443 444 #endif /* CONFIG_X86_LOCAL_APIC */ 445 446 static inline void ack_APIC_irq(void) 447 { 448 /* 449 * ack_APIC_irq() actually gets compiled as a single instruction 450 * ... yummie. 451 */ 452 apic_eoi(); 453 } 454 455 static inline unsigned default_get_apic_id(unsigned long x) 456 { 457 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 458 459 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 460 return (x >> 24) & 0xFF; 461 else 462 return (x >> 24) & 0x0F; 463 } 464 465 /* 466 * Warm reset vector position: 467 */ 468 #define TRAMPOLINE_PHYS_LOW 0x467 469 #define TRAMPOLINE_PHYS_HIGH 0x469 470 471 #ifdef CONFIG_X86_64 472 extern void apic_send_IPI_self(int vector); 473 474 DECLARE_PER_CPU(int, x2apic_extra_bits); 475 476 extern int default_cpu_present_to_apicid(int mps_cpu); 477 extern int default_check_phys_apicid_present(int phys_apicid); 478 #endif 479 480 extern void generic_bigsmp_probe(void); 481 482 483 #ifdef CONFIG_X86_LOCAL_APIC 484 485 #include <asm/smp.h> 486 487 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 488 489 static inline const struct cpumask *default_target_cpus(void) 490 { 491 #ifdef CONFIG_SMP 492 return cpu_online_mask; 493 #else 494 return cpumask_of(0); 495 #endif 496 } 497 498 static inline const struct cpumask *online_target_cpus(void) 499 { 500 return cpu_online_mask; 501 } 502 503 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 504 505 506 static inline unsigned int read_apic_id(void) 507 { 508 unsigned int reg; 509 510 reg = apic_read(APIC_ID); 511 512 return apic->get_apic_id(reg); 513 } 514 515 static inline int default_apic_id_valid(int apicid) 516 { 517 return (apicid < 255); 518 } 519 520 extern int default_acpi_madt_oem_check(char *, char *); 521 522 extern void default_setup_apic_routing(void); 523 524 extern struct apic apic_noop; 525 526 #ifdef CONFIG_X86_32 527 528 static inline int noop_x86_32_early_logical_apicid(int cpu) 529 { 530 return BAD_APICID; 531 } 532 533 /* 534 * Set up the logical destination ID. 535 * 536 * Intel recommends to set DFR, LDR and TPR before enabling 537 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 538 * document number 292116). So here it goes... 539 */ 540 extern void default_init_apic_ldr(void); 541 542 static inline int default_apic_id_registered(void) 543 { 544 return physid_isset(read_apic_id(), phys_cpu_present_map); 545 } 546 547 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 548 { 549 return cpuid_apic >> index_msb; 550 } 551 552 #endif 553 554 extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask, 555 struct irq_data *irqdata, 556 unsigned int *apicid); 557 extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask, 558 struct irq_data *irqdata, 559 unsigned int *apicid); 560 561 static inline void 562 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 563 const struct cpumask *mask) 564 { 565 /* Careful. Some cpus do not strictly honor the set of cpus 566 * specified in the interrupt destination when using lowest 567 * priority interrupt delivery mode. 568 * 569 * In particular there was a hyperthreading cpu observed to 570 * deliver interrupts to the wrong hyperthread when only one 571 * hyperthread was specified in the interrupt desitination. 572 */ 573 cpumask_clear(retmask); 574 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 575 } 576 577 static inline void 578 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 579 const struct cpumask *mask) 580 { 581 cpumask_copy(retmask, cpumask_of(cpu)); 582 } 583 584 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 585 { 586 return physid_isset(apicid, *map); 587 } 588 589 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 590 { 591 *retmap = *phys_map; 592 } 593 594 static inline int __default_cpu_present_to_apicid(int mps_cpu) 595 { 596 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 597 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 598 else 599 return BAD_APICID; 600 } 601 602 static inline int 603 __default_check_phys_apicid_present(int phys_apicid) 604 { 605 return physid_isset(phys_apicid, phys_cpu_present_map); 606 } 607 608 #ifdef CONFIG_X86_32 609 static inline int default_cpu_present_to_apicid(int mps_cpu) 610 { 611 return __default_cpu_present_to_apicid(mps_cpu); 612 } 613 614 static inline int 615 default_check_phys_apicid_present(int phys_apicid) 616 { 617 return __default_check_phys_apicid_present(phys_apicid); 618 } 619 #else 620 extern int default_cpu_present_to_apicid(int mps_cpu); 621 extern int default_check_phys_apicid_present(int phys_apicid); 622 #endif 623 624 #endif /* CONFIG_X86_LOCAL_APIC */ 625 extern void irq_enter(void); 626 extern void irq_exit(void); 627 628 static inline void entering_irq(void) 629 { 630 irq_enter(); 631 } 632 633 static inline void entering_ack_irq(void) 634 { 635 entering_irq(); 636 ack_APIC_irq(); 637 } 638 639 static inline void ipi_entering_ack_irq(void) 640 { 641 irq_enter(); 642 ack_APIC_irq(); 643 } 644 645 static inline void exiting_irq(void) 646 { 647 irq_exit(); 648 } 649 650 static inline void exiting_ack_irq(void) 651 { 652 ack_APIC_irq(); 653 irq_exit(); 654 } 655 656 extern void ioapic_zap_locks(void); 657 658 #endif /* _ASM_X86_APIC_H */ 659