1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/apicdef.h> 10 #include <linux/atomic.h> 11 #include <asm/fixmap.h> 12 #include <asm/mpspec.h> 13 #include <asm/msr.h> 14 #include <asm/hardirq.h> 15 16 #define ARCH_APICTIMER_STOPS_ON_C3 1 17 18 /* 19 * Debugging macros 20 */ 21 #define APIC_QUIET 0 22 #define APIC_VERBOSE 1 23 #define APIC_DEBUG 2 24 25 /* Macros for apic_extnmi which controls external NMI masking */ 26 #define APIC_EXTNMI_BSP 0 /* Default */ 27 #define APIC_EXTNMI_ALL 1 28 #define APIC_EXTNMI_NONE 2 29 30 /* 31 * Define the default level of output to be very little 32 * This can be turned up by using apic=verbose for more 33 * information and apic=debug for _lots_ of information. 34 * apic_verbosity is defined in apic.c 35 */ 36 #define apic_printk(v, s, a...) do { \ 37 if ((v) <= apic_verbosity) \ 38 printk(s, ##a); \ 39 } while (0) 40 41 42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 43 extern void generic_apic_probe(void); 44 #else 45 static inline void generic_apic_probe(void) 46 { 47 } 48 #endif 49 50 #ifdef CONFIG_X86_LOCAL_APIC 51 52 extern int apic_verbosity; 53 extern int local_apic_timer_c2_ok; 54 55 extern bool apic_is_disabled; 56 extern unsigned int lapic_timer_period; 57 58 extern int cpuid_to_apicid[]; 59 60 extern enum apic_intr_mode_id apic_intr_mode; 61 enum apic_intr_mode_id { 62 APIC_PIC, 63 APIC_VIRTUAL_WIRE, 64 APIC_VIRTUAL_WIRE_NO_CONFIG, 65 APIC_SYMMETRIC_IO, 66 APIC_SYMMETRIC_IO_NO_ROUTING 67 }; 68 69 #ifdef CONFIG_SMP 70 extern void __inquire_remote_apic(int apicid); 71 #else /* CONFIG_SMP */ 72 static inline void __inquire_remote_apic(int apicid) 73 { 74 } 75 #endif /* CONFIG_SMP */ 76 77 static inline void default_inquire_remote_apic(int apicid) 78 { 79 if (apic_verbosity >= APIC_DEBUG) 80 __inquire_remote_apic(apicid); 81 } 82 83 /* 84 * With 82489DX we can't rely on apic feature bit 85 * retrieved via cpuid but still have to deal with 86 * such an apic chip so we assume that SMP configuration 87 * is found from MP table (64bit case uses ACPI mostly 88 * which set smp presence flag as well so we are safe 89 * to use this helper too). 90 */ 91 static inline bool apic_from_smp_config(void) 92 { 93 return smp_found_config && !apic_is_disabled; 94 } 95 96 /* 97 * Basic functions accessing APICs. 98 */ 99 #ifdef CONFIG_PARAVIRT 100 #include <asm/paravirt.h> 101 #endif 102 103 static inline void native_apic_mem_write(u32 reg, u32 v) 104 { 105 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 106 107 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 108 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 109 ASM_OUTPUT2("0" (v), "m" (*addr))); 110 } 111 112 static inline u32 native_apic_mem_read(u32 reg) 113 { 114 return *((volatile u32 *)(APIC_BASE + reg)); 115 } 116 117 extern void native_apic_wait_icr_idle(void); 118 extern u32 native_safe_apic_wait_icr_idle(void); 119 extern void native_apic_icr_write(u32 low, u32 id); 120 extern u64 native_apic_icr_read(void); 121 122 static inline bool apic_is_x2apic_enabled(void) 123 { 124 u64 msr; 125 126 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 127 return false; 128 return msr & X2APIC_ENABLE; 129 } 130 131 extern void enable_IR_x2apic(void); 132 133 extern int get_physical_broadcast(void); 134 135 extern int lapic_get_maxlvt(void); 136 extern void clear_local_APIC(void); 137 extern void disconnect_bsp_APIC(int virt_wire_setup); 138 extern void disable_local_APIC(void); 139 extern void apic_soft_disable(void); 140 extern void lapic_shutdown(void); 141 extern void sync_Arb_IDs(void); 142 extern void init_bsp_APIC(void); 143 extern void apic_intr_mode_select(void); 144 extern void apic_intr_mode_init(void); 145 extern void init_apic_mappings(void); 146 void register_lapic_address(unsigned long address); 147 extern void setup_boot_APIC_clock(void); 148 extern void setup_secondary_APIC_clock(void); 149 extern void lapic_update_tsc_freq(void); 150 151 #ifdef CONFIG_X86_64 152 static inline int apic_force_enable(unsigned long addr) 153 { 154 return -1; 155 } 156 #else 157 extern int apic_force_enable(unsigned long addr); 158 #endif 159 160 extern void apic_ap_setup(void); 161 162 /* 163 * On 32bit this is mach-xxx local 164 */ 165 #ifdef CONFIG_X86_64 166 extern int apic_is_clustered_box(void); 167 #else 168 static inline int apic_is_clustered_box(void) 169 { 170 return 0; 171 } 172 #endif 173 174 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 175 extern void lapic_assign_system_vectors(void); 176 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 177 extern void lapic_update_legacy_vectors(void); 178 extern void lapic_online(void); 179 extern void lapic_offline(void); 180 extern bool apic_needs_pit(void); 181 182 extern void apic_send_IPI_allbutself(unsigned int vector); 183 184 #else /* !CONFIG_X86_LOCAL_APIC */ 185 static inline void lapic_shutdown(void) { } 186 #define local_apic_timer_c2_ok 1 187 static inline void init_apic_mappings(void) { } 188 static inline void disable_local_APIC(void) { } 189 # define setup_boot_APIC_clock x86_init_noop 190 # define setup_secondary_APIC_clock x86_init_noop 191 static inline void lapic_update_tsc_freq(void) { } 192 static inline void init_bsp_APIC(void) { } 193 static inline void apic_intr_mode_select(void) { } 194 static inline void apic_intr_mode_init(void) { } 195 static inline void lapic_assign_system_vectors(void) { } 196 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 197 static inline bool apic_needs_pit(void) { return true; } 198 #endif /* !CONFIG_X86_LOCAL_APIC */ 199 200 #ifdef CONFIG_X86_X2APIC 201 static inline void native_apic_msr_write(u32 reg, u32 v) 202 { 203 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 204 reg == APIC_LVR) 205 return; 206 207 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 208 } 209 210 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 211 { 212 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 213 } 214 215 static inline u32 native_apic_msr_read(u32 reg) 216 { 217 u64 msr; 218 219 if (reg == APIC_DFR) 220 return -1; 221 222 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 223 return (u32)msr; 224 } 225 226 static inline void native_x2apic_wait_icr_idle(void) 227 { 228 /* no need to wait for icr idle in x2apic */ 229 return; 230 } 231 232 static inline u32 native_safe_x2apic_wait_icr_idle(void) 233 { 234 /* no need to wait for icr idle in x2apic */ 235 return 0; 236 } 237 238 static inline void native_x2apic_icr_write(u32 low, u32 id) 239 { 240 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 241 } 242 243 static inline u64 native_x2apic_icr_read(void) 244 { 245 unsigned long val; 246 247 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 248 return val; 249 } 250 251 extern int x2apic_mode; 252 extern int x2apic_phys; 253 extern void __init x2apic_set_max_apicid(u32 apicid); 254 extern void x2apic_setup(void); 255 static inline int x2apic_enabled(void) 256 { 257 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 258 } 259 260 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 261 #else /* !CONFIG_X86_X2APIC */ 262 static inline void x2apic_setup(void) { } 263 static inline int x2apic_enabled(void) { return 0; } 264 265 #define x2apic_mode (0) 266 #define x2apic_supported() (0) 267 #endif /* !CONFIG_X86_X2APIC */ 268 extern void __init check_x2apic(void); 269 270 struct irq_data; 271 272 /* 273 * Copyright 2004 James Cleverdon, IBM. 274 * 275 * Generic APIC sub-arch data struct. 276 * 277 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 278 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 279 * James Cleverdon. 280 */ 281 struct apic { 282 /* Hotpath functions first */ 283 void (*eoi_write)(u32 reg, u32 v); 284 void (*native_eoi_write)(u32 reg, u32 v); 285 void (*write)(u32 reg, u32 v); 286 u32 (*read)(u32 reg); 287 288 /* IPI related functions */ 289 void (*wait_icr_idle)(void); 290 u32 (*safe_wait_icr_idle)(void); 291 292 void (*send_IPI)(int cpu, int vector); 293 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 294 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 295 void (*send_IPI_allbutself)(int vector); 296 void (*send_IPI_all)(int vector); 297 void (*send_IPI_self)(int vector); 298 299 u32 disable_esr; 300 301 enum apic_delivery_modes delivery_mode; 302 bool dest_mode_logical; 303 304 u32 (*calc_dest_apicid)(unsigned int cpu); 305 306 /* ICR related functions */ 307 u64 (*icr_read)(void); 308 void (*icr_write)(u32 low, u32 high); 309 310 /* Probe, setup and smpboot functions */ 311 int (*probe)(void); 312 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 313 int (*apic_id_valid)(u32 apicid); 314 int (*apic_id_registered)(void); 315 316 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 317 void (*init_apic_ldr)(void); 318 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 319 void (*setup_apic_routing)(void); 320 int (*cpu_present_to_apicid)(int mps_cpu); 321 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 322 int (*check_phys_apicid_present)(int phys_apicid); 323 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 324 325 u32 (*get_apic_id)(unsigned long x); 326 u32 (*set_apic_id)(unsigned int id); 327 328 /* wakeup_secondary_cpu */ 329 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 330 /* wakeup secondary CPU using 64-bit wakeup point */ 331 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); 332 333 void (*inquire_remote_apic)(int apicid); 334 335 #ifdef CONFIG_X86_32 336 /* 337 * Called very early during boot from get_smp_config(). It should 338 * return the logical apicid. x86_[bios]_cpu_to_apicid is 339 * initialized before this function is called. 340 * 341 * If logical apicid can't be determined that early, the function 342 * may return BAD_APICID. Logical apicid will be configured after 343 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 344 * won't be applied properly during early boot in this case. 345 */ 346 int (*x86_32_early_logical_apicid)(int cpu); 347 #endif 348 char *name; 349 }; 350 351 /* 352 * Pointer to the local APIC driver in use on this system (there's 353 * always just one such driver in use - the kernel decides via an 354 * early probing process which one it picks - and then sticks to it): 355 */ 356 extern struct apic *apic; 357 358 /* 359 * APIC drivers are probed based on how they are listed in the .apicdrivers 360 * section. So the order is important and enforced by the ordering 361 * of different apic driver files in the Makefile. 362 * 363 * For the files having two apic drivers, we use apic_drivers() 364 * to enforce the order with in them. 365 */ 366 #define apic_driver(sym) \ 367 static const struct apic *__apicdrivers_##sym __used \ 368 __aligned(sizeof(struct apic *)) \ 369 __section(".apicdrivers") = { &sym } 370 371 #define apic_drivers(sym1, sym2) \ 372 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 373 __aligned(sizeof(struct apic *)) \ 374 __section(".apicdrivers") = { &sym1, &sym2 } 375 376 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 377 378 /* 379 * APIC functionality to boot other CPUs - only used on SMP: 380 */ 381 #ifdef CONFIG_SMP 382 extern int lapic_can_unplug_cpu(void); 383 #endif 384 385 #ifdef CONFIG_X86_LOCAL_APIC 386 387 static inline u32 apic_read(u32 reg) 388 { 389 return apic->read(reg); 390 } 391 392 static inline void apic_write(u32 reg, u32 val) 393 { 394 apic->write(reg, val); 395 } 396 397 static inline void apic_eoi(void) 398 { 399 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 400 } 401 402 static inline u64 apic_icr_read(void) 403 { 404 return apic->icr_read(); 405 } 406 407 static inline void apic_icr_write(u32 low, u32 high) 408 { 409 apic->icr_write(low, high); 410 } 411 412 static inline void apic_wait_icr_idle(void) 413 { 414 apic->wait_icr_idle(); 415 } 416 417 static inline u32 safe_apic_wait_icr_idle(void) 418 { 419 return apic->safe_wait_icr_idle(); 420 } 421 422 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 423 424 #else /* CONFIG_X86_LOCAL_APIC */ 425 426 static inline u32 apic_read(u32 reg) { return 0; } 427 static inline void apic_write(u32 reg, u32 val) { } 428 static inline void apic_eoi(void) { } 429 static inline u64 apic_icr_read(void) { return 0; } 430 static inline void apic_icr_write(u32 low, u32 high) { } 431 static inline void apic_wait_icr_idle(void) { } 432 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 433 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 434 435 #endif /* CONFIG_X86_LOCAL_APIC */ 436 437 extern void apic_ack_irq(struct irq_data *data); 438 439 static inline void ack_APIC_irq(void) 440 { 441 /* 442 * ack_APIC_irq() actually gets compiled as a single instruction 443 * ... yummie. 444 */ 445 apic_eoi(); 446 } 447 448 449 static inline bool lapic_vector_set_in_irr(unsigned int vector) 450 { 451 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 452 453 return !!(irr & (1U << (vector % 32))); 454 } 455 456 static inline unsigned default_get_apic_id(unsigned long x) 457 { 458 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 459 460 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 461 return (x >> 24) & 0xFF; 462 else 463 return (x >> 24) & 0x0F; 464 } 465 466 /* 467 * Warm reset vector position: 468 */ 469 #define TRAMPOLINE_PHYS_LOW 0x467 470 #define TRAMPOLINE_PHYS_HIGH 0x469 471 472 extern void generic_bigsmp_probe(void); 473 474 #ifdef CONFIG_X86_LOCAL_APIC 475 476 #include <asm/smp.h> 477 478 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 479 480 extern struct apic apic_noop; 481 482 static inline unsigned int read_apic_id(void) 483 { 484 unsigned int reg = apic_read(APIC_ID); 485 486 return apic->get_apic_id(reg); 487 } 488 489 #ifdef CONFIG_X86_64 490 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 491 extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); 492 #endif 493 494 extern int default_apic_id_valid(u32 apicid); 495 extern int default_acpi_madt_oem_check(char *, char *); 496 extern void default_setup_apic_routing(void); 497 498 extern u32 apic_default_calc_apicid(unsigned int cpu); 499 extern u32 apic_flat_calc_apicid(unsigned int cpu); 500 501 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 502 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 503 extern int default_cpu_present_to_apicid(int mps_cpu); 504 extern int default_check_phys_apicid_present(int phys_apicid); 505 506 #else /* CONFIG_X86_LOCAL_APIC */ 507 508 static inline unsigned int read_apic_id(void) { return 0; } 509 510 #endif /* !CONFIG_X86_LOCAL_APIC */ 511 512 #ifdef CONFIG_SMP 513 void apic_smt_update(void); 514 #else 515 static inline void apic_smt_update(void) { } 516 #endif 517 518 struct msi_msg; 519 struct irq_cfg; 520 521 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 522 bool dmar); 523 524 extern void ioapic_zap_locks(void); 525 526 #endif /* _ASM_X86_APIC_H */ 527