1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 6 #include <asm/alternative.h> 7 #include <asm/cpufeature.h> 8 #include <asm/apicdef.h> 9 #include <linux/atomic.h> 10 #include <asm/fixmap.h> 11 #include <asm/mpspec.h> 12 #include <asm/msr.h> 13 14 #define ARCH_APICTIMER_STOPS_ON_C3 1 15 16 /* 17 * Debugging macros 18 */ 19 #define APIC_QUIET 0 20 #define APIC_VERBOSE 1 21 #define APIC_DEBUG 2 22 23 /* Macros for apic_extnmi which controls external NMI masking */ 24 #define APIC_EXTNMI_BSP 0 /* Default */ 25 #define APIC_EXTNMI_ALL 1 26 #define APIC_EXTNMI_NONE 2 27 28 /* 29 * Define the default level of output to be very little 30 * This can be turned up by using apic=verbose for more 31 * information and apic=debug for _lots_ of information. 32 * apic_verbosity is defined in apic.c 33 */ 34 #define apic_printk(v, s, a...) do { \ 35 if ((v) <= apic_verbosity) \ 36 printk(s, ##a); \ 37 } while (0) 38 39 40 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 41 extern void generic_apic_probe(void); 42 #else 43 static inline void generic_apic_probe(void) 44 { 45 } 46 #endif 47 48 #ifdef CONFIG_X86_LOCAL_APIC 49 50 extern unsigned int apic_verbosity; 51 extern int local_apic_timer_c2_ok; 52 53 extern int disable_apic; 54 extern unsigned int lapic_timer_frequency; 55 56 extern enum apic_intr_mode_id apic_intr_mode; 57 enum apic_intr_mode_id { 58 APIC_PIC, 59 APIC_VIRTUAL_WIRE, 60 APIC_VIRTUAL_WIRE_NO_CONFIG, 61 APIC_SYMMETRIC_IO, 62 APIC_SYMMETRIC_IO_NO_ROUTING 63 }; 64 65 #ifdef CONFIG_SMP 66 extern void __inquire_remote_apic(int apicid); 67 #else /* CONFIG_SMP */ 68 static inline void __inquire_remote_apic(int apicid) 69 { 70 } 71 #endif /* CONFIG_SMP */ 72 73 static inline void default_inquire_remote_apic(int apicid) 74 { 75 if (apic_verbosity >= APIC_DEBUG) 76 __inquire_remote_apic(apicid); 77 } 78 79 /* 80 * With 82489DX we can't rely on apic feature bit 81 * retrieved via cpuid but still have to deal with 82 * such an apic chip so we assume that SMP configuration 83 * is found from MP table (64bit case uses ACPI mostly 84 * which set smp presence flag as well so we are safe 85 * to use this helper too). 86 */ 87 static inline bool apic_from_smp_config(void) 88 { 89 return smp_found_config && !disable_apic; 90 } 91 92 /* 93 * Basic functions accessing APICs. 94 */ 95 #ifdef CONFIG_PARAVIRT 96 #include <asm/paravirt.h> 97 #endif 98 99 extern int setup_profiling_timer(unsigned int); 100 101 static inline void native_apic_mem_write(u32 reg, u32 v) 102 { 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108 } 109 110 static inline u32 native_apic_mem_read(u32 reg) 111 { 112 return *((volatile u32 *)(APIC_BASE + reg)); 113 } 114 115 extern void native_apic_wait_icr_idle(void); 116 extern u32 native_safe_apic_wait_icr_idle(void); 117 extern void native_apic_icr_write(u32 low, u32 id); 118 extern u64 native_apic_icr_read(void); 119 120 static inline bool apic_is_x2apic_enabled(void) 121 { 122 u64 msr; 123 124 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 125 return false; 126 return msr & X2APIC_ENABLE; 127 } 128 129 extern void enable_IR_x2apic(void); 130 131 extern int get_physical_broadcast(void); 132 133 extern int lapic_get_maxlvt(void); 134 extern void clear_local_APIC(void); 135 extern void disconnect_bsp_APIC(int virt_wire_setup); 136 extern void disable_local_APIC(void); 137 extern void lapic_shutdown(void); 138 extern void sync_Arb_IDs(void); 139 extern void apic_intr_mode_init(void); 140 extern void setup_local_APIC(void); 141 extern void init_apic_mappings(void); 142 void register_lapic_address(unsigned long address); 143 extern void setup_boot_APIC_clock(void); 144 extern void setup_secondary_APIC_clock(void); 145 extern void lapic_update_tsc_freq(void); 146 147 #ifdef CONFIG_X86_64 148 static inline int apic_force_enable(unsigned long addr) 149 { 150 return -1; 151 } 152 #else 153 extern int apic_force_enable(unsigned long addr); 154 #endif 155 156 extern void apic_bsp_setup(bool upmode); 157 extern void apic_ap_setup(void); 158 159 /* 160 * On 32bit this is mach-xxx local 161 */ 162 #ifdef CONFIG_X86_64 163 extern int apic_is_clustered_box(void); 164 #else 165 static inline int apic_is_clustered_box(void) 166 { 167 return 0; 168 } 169 #endif 170 171 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 172 173 #else /* !CONFIG_X86_LOCAL_APIC */ 174 static inline void lapic_shutdown(void) { } 175 #define local_apic_timer_c2_ok 1 176 static inline void init_apic_mappings(void) { } 177 static inline void disable_local_APIC(void) { } 178 # define setup_boot_APIC_clock x86_init_noop 179 # define setup_secondary_APIC_clock x86_init_noop 180 static inline void lapic_update_tsc_freq(void) { } 181 static inline void apic_intr_mode_init(void) { } 182 #endif /* !CONFIG_X86_LOCAL_APIC */ 183 184 #ifdef CONFIG_X86_X2APIC 185 /* 186 * Make previous memory operations globally visible before 187 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 188 * mfence for this. 189 */ 190 static inline void x2apic_wrmsr_fence(void) 191 { 192 asm volatile("mfence" : : : "memory"); 193 } 194 195 static inline void native_apic_msr_write(u32 reg, u32 v) 196 { 197 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 198 reg == APIC_LVR) 199 return; 200 201 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 202 } 203 204 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 205 { 206 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 207 } 208 209 static inline u32 native_apic_msr_read(u32 reg) 210 { 211 u64 msr; 212 213 if (reg == APIC_DFR) 214 return -1; 215 216 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 217 return (u32)msr; 218 } 219 220 static inline void native_x2apic_wait_icr_idle(void) 221 { 222 /* no need to wait for icr idle in x2apic */ 223 return; 224 } 225 226 static inline u32 native_safe_x2apic_wait_icr_idle(void) 227 { 228 /* no need to wait for icr idle in x2apic */ 229 return 0; 230 } 231 232 static inline void native_x2apic_icr_write(u32 low, u32 id) 233 { 234 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 235 } 236 237 static inline u64 native_x2apic_icr_read(void) 238 { 239 unsigned long val; 240 241 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 242 return val; 243 } 244 245 extern int x2apic_mode; 246 extern int x2apic_phys; 247 extern void __init check_x2apic(void); 248 extern void x2apic_setup(void); 249 static inline int x2apic_enabled(void) 250 { 251 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 252 } 253 254 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 255 #else /* !CONFIG_X86_X2APIC */ 256 static inline void check_x2apic(void) { } 257 static inline void x2apic_setup(void) { } 258 static inline int x2apic_enabled(void) { return 0; } 259 260 #define x2apic_mode (0) 261 #define x2apic_supported() (0) 262 #endif /* !CONFIG_X86_X2APIC */ 263 264 struct irq_data; 265 266 /* 267 * Copyright 2004 James Cleverdon, IBM. 268 * Subject to the GNU Public License, v.2 269 * 270 * Generic APIC sub-arch data struct. 271 * 272 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 273 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 274 * James Cleverdon. 275 */ 276 struct apic { 277 /* Hotpath functions first */ 278 void (*eoi_write)(u32 reg, u32 v); 279 void (*native_eoi_write)(u32 reg, u32 v); 280 void (*write)(u32 reg, u32 v); 281 u32 (*read)(u32 reg); 282 283 /* IPI related functions */ 284 void (*wait_icr_idle)(void); 285 u32 (*safe_wait_icr_idle)(void); 286 287 void (*send_IPI)(int cpu, int vector); 288 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 289 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 290 void (*send_IPI_allbutself)(int vector); 291 void (*send_IPI_all)(int vector); 292 void (*send_IPI_self)(int vector); 293 294 /* dest_logical is used by the IPI functions */ 295 u32 dest_logical; 296 u32 disable_esr; 297 u32 irq_delivery_mode; 298 u32 irq_dest_mode; 299 300 /* Functions and data related to vector allocation */ 301 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 302 const struct cpumask *mask); 303 int (*cpu_mask_to_apicid)(const struct cpumask *cpumask, 304 struct irq_data *irqdata, 305 unsigned int *apicid); 306 u32 (*calc_dest_apicid)(unsigned int cpu); 307 308 /* ICR related functions */ 309 u64 (*icr_read)(void); 310 void (*icr_write)(u32 low, u32 high); 311 312 /* Probe, setup and smpboot functions */ 313 int (*probe)(void); 314 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 315 int (*apic_id_valid)(int apicid); 316 int (*apic_id_registered)(void); 317 318 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 319 void (*init_apic_ldr)(void); 320 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 321 void (*setup_apic_routing)(void); 322 int (*cpu_present_to_apicid)(int mps_cpu); 323 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 324 int (*check_phys_apicid_present)(int phys_apicid); 325 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 326 327 u32 (*get_apic_id)(unsigned long x); 328 u32 (*set_apic_id)(unsigned int id); 329 330 /* wakeup_secondary_cpu */ 331 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 332 333 void (*inquire_remote_apic)(int apicid); 334 335 #ifdef CONFIG_X86_32 336 /* 337 * Called very early during boot from get_smp_config(). It should 338 * return the logical apicid. x86_[bios]_cpu_to_apicid is 339 * initialized before this function is called. 340 * 341 * If logical apicid can't be determined that early, the function 342 * may return BAD_APICID. Logical apicid will be configured after 343 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 344 * won't be applied properly during early boot in this case. 345 */ 346 int (*x86_32_early_logical_apicid)(int cpu); 347 #endif 348 char *name; 349 }; 350 351 /* 352 * Pointer to the local APIC driver in use on this system (there's 353 * always just one such driver in use - the kernel decides via an 354 * early probing process which one it picks - and then sticks to it): 355 */ 356 extern struct apic *apic; 357 358 /* 359 * APIC drivers are probed based on how they are listed in the .apicdrivers 360 * section. So the order is important and enforced by the ordering 361 * of different apic driver files in the Makefile. 362 * 363 * For the files having two apic drivers, we use apic_drivers() 364 * to enforce the order with in them. 365 */ 366 #define apic_driver(sym) \ 367 static const struct apic *__apicdrivers_##sym __used \ 368 __aligned(sizeof(struct apic *)) \ 369 __section(.apicdrivers) = { &sym } 370 371 #define apic_drivers(sym1, sym2) \ 372 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 373 __aligned(sizeof(struct apic *)) \ 374 __section(.apicdrivers) = { &sym1, &sym2 } 375 376 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 377 378 /* 379 * APIC functionality to boot other CPUs - only used on SMP: 380 */ 381 #ifdef CONFIG_SMP 382 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 383 #endif 384 385 #ifdef CONFIG_X86_LOCAL_APIC 386 387 static inline u32 apic_read(u32 reg) 388 { 389 return apic->read(reg); 390 } 391 392 static inline void apic_write(u32 reg, u32 val) 393 { 394 apic->write(reg, val); 395 } 396 397 static inline void apic_eoi(void) 398 { 399 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 400 } 401 402 static inline u64 apic_icr_read(void) 403 { 404 return apic->icr_read(); 405 } 406 407 static inline void apic_icr_write(u32 low, u32 high) 408 { 409 apic->icr_write(low, high); 410 } 411 412 static inline void apic_wait_icr_idle(void) 413 { 414 apic->wait_icr_idle(); 415 } 416 417 static inline u32 safe_apic_wait_icr_idle(void) 418 { 419 return apic->safe_wait_icr_idle(); 420 } 421 422 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 423 424 #else /* CONFIG_X86_LOCAL_APIC */ 425 426 static inline u32 apic_read(u32 reg) { return 0; } 427 static inline void apic_write(u32 reg, u32 val) { } 428 static inline void apic_eoi(void) { } 429 static inline u64 apic_icr_read(void) { return 0; } 430 static inline void apic_icr_write(u32 low, u32 high) { } 431 static inline void apic_wait_icr_idle(void) { } 432 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 433 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 434 435 #endif /* CONFIG_X86_LOCAL_APIC */ 436 437 static inline void ack_APIC_irq(void) 438 { 439 /* 440 * ack_APIC_irq() actually gets compiled as a single instruction 441 * ... yummie. 442 */ 443 apic_eoi(); 444 } 445 446 static inline unsigned default_get_apic_id(unsigned long x) 447 { 448 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 449 450 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 451 return (x >> 24) & 0xFF; 452 else 453 return (x >> 24) & 0x0F; 454 } 455 456 /* 457 * Warm reset vector position: 458 */ 459 #define TRAMPOLINE_PHYS_LOW 0x467 460 #define TRAMPOLINE_PHYS_HIGH 0x469 461 462 #ifdef CONFIG_X86_64 463 extern void apic_send_IPI_self(int vector); 464 465 DECLARE_PER_CPU(int, x2apic_extra_bits); 466 #endif 467 468 extern void generic_bigsmp_probe(void); 469 470 #ifdef CONFIG_X86_LOCAL_APIC 471 472 #include <asm/smp.h> 473 474 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 475 476 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 477 478 extern struct apic apic_noop; 479 480 static inline unsigned int read_apic_id(void) 481 { 482 unsigned int reg = apic_read(APIC_ID); 483 484 return apic->get_apic_id(reg); 485 } 486 487 extern int default_apic_id_valid(int apicid); 488 extern int default_acpi_madt_oem_check(char *, char *); 489 extern void default_setup_apic_routing(void); 490 491 extern u32 apic_default_calc_apicid(unsigned int cpu); 492 extern u32 apic_flat_calc_apicid(unsigned int cpu); 493 494 extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask, 495 struct irq_data *irqdata, 496 unsigned int *apicid); 497 extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask, 498 struct irq_data *irqdata, 499 unsigned int *apicid); 500 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 501 extern void flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 502 const struct cpumask *mask); 503 extern void default_vector_allocation_domain(int cpu, struct cpumask *retmask, 504 const struct cpumask *mask); 505 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 506 extern int default_cpu_present_to_apicid(int mps_cpu); 507 extern int default_check_phys_apicid_present(int phys_apicid); 508 509 #endif /* CONFIG_X86_LOCAL_APIC */ 510 511 extern void irq_enter(void); 512 extern void irq_exit(void); 513 514 static inline void entering_irq(void) 515 { 516 irq_enter(); 517 } 518 519 static inline void entering_ack_irq(void) 520 { 521 entering_irq(); 522 ack_APIC_irq(); 523 } 524 525 static inline void ipi_entering_ack_irq(void) 526 { 527 irq_enter(); 528 ack_APIC_irq(); 529 } 530 531 static inline void exiting_irq(void) 532 { 533 irq_exit(); 534 } 535 536 static inline void exiting_ack_irq(void) 537 { 538 ack_APIC_irq(); 539 irq_exit(); 540 } 541 542 extern void ioapic_zap_locks(void); 543 544 #endif /* _ASM_X86_APIC_H */ 545