1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/apicdef.h> 10 #include <linux/atomic.h> 11 #include <asm/fixmap.h> 12 #include <asm/mpspec.h> 13 #include <asm/msr.h> 14 #include <asm/hardirq.h> 15 16 #define ARCH_APICTIMER_STOPS_ON_C3 1 17 18 /* 19 * Debugging macros 20 */ 21 #define APIC_QUIET 0 22 #define APIC_VERBOSE 1 23 #define APIC_DEBUG 2 24 25 /* Macros for apic_extnmi which controls external NMI masking */ 26 #define APIC_EXTNMI_BSP 0 /* Default */ 27 #define APIC_EXTNMI_ALL 1 28 #define APIC_EXTNMI_NONE 2 29 30 /* 31 * Define the default level of output to be very little 32 * This can be turned up by using apic=verbose for more 33 * information and apic=debug for _lots_ of information. 34 * apic_verbosity is defined in apic.c 35 */ 36 #define apic_printk(v, s, a...) do { \ 37 if ((v) <= apic_verbosity) \ 38 printk(s, ##a); \ 39 } while (0) 40 41 42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 43 extern void x86_32_probe_apic(void); 44 #else 45 static inline void x86_32_probe_apic(void) { } 46 #endif 47 48 #ifdef CONFIG_X86_LOCAL_APIC 49 50 extern int apic_verbosity; 51 extern int local_apic_timer_c2_ok; 52 53 extern bool apic_is_disabled; 54 extern unsigned int lapic_timer_period; 55 56 extern int cpuid_to_apicid[]; 57 58 extern enum apic_intr_mode_id apic_intr_mode; 59 enum apic_intr_mode_id { 60 APIC_PIC, 61 APIC_VIRTUAL_WIRE, 62 APIC_VIRTUAL_WIRE_NO_CONFIG, 63 APIC_SYMMETRIC_IO, 64 APIC_SYMMETRIC_IO_NO_ROUTING 65 }; 66 67 /* 68 * With 82489DX we can't rely on apic feature bit 69 * retrieved via cpuid but still have to deal with 70 * such an apic chip so we assume that SMP configuration 71 * is found from MP table (64bit case uses ACPI mostly 72 * which set smp presence flag as well so we are safe 73 * to use this helper too). 74 */ 75 static inline bool apic_from_smp_config(void) 76 { 77 return smp_found_config && !apic_is_disabled; 78 } 79 80 /* 81 * Basic functions accessing APICs. 82 */ 83 #ifdef CONFIG_PARAVIRT 84 #include <asm/paravirt.h> 85 #endif 86 87 static inline void native_apic_mem_write(u32 reg, u32 v) 88 { 89 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 90 91 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 92 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 93 ASM_OUTPUT2("0" (v), "m" (*addr))); 94 } 95 96 static inline u32 native_apic_mem_read(u32 reg) 97 { 98 return *((volatile u32 *)(APIC_BASE + reg)); 99 } 100 101 extern void native_apic_wait_icr_idle(void); 102 extern u32 native_safe_apic_wait_icr_idle(void); 103 extern void native_apic_icr_write(u32 low, u32 id); 104 extern u64 native_apic_icr_read(void); 105 106 static inline bool apic_is_x2apic_enabled(void) 107 { 108 u64 msr; 109 110 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 111 return false; 112 return msr & X2APIC_ENABLE; 113 } 114 115 extern void enable_IR_x2apic(void); 116 117 extern int get_physical_broadcast(void); 118 119 extern int lapic_get_maxlvt(void); 120 extern void clear_local_APIC(void); 121 extern void disconnect_bsp_APIC(int virt_wire_setup); 122 extern void disable_local_APIC(void); 123 extern void apic_soft_disable(void); 124 extern void lapic_shutdown(void); 125 extern void sync_Arb_IDs(void); 126 extern void init_bsp_APIC(void); 127 extern void apic_intr_mode_select(void); 128 extern void apic_intr_mode_init(void); 129 extern void init_apic_mappings(void); 130 void register_lapic_address(unsigned long address); 131 extern void setup_boot_APIC_clock(void); 132 extern void setup_secondary_APIC_clock(void); 133 extern void lapic_update_tsc_freq(void); 134 135 #ifdef CONFIG_X86_64 136 static inline bool apic_force_enable(unsigned long addr) 137 { 138 return false; 139 } 140 #else 141 extern bool apic_force_enable(unsigned long addr); 142 #endif 143 144 extern void apic_ap_setup(void); 145 146 /* 147 * On 32bit this is mach-xxx local 148 */ 149 #ifdef CONFIG_X86_64 150 extern int apic_is_clustered_box(void); 151 #else 152 static inline int apic_is_clustered_box(void) 153 { 154 return 0; 155 } 156 #endif 157 158 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 159 extern void lapic_assign_system_vectors(void); 160 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 161 extern void lapic_update_legacy_vectors(void); 162 extern void lapic_online(void); 163 extern void lapic_offline(void); 164 extern bool apic_needs_pit(void); 165 166 extern void apic_send_IPI_allbutself(unsigned int vector); 167 168 #else /* !CONFIG_X86_LOCAL_APIC */ 169 static inline void lapic_shutdown(void) { } 170 #define local_apic_timer_c2_ok 1 171 static inline void init_apic_mappings(void) { } 172 static inline void disable_local_APIC(void) { } 173 # define setup_boot_APIC_clock x86_init_noop 174 # define setup_secondary_APIC_clock x86_init_noop 175 static inline void lapic_update_tsc_freq(void) { } 176 static inline void init_bsp_APIC(void) { } 177 static inline void apic_intr_mode_select(void) { } 178 static inline void apic_intr_mode_init(void) { } 179 static inline void lapic_assign_system_vectors(void) { } 180 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 181 static inline bool apic_needs_pit(void) { return true; } 182 #endif /* !CONFIG_X86_LOCAL_APIC */ 183 184 #ifdef CONFIG_X86_X2APIC 185 static inline void native_apic_msr_write(u32 reg, u32 v) 186 { 187 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 188 reg == APIC_LVR) 189 return; 190 191 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 192 } 193 194 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 195 { 196 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 197 } 198 199 static inline u32 native_apic_msr_read(u32 reg) 200 { 201 u64 msr; 202 203 if (reg == APIC_DFR) 204 return -1; 205 206 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 207 return (u32)msr; 208 } 209 210 static inline void native_x2apic_wait_icr_idle(void) 211 { 212 /* no need to wait for icr idle in x2apic */ 213 return; 214 } 215 216 static inline u32 native_safe_x2apic_wait_icr_idle(void) 217 { 218 /* no need to wait for icr idle in x2apic */ 219 return 0; 220 } 221 222 static inline void native_x2apic_icr_write(u32 low, u32 id) 223 { 224 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 225 } 226 227 static inline u64 native_x2apic_icr_read(void) 228 { 229 unsigned long val; 230 231 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 232 return val; 233 } 234 235 extern int x2apic_mode; 236 extern int x2apic_phys; 237 extern void __init x2apic_set_max_apicid(u32 apicid); 238 extern void x2apic_setup(void); 239 static inline int x2apic_enabled(void) 240 { 241 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 242 } 243 244 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 245 #else /* !CONFIG_X86_X2APIC */ 246 static inline void x2apic_setup(void) { } 247 static inline int x2apic_enabled(void) { return 0; } 248 static inline u32 native_apic_msr_read(u32 reg) { BUG(); } 249 #define x2apic_mode (0) 250 #define x2apic_supported() (0) 251 #endif /* !CONFIG_X86_X2APIC */ 252 extern void __init check_x2apic(void); 253 254 struct irq_data; 255 256 /* 257 * Copyright 2004 James Cleverdon, IBM. 258 * 259 * Generic APIC sub-arch data struct. 260 * 261 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 262 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 263 * James Cleverdon. 264 */ 265 struct apic { 266 /* Hotpath functions first */ 267 void (*eoi_write)(u32 reg, u32 v); 268 void (*native_eoi_write)(u32 reg, u32 v); 269 void (*write)(u32 reg, u32 v); 270 u32 (*read)(u32 reg); 271 272 /* IPI related functions */ 273 void (*wait_icr_idle)(void); 274 u32 (*safe_wait_icr_idle)(void); 275 276 void (*send_IPI)(int cpu, int vector); 277 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 278 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 279 void (*send_IPI_allbutself)(int vector); 280 void (*send_IPI_all)(int vector); 281 void (*send_IPI_self)(int vector); 282 283 u32 disable_esr; 284 285 enum apic_delivery_modes delivery_mode; 286 bool dest_mode_logical; 287 288 u32 (*calc_dest_apicid)(unsigned int cpu); 289 290 /* ICR related functions */ 291 u64 (*icr_read)(void); 292 void (*icr_write)(u32 low, u32 high); 293 294 /* Probe, setup and smpboot functions */ 295 int (*probe)(void); 296 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 297 int (*apic_id_valid)(u32 apicid); 298 int (*apic_id_registered)(void); 299 300 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 301 void (*init_apic_ldr)(void); 302 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 303 int (*cpu_present_to_apicid)(int mps_cpu); 304 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 305 306 u32 (*get_apic_id)(unsigned long x); 307 u32 (*set_apic_id)(unsigned int id); 308 309 /* wakeup_secondary_cpu */ 310 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 311 /* wakeup secondary CPU using 64-bit wakeup point */ 312 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); 313 314 char *name; 315 }; 316 317 /* 318 * Pointer to the local APIC driver in use on this system (there's 319 * always just one such driver in use - the kernel decides via an 320 * early probing process which one it picks - and then sticks to it): 321 */ 322 extern struct apic *apic; 323 324 /* 325 * APIC drivers are probed based on how they are listed in the .apicdrivers 326 * section. So the order is important and enforced by the ordering 327 * of different apic driver files in the Makefile. 328 * 329 * For the files having two apic drivers, we use apic_drivers() 330 * to enforce the order with in them. 331 */ 332 #define apic_driver(sym) \ 333 static const struct apic *__apicdrivers_##sym __used \ 334 __aligned(sizeof(struct apic *)) \ 335 __section(".apicdrivers") = { &sym } 336 337 #define apic_drivers(sym1, sym2) \ 338 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 339 __aligned(sizeof(struct apic *)) \ 340 __section(".apicdrivers") = { &sym1, &sym2 } 341 342 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 343 344 /* 345 * APIC functionality to boot other CPUs - only used on SMP: 346 */ 347 #ifdef CONFIG_SMP 348 extern int lapic_can_unplug_cpu(void); 349 #endif 350 351 #ifdef CONFIG_X86_LOCAL_APIC 352 353 static inline u32 apic_read(u32 reg) 354 { 355 return apic->read(reg); 356 } 357 358 static inline void apic_write(u32 reg, u32 val) 359 { 360 apic->write(reg, val); 361 } 362 363 static inline void apic_eoi(void) 364 { 365 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 366 } 367 368 static inline u64 apic_icr_read(void) 369 { 370 return apic->icr_read(); 371 } 372 373 static inline void apic_icr_write(u32 low, u32 high) 374 { 375 apic->icr_write(low, high); 376 } 377 378 static inline void apic_wait_icr_idle(void) 379 { 380 apic->wait_icr_idle(); 381 } 382 383 static inline u32 safe_apic_wait_icr_idle(void) 384 { 385 return apic->safe_wait_icr_idle(); 386 } 387 388 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 389 390 #else /* CONFIG_X86_LOCAL_APIC */ 391 392 static inline u32 apic_read(u32 reg) { return 0; } 393 static inline void apic_write(u32 reg, u32 val) { } 394 static inline void apic_eoi(void) { } 395 static inline u64 apic_icr_read(void) { return 0; } 396 static inline void apic_icr_write(u32 low, u32 high) { } 397 static inline void apic_wait_icr_idle(void) { } 398 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 399 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 400 401 #endif /* CONFIG_X86_LOCAL_APIC */ 402 403 extern void apic_ack_irq(struct irq_data *data); 404 405 static inline void ack_APIC_irq(void) 406 { 407 /* 408 * ack_APIC_irq() actually gets compiled as a single instruction 409 * ... yummie. 410 */ 411 apic_eoi(); 412 } 413 414 415 static inline bool lapic_vector_set_in_irr(unsigned int vector) 416 { 417 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 418 419 return !!(irr & (1U << (vector % 32))); 420 } 421 422 static inline unsigned default_get_apic_id(unsigned long x) 423 { 424 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 425 426 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 427 return (x >> 24) & 0xFF; 428 else 429 return (x >> 24) & 0x0F; 430 } 431 432 /* 433 * Warm reset vector position: 434 */ 435 #define TRAMPOLINE_PHYS_LOW 0x467 436 #define TRAMPOLINE_PHYS_HIGH 0x469 437 438 extern void generic_bigsmp_probe(void); 439 440 #ifdef CONFIG_X86_LOCAL_APIC 441 442 #include <asm/smp.h> 443 444 extern struct apic apic_noop; 445 446 static inline unsigned int read_apic_id(void) 447 { 448 unsigned int reg = apic_read(APIC_ID); 449 450 return apic->get_apic_id(reg); 451 } 452 453 #ifdef CONFIG_X86_64 454 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 455 extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); 456 extern int default_acpi_madt_oem_check(char *, char *); 457 extern void x86_64_probe_apic(void); 458 #else 459 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } 460 static inline void x86_64_probe_apic(void) { } 461 #endif 462 463 extern int default_apic_id_valid(u32 apicid); 464 465 extern u32 apic_default_calc_apicid(unsigned int cpu); 466 extern u32 apic_flat_calc_apicid(unsigned int cpu); 467 468 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 469 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 470 extern int default_cpu_present_to_apicid(int mps_cpu); 471 472 #else /* CONFIG_X86_LOCAL_APIC */ 473 474 static inline unsigned int read_apic_id(void) { return 0; } 475 476 #endif /* !CONFIG_X86_LOCAL_APIC */ 477 478 #ifdef CONFIG_SMP 479 void apic_smt_update(void); 480 #else 481 static inline void apic_smt_update(void) { } 482 #endif 483 484 struct msi_msg; 485 struct irq_cfg; 486 487 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 488 bool dmar); 489 490 extern void ioapic_zap_locks(void); 491 492 #endif /* _ASM_X86_APIC_H */ 493