1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/idle.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* 27 * Define the default level of output to be very little 28 * This can be turned up by using apic=verbose for more 29 * information and apic=debug for _lots_ of information. 30 * apic_verbosity is defined in apic.c 31 */ 32 #define apic_printk(v, s, a...) do { \ 33 if ((v) <= apic_verbosity) \ 34 printk(s, ##a); \ 35 } while (0) 36 37 38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39 extern void generic_apic_probe(void); 40 #else 41 static inline void generic_apic_probe(void) 42 { 43 } 44 #endif 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 48 extern unsigned int apic_verbosity; 49 extern int local_apic_timer_c2_ok; 50 51 extern int disable_apic; 52 extern unsigned int lapic_timer_frequency; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 extern int setup_profiling_timer(unsigned int); 89 90 static inline void native_apic_mem_write(u32 reg, u32 v) 91 { 92 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 93 94 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, 95 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 96 ASM_OUTPUT2("0" (v), "m" (*addr))); 97 } 98 99 static inline u32 native_apic_mem_read(u32 reg) 100 { 101 return *((volatile u32 *)(APIC_BASE + reg)); 102 } 103 104 extern void native_apic_wait_icr_idle(void); 105 extern u32 native_safe_apic_wait_icr_idle(void); 106 extern void native_apic_icr_write(u32 low, u32 id); 107 extern u64 native_apic_icr_read(void); 108 109 static inline bool apic_is_x2apic_enabled(void) 110 { 111 u64 msr; 112 113 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 114 return false; 115 return msr & X2APIC_ENABLE; 116 } 117 118 #ifdef CONFIG_X86_X2APIC 119 /* 120 * Make previous memory operations globally visible before 121 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 122 * mfence for this. 123 */ 124 static inline void x2apic_wrmsr_fence(void) 125 { 126 asm volatile("mfence" : : : "memory"); 127 } 128 129 static inline void native_apic_msr_write(u32 reg, u32 v) 130 { 131 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 132 reg == APIC_LVR) 133 return; 134 135 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 136 } 137 138 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 139 { 140 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 141 } 142 143 static inline u32 native_apic_msr_read(u32 reg) 144 { 145 u64 msr; 146 147 if (reg == APIC_DFR) 148 return -1; 149 150 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 151 return (u32)msr; 152 } 153 154 static inline void native_x2apic_wait_icr_idle(void) 155 { 156 /* no need to wait for icr idle in x2apic */ 157 return; 158 } 159 160 static inline u32 native_safe_x2apic_wait_icr_idle(void) 161 { 162 /* no need to wait for icr idle in x2apic */ 163 return 0; 164 } 165 166 static inline void native_x2apic_icr_write(u32 low, u32 id) 167 { 168 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 169 } 170 171 static inline u64 native_x2apic_icr_read(void) 172 { 173 unsigned long val; 174 175 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 176 return val; 177 } 178 179 extern int x2apic_mode; 180 extern int x2apic_phys; 181 extern void __init check_x2apic(void); 182 extern void x2apic_setup(void); 183 static inline int x2apic_enabled(void) 184 { 185 return cpu_has_x2apic && apic_is_x2apic_enabled(); 186 } 187 188 #define x2apic_supported() (cpu_has_x2apic) 189 #else 190 static inline void check_x2apic(void) { } 191 static inline void x2apic_setup(void) { } 192 static inline int x2apic_enabled(void) { return 0; } 193 194 #define x2apic_mode (0) 195 #define x2apic_supported() (0) 196 #endif 197 198 extern void enable_IR_x2apic(void); 199 200 extern int get_physical_broadcast(void); 201 202 extern int lapic_get_maxlvt(void); 203 extern void clear_local_APIC(void); 204 extern void disconnect_bsp_APIC(int virt_wire_setup); 205 extern void disable_local_APIC(void); 206 extern void lapic_shutdown(void); 207 extern int verify_local_APIC(void); 208 extern void sync_Arb_IDs(void); 209 extern void init_bsp_APIC(void); 210 extern void setup_local_APIC(void); 211 extern void init_apic_mappings(void); 212 void register_lapic_address(unsigned long address); 213 extern void setup_boot_APIC_clock(void); 214 extern void setup_secondary_APIC_clock(void); 215 extern int APIC_init_uniprocessor(void); 216 217 #ifdef CONFIG_X86_64 218 static inline int apic_force_enable(unsigned long addr) 219 { 220 return -1; 221 } 222 #else 223 extern int apic_force_enable(unsigned long addr); 224 #endif 225 226 extern int apic_bsp_setup(bool upmode); 227 extern void apic_ap_setup(void); 228 229 /* 230 * On 32bit this is mach-xxx local 231 */ 232 #ifdef CONFIG_X86_64 233 extern int apic_is_clustered_box(void); 234 #else 235 static inline int apic_is_clustered_box(void) 236 { 237 return 0; 238 } 239 #endif 240 241 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 242 243 #else /* !CONFIG_X86_LOCAL_APIC */ 244 static inline void lapic_shutdown(void) { } 245 #define local_apic_timer_c2_ok 1 246 static inline void init_apic_mappings(void) { } 247 static inline void disable_local_APIC(void) { } 248 # define setup_boot_APIC_clock x86_init_noop 249 # define setup_secondary_APIC_clock x86_init_noop 250 #endif /* !CONFIG_X86_LOCAL_APIC */ 251 252 #ifdef CONFIG_X86_64 253 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 254 #else 255 256 #endif 257 258 /* 259 * Copyright 2004 James Cleverdon, IBM. 260 * Subject to the GNU Public License, v.2 261 * 262 * Generic APIC sub-arch data struct. 263 * 264 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 265 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 266 * James Cleverdon. 267 */ 268 struct apic { 269 char *name; 270 271 int (*probe)(void); 272 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 273 int (*apic_id_valid)(int apicid); 274 int (*apic_id_registered)(void); 275 276 u32 irq_delivery_mode; 277 u32 irq_dest_mode; 278 279 const struct cpumask *(*target_cpus)(void); 280 281 int disable_esr; 282 283 int dest_logical; 284 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 285 286 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 287 const struct cpumask *mask); 288 void (*init_apic_ldr)(void); 289 290 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 291 292 void (*setup_apic_routing)(void); 293 int (*cpu_present_to_apicid)(int mps_cpu); 294 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 295 int (*check_phys_apicid_present)(int phys_apicid); 296 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 297 298 unsigned int (*get_apic_id)(unsigned long x); 299 unsigned long (*set_apic_id)(unsigned int id); 300 unsigned long apic_id_mask; 301 302 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 303 const struct cpumask *andmask, 304 unsigned int *apicid); 305 306 /* ipi */ 307 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 308 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 309 int vector); 310 void (*send_IPI_allbutself)(int vector); 311 void (*send_IPI_all)(int vector); 312 void (*send_IPI_self)(int vector); 313 314 /* wakeup_secondary_cpu */ 315 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 316 317 bool wait_for_init_deassert; 318 void (*inquire_remote_apic)(int apicid); 319 320 /* apic ops */ 321 u32 (*read)(u32 reg); 322 void (*write)(u32 reg, u32 v); 323 /* 324 * ->eoi_write() has the same signature as ->write(). 325 * 326 * Drivers can support both ->eoi_write() and ->write() by passing the same 327 * callback value. Kernel can override ->eoi_write() and fall back 328 * on write for EOI. 329 */ 330 void (*eoi_write)(u32 reg, u32 v); 331 u64 (*icr_read)(void); 332 void (*icr_write)(u32 low, u32 high); 333 void (*wait_icr_idle)(void); 334 u32 (*safe_wait_icr_idle)(void); 335 336 #ifdef CONFIG_X86_32 337 /* 338 * Called very early during boot from get_smp_config(). It should 339 * return the logical apicid. x86_[bios]_cpu_to_apicid is 340 * initialized before this function is called. 341 * 342 * If logical apicid can't be determined that early, the function 343 * may return BAD_APICID. Logical apicid will be configured after 344 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 345 * won't be applied properly during early boot in this case. 346 */ 347 int (*x86_32_early_logical_apicid)(int cpu); 348 #endif 349 }; 350 351 /* 352 * Pointer to the local APIC driver in use on this system (there's 353 * always just one such driver in use - the kernel decides via an 354 * early probing process which one it picks - and then sticks to it): 355 */ 356 extern struct apic *apic; 357 358 /* 359 * APIC drivers are probed based on how they are listed in the .apicdrivers 360 * section. So the order is important and enforced by the ordering 361 * of different apic driver files in the Makefile. 362 * 363 * For the files having two apic drivers, we use apic_drivers() 364 * to enforce the order with in them. 365 */ 366 #define apic_driver(sym) \ 367 static const struct apic *__apicdrivers_##sym __used \ 368 __aligned(sizeof(struct apic *)) \ 369 __section(.apicdrivers) = { &sym } 370 371 #define apic_drivers(sym1, sym2) \ 372 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 373 __aligned(sizeof(struct apic *)) \ 374 __section(.apicdrivers) = { &sym1, &sym2 } 375 376 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 377 378 /* 379 * APIC functionality to boot other CPUs - only used on SMP: 380 */ 381 #ifdef CONFIG_SMP 382 extern atomic_t init_deasserted; 383 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 384 #endif 385 386 #ifdef CONFIG_X86_LOCAL_APIC 387 388 static inline u32 apic_read(u32 reg) 389 { 390 return apic->read(reg); 391 } 392 393 static inline void apic_write(u32 reg, u32 val) 394 { 395 apic->write(reg, val); 396 } 397 398 static inline void apic_eoi(void) 399 { 400 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 401 } 402 403 static inline u64 apic_icr_read(void) 404 { 405 return apic->icr_read(); 406 } 407 408 static inline void apic_icr_write(u32 low, u32 high) 409 { 410 apic->icr_write(low, high); 411 } 412 413 static inline void apic_wait_icr_idle(void) 414 { 415 apic->wait_icr_idle(); 416 } 417 418 static inline u32 safe_apic_wait_icr_idle(void) 419 { 420 return apic->safe_wait_icr_idle(); 421 } 422 423 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 424 425 #else /* CONFIG_X86_LOCAL_APIC */ 426 427 static inline u32 apic_read(u32 reg) { return 0; } 428 static inline void apic_write(u32 reg, u32 val) { } 429 static inline void apic_eoi(void) { } 430 static inline u64 apic_icr_read(void) { return 0; } 431 static inline void apic_icr_write(u32 low, u32 high) { } 432 static inline void apic_wait_icr_idle(void) { } 433 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 434 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 435 436 #endif /* CONFIG_X86_LOCAL_APIC */ 437 438 static inline void ack_APIC_irq(void) 439 { 440 /* 441 * ack_APIC_irq() actually gets compiled as a single instruction 442 * ... yummie. 443 */ 444 apic_eoi(); 445 } 446 447 static inline unsigned default_get_apic_id(unsigned long x) 448 { 449 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 450 451 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 452 return (x >> 24) & 0xFF; 453 else 454 return (x >> 24) & 0x0F; 455 } 456 457 /* 458 * Warm reset vector position: 459 */ 460 #define TRAMPOLINE_PHYS_LOW 0x467 461 #define TRAMPOLINE_PHYS_HIGH 0x469 462 463 #ifdef CONFIG_X86_64 464 extern void apic_send_IPI_self(int vector); 465 466 DECLARE_PER_CPU(int, x2apic_extra_bits); 467 468 extern int default_cpu_present_to_apicid(int mps_cpu); 469 extern int default_check_phys_apicid_present(int phys_apicid); 470 #endif 471 472 extern void generic_bigsmp_probe(void); 473 474 475 #ifdef CONFIG_X86_LOCAL_APIC 476 477 #include <asm/smp.h> 478 479 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 480 481 static inline const struct cpumask *default_target_cpus(void) 482 { 483 #ifdef CONFIG_SMP 484 return cpu_online_mask; 485 #else 486 return cpumask_of(0); 487 #endif 488 } 489 490 static inline const struct cpumask *online_target_cpus(void) 491 { 492 return cpu_online_mask; 493 } 494 495 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 496 497 498 static inline unsigned int read_apic_id(void) 499 { 500 unsigned int reg; 501 502 reg = apic_read(APIC_ID); 503 504 return apic->get_apic_id(reg); 505 } 506 507 static inline int default_apic_id_valid(int apicid) 508 { 509 return (apicid < 255); 510 } 511 512 extern int default_acpi_madt_oem_check(char *, char *); 513 514 extern void default_setup_apic_routing(void); 515 516 extern struct apic apic_noop; 517 518 #ifdef CONFIG_X86_32 519 520 static inline int noop_x86_32_early_logical_apicid(int cpu) 521 { 522 return BAD_APICID; 523 } 524 525 /* 526 * Set up the logical destination ID. 527 * 528 * Intel recommends to set DFR, LDR and TPR before enabling 529 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 530 * document number 292116). So here it goes... 531 */ 532 extern void default_init_apic_ldr(void); 533 534 static inline int default_apic_id_registered(void) 535 { 536 return physid_isset(read_apic_id(), phys_cpu_present_map); 537 } 538 539 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 540 { 541 return cpuid_apic >> index_msb; 542 } 543 544 #endif 545 546 static inline int 547 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 548 const struct cpumask *andmask, 549 unsigned int *apicid) 550 { 551 unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 552 cpumask_bits(andmask)[0] & 553 cpumask_bits(cpu_online_mask)[0] & 554 APIC_ALL_CPUS; 555 556 if (likely(cpu_mask)) { 557 *apicid = (unsigned int)cpu_mask; 558 return 0; 559 } else { 560 return -EINVAL; 561 } 562 } 563 564 extern int 565 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 566 const struct cpumask *andmask, 567 unsigned int *apicid); 568 569 static inline void 570 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 571 const struct cpumask *mask) 572 { 573 /* Careful. Some cpus do not strictly honor the set of cpus 574 * specified in the interrupt destination when using lowest 575 * priority interrupt delivery mode. 576 * 577 * In particular there was a hyperthreading cpu observed to 578 * deliver interrupts to the wrong hyperthread when only one 579 * hyperthread was specified in the interrupt desitination. 580 */ 581 cpumask_clear(retmask); 582 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 583 } 584 585 static inline void 586 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 587 const struct cpumask *mask) 588 { 589 cpumask_copy(retmask, cpumask_of(cpu)); 590 } 591 592 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 593 { 594 return physid_isset(apicid, *map); 595 } 596 597 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 598 { 599 *retmap = *phys_map; 600 } 601 602 static inline int __default_cpu_present_to_apicid(int mps_cpu) 603 { 604 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 605 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 606 else 607 return BAD_APICID; 608 } 609 610 static inline int 611 __default_check_phys_apicid_present(int phys_apicid) 612 { 613 return physid_isset(phys_apicid, phys_cpu_present_map); 614 } 615 616 #ifdef CONFIG_X86_32 617 static inline int default_cpu_present_to_apicid(int mps_cpu) 618 { 619 return __default_cpu_present_to_apicid(mps_cpu); 620 } 621 622 static inline int 623 default_check_phys_apicid_present(int phys_apicid) 624 { 625 return __default_check_phys_apicid_present(phys_apicid); 626 } 627 #else 628 extern int default_cpu_present_to_apicid(int mps_cpu); 629 extern int default_check_phys_apicid_present(int phys_apicid); 630 #endif 631 632 #endif /* CONFIG_X86_LOCAL_APIC */ 633 extern void irq_enter(void); 634 extern void irq_exit(void); 635 636 static inline void entering_irq(void) 637 { 638 irq_enter(); 639 exit_idle(); 640 } 641 642 static inline void entering_ack_irq(void) 643 { 644 ack_APIC_irq(); 645 entering_irq(); 646 } 647 648 static inline void exiting_irq(void) 649 { 650 irq_exit(); 651 } 652 653 static inline void exiting_ack_irq(void) 654 { 655 irq_exit(); 656 /* Ack only at the end to avoid potential reentry */ 657 ack_APIC_irq(); 658 } 659 660 extern void ioapic_zap_locks(void); 661 662 #endif /* _ASM_X86_APIC_H */ 663