1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/delay.h> 6 #include <linux/pm.h> 7 8 #include <asm/alternative.h> 9 #include <asm/cpufeature.h> 10 #include <asm/processor.h> 11 #include <asm/apicdef.h> 12 #include <asm/atomic.h> 13 #include <asm/fixmap.h> 14 #include <asm/mpspec.h> 15 #include <asm/system.h> 16 #include <asm/msr.h> 17 18 #define ARCH_APICTIMER_STOPS_ON_C3 1 19 20 /* 21 * Debugging macros 22 */ 23 #define APIC_QUIET 0 24 #define APIC_VERBOSE 1 25 #define APIC_DEBUG 2 26 27 /* 28 * Define the default level of output to be very little 29 * This can be turned up by using apic=verbose for more 30 * information and apic=debug for _lots_ of information. 31 * apic_verbosity is defined in apic.c 32 */ 33 #define apic_printk(v, s, a...) do { \ 34 if ((v) <= apic_verbosity) \ 35 printk(s, ##a); \ 36 } while (0) 37 38 39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 40 extern void generic_apic_probe(void); 41 #else 42 static inline void generic_apic_probe(void) 43 { 44 } 45 #endif 46 47 #ifdef CONFIG_X86_LOCAL_APIC 48 49 extern unsigned int apic_verbosity; 50 extern int local_apic_timer_c2_ok; 51 52 extern int disable_apic; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 #ifdef CONFIG_X86_64 89 extern int is_vsmp_box(void); 90 #else 91 static inline int is_vsmp_box(void) 92 { 93 return 0; 94 } 95 #endif 96 extern void xapic_wait_icr_idle(void); 97 extern u32 safe_xapic_wait_icr_idle(void); 98 extern void xapic_icr_write(u32, u32); 99 extern int setup_profiling_timer(unsigned int); 100 101 static inline void native_apic_mem_write(u32 reg, u32 v) 102 { 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108 } 109 110 static inline u32 native_apic_mem_read(u32 reg) 111 { 112 return *((volatile u32 *)(APIC_BASE + reg)); 113 } 114 115 extern void native_apic_wait_icr_idle(void); 116 extern u32 native_safe_apic_wait_icr_idle(void); 117 extern void native_apic_icr_write(u32 low, u32 id); 118 extern u64 native_apic_icr_read(void); 119 120 extern int x2apic_mode; 121 122 #ifdef CONFIG_X86_X2APIC 123 /* 124 * Make previous memory operations globally visible before 125 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 126 * mfence for this. 127 */ 128 static inline void x2apic_wrmsr_fence(void) 129 { 130 asm volatile("mfence" : : : "memory"); 131 } 132 133 static inline void native_apic_msr_write(u32 reg, u32 v) 134 { 135 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 136 reg == APIC_LVR) 137 return; 138 139 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 140 } 141 142 static inline u32 native_apic_msr_read(u32 reg) 143 { 144 u32 low, high; 145 146 if (reg == APIC_DFR) 147 return -1; 148 149 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); 150 return low; 151 } 152 153 static inline void native_x2apic_wait_icr_idle(void) 154 { 155 /* no need to wait for icr idle in x2apic */ 156 return; 157 } 158 159 static inline u32 native_safe_x2apic_wait_icr_idle(void) 160 { 161 /* no need to wait for icr idle in x2apic */ 162 return 0; 163 } 164 165 static inline void native_x2apic_icr_write(u32 low, u32 id) 166 { 167 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 168 } 169 170 static inline u64 native_x2apic_icr_read(void) 171 { 172 unsigned long val; 173 174 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 175 return val; 176 } 177 178 extern int x2apic_phys; 179 extern void check_x2apic(void); 180 extern void enable_x2apic(void); 181 extern void x2apic_icr_write(u32 low, u32 id); 182 static inline int x2apic_enabled(void) 183 { 184 int msr, msr2; 185 186 if (!cpu_has_x2apic) 187 return 0; 188 189 rdmsr(MSR_IA32_APICBASE, msr, msr2); 190 if (msr & X2APIC_ENABLE) 191 return 1; 192 return 0; 193 } 194 195 #define x2apic_supported() (cpu_has_x2apic) 196 static inline void x2apic_force_phys(void) 197 { 198 x2apic_phys = 1; 199 } 200 #else 201 static inline void check_x2apic(void) 202 { 203 } 204 static inline void enable_x2apic(void) 205 { 206 } 207 static inline int x2apic_enabled(void) 208 { 209 return 0; 210 } 211 static inline void x2apic_force_phys(void) 212 { 213 } 214 215 #define x2apic_preenabled 0 216 #define x2apic_supported() 0 217 #endif 218 219 extern void enable_IR_x2apic(void); 220 221 extern int get_physical_broadcast(void); 222 223 extern void apic_disable(void); 224 extern int lapic_get_maxlvt(void); 225 extern void clear_local_APIC(void); 226 extern void connect_bsp_APIC(void); 227 extern void disconnect_bsp_APIC(int virt_wire_setup); 228 extern void disable_local_APIC(void); 229 extern void lapic_shutdown(void); 230 extern int verify_local_APIC(void); 231 extern void cache_APIC_registers(void); 232 extern void sync_Arb_IDs(void); 233 extern void init_bsp_APIC(void); 234 extern void setup_local_APIC(void); 235 extern void end_local_APIC_setup(void); 236 extern void init_apic_mappings(void); 237 extern void setup_boot_APIC_clock(void); 238 extern void setup_secondary_APIC_clock(void); 239 extern int APIC_init_uniprocessor(void); 240 extern void enable_NMI_through_LVT0(void); 241 242 /* 243 * On 32bit this is mach-xxx local 244 */ 245 #ifdef CONFIG_X86_64 246 extern void early_init_lapic_mapping(void); 247 extern int apic_is_clustered_box(void); 248 #else 249 static inline int apic_is_clustered_box(void) 250 { 251 return 0; 252 } 253 #endif 254 255 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 256 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 257 258 259 #else /* !CONFIG_X86_LOCAL_APIC */ 260 static inline void lapic_shutdown(void) { } 261 #define local_apic_timer_c2_ok 1 262 static inline void init_apic_mappings(void) { } 263 static inline void disable_local_APIC(void) { } 264 static inline void apic_disable(void) { } 265 # define setup_boot_APIC_clock x86_init_noop 266 # define setup_secondary_APIC_clock x86_init_noop 267 #endif /* !CONFIG_X86_LOCAL_APIC */ 268 269 #ifdef CONFIG_X86_64 270 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 271 #else 272 273 #endif 274 275 /* 276 * Copyright 2004 James Cleverdon, IBM. 277 * Subject to the GNU Public License, v.2 278 * 279 * Generic APIC sub-arch data struct. 280 * 281 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 282 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 283 * James Cleverdon. 284 */ 285 struct apic { 286 char *name; 287 288 int (*probe)(void); 289 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 290 int (*apic_id_registered)(void); 291 292 u32 irq_delivery_mode; 293 u32 irq_dest_mode; 294 295 const struct cpumask *(*target_cpus)(void); 296 297 int disable_esr; 298 299 int dest_logical; 300 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 301 unsigned long (*check_apicid_present)(int apicid); 302 303 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 304 void (*init_apic_ldr)(void); 305 306 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 307 308 void (*setup_apic_routing)(void); 309 int (*multi_timer_check)(int apic, int irq); 310 int (*apicid_to_node)(int logical_apicid); 311 int (*cpu_to_logical_apicid)(int cpu); 312 int (*cpu_present_to_apicid)(int mps_cpu); 313 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 314 void (*setup_portio_remap)(void); 315 int (*check_phys_apicid_present)(int phys_apicid); 316 void (*enable_apic_mode)(void); 317 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 318 319 /* 320 * When one of the next two hooks returns 1 the apic 321 * is switched to this. Essentially they are additional 322 * probe functions: 323 */ 324 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 325 326 unsigned int (*get_apic_id)(unsigned long x); 327 unsigned long (*set_apic_id)(unsigned int id); 328 unsigned long apic_id_mask; 329 330 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 331 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 332 const struct cpumask *andmask); 333 334 /* ipi */ 335 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 336 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 337 int vector); 338 void (*send_IPI_allbutself)(int vector); 339 void (*send_IPI_all)(int vector); 340 void (*send_IPI_self)(int vector); 341 342 /* wakeup_secondary_cpu */ 343 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 344 345 int trampoline_phys_low; 346 int trampoline_phys_high; 347 348 void (*wait_for_init_deassert)(atomic_t *deassert); 349 void (*smp_callin_clear_local_apic)(void); 350 void (*inquire_remote_apic)(int apicid); 351 352 /* apic ops */ 353 u32 (*read)(u32 reg); 354 void (*write)(u32 reg, u32 v); 355 u64 (*icr_read)(void); 356 void (*icr_write)(u32 low, u32 high); 357 void (*wait_icr_idle)(void); 358 u32 (*safe_wait_icr_idle)(void); 359 }; 360 361 /* 362 * Pointer to the local APIC driver in use on this system (there's 363 * always just one such driver in use - the kernel decides via an 364 * early probing process which one it picks - and then sticks to it): 365 */ 366 extern struct apic *apic; 367 368 /* 369 * APIC functionality to boot other CPUs - only used on SMP: 370 */ 371 #ifdef CONFIG_SMP 372 extern atomic_t init_deasserted; 373 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 374 #endif 375 376 static inline u32 apic_read(u32 reg) 377 { 378 return apic->read(reg); 379 } 380 381 static inline void apic_write(u32 reg, u32 val) 382 { 383 apic->write(reg, val); 384 } 385 386 static inline u64 apic_icr_read(void) 387 { 388 return apic->icr_read(); 389 } 390 391 static inline void apic_icr_write(u32 low, u32 high) 392 { 393 apic->icr_write(low, high); 394 } 395 396 static inline void apic_wait_icr_idle(void) 397 { 398 apic->wait_icr_idle(); 399 } 400 401 static inline u32 safe_apic_wait_icr_idle(void) 402 { 403 return apic->safe_wait_icr_idle(); 404 } 405 406 407 static inline void ack_APIC_irq(void) 408 { 409 #ifdef CONFIG_X86_LOCAL_APIC 410 /* 411 * ack_APIC_irq() actually gets compiled as a single instruction 412 * ... yummie. 413 */ 414 415 /* Docs say use 0 for future compatibility */ 416 apic_write(APIC_EOI, 0); 417 #endif 418 } 419 420 static inline unsigned default_get_apic_id(unsigned long x) 421 { 422 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 423 424 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 425 return (x >> 24) & 0xFF; 426 else 427 return (x >> 24) & 0x0F; 428 } 429 430 /* 431 * Warm reset vector default position: 432 */ 433 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 434 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 435 436 #ifdef CONFIG_X86_64 437 extern struct apic apic_flat; 438 extern struct apic apic_physflat; 439 extern struct apic apic_x2apic_cluster; 440 extern struct apic apic_x2apic_phys; 441 extern int default_acpi_madt_oem_check(char *, char *); 442 443 extern void apic_send_IPI_self(int vector); 444 445 extern struct apic apic_x2apic_uv_x; 446 DECLARE_PER_CPU(int, x2apic_extra_bits); 447 448 extern int default_cpu_present_to_apicid(int mps_cpu); 449 extern int default_check_phys_apicid_present(int phys_apicid); 450 #endif 451 452 static inline void default_wait_for_init_deassert(atomic_t *deassert) 453 { 454 while (!atomic_read(deassert)) 455 cpu_relax(); 456 return; 457 } 458 459 extern void generic_bigsmp_probe(void); 460 461 462 #ifdef CONFIG_X86_LOCAL_APIC 463 464 #include <asm/smp.h> 465 466 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 467 468 static inline const struct cpumask *default_target_cpus(void) 469 { 470 #ifdef CONFIG_SMP 471 return cpu_online_mask; 472 #else 473 return cpumask_of(0); 474 #endif 475 } 476 477 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 478 479 480 static inline unsigned int read_apic_id(void) 481 { 482 unsigned int reg; 483 484 reg = apic_read(APIC_ID); 485 486 return apic->get_apic_id(reg); 487 } 488 489 extern void default_setup_apic_routing(void); 490 491 extern struct apic apic_noop; 492 493 #ifdef CONFIG_X86_32 494 495 extern struct apic apic_default; 496 497 /* 498 * Set up the logical destination ID. 499 * 500 * Intel recommends to set DFR, LDR and TPR before enabling 501 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 502 * document number 292116). So here it goes... 503 */ 504 extern void default_init_apic_ldr(void); 505 506 static inline int default_apic_id_registered(void) 507 { 508 return physid_isset(read_apic_id(), phys_cpu_present_map); 509 } 510 511 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 512 { 513 return cpuid_apic >> index_msb; 514 } 515 516 extern int default_apicid_to_node(int logical_apicid); 517 518 #endif 519 520 static inline unsigned int 521 default_cpu_mask_to_apicid(const struct cpumask *cpumask) 522 { 523 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 524 } 525 526 static inline unsigned int 527 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 528 const struct cpumask *andmask) 529 { 530 unsigned long mask1 = cpumask_bits(cpumask)[0]; 531 unsigned long mask2 = cpumask_bits(andmask)[0]; 532 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 533 534 return (unsigned int)(mask1 & mask2 & mask3); 535 } 536 537 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 538 { 539 return physid_isset(apicid, *map); 540 } 541 542 static inline unsigned long default_check_apicid_present(int bit) 543 { 544 return physid_isset(bit, phys_cpu_present_map); 545 } 546 547 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 548 { 549 *retmap = *phys_map; 550 } 551 552 /* Mapping from cpu number to logical apicid */ 553 static inline int default_cpu_to_logical_apicid(int cpu) 554 { 555 return 1 << cpu; 556 } 557 558 static inline int __default_cpu_present_to_apicid(int mps_cpu) 559 { 560 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 561 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 562 else 563 return BAD_APICID; 564 } 565 566 static inline int 567 __default_check_phys_apicid_present(int phys_apicid) 568 { 569 return physid_isset(phys_apicid, phys_cpu_present_map); 570 } 571 572 #ifdef CONFIG_X86_32 573 static inline int default_cpu_present_to_apicid(int mps_cpu) 574 { 575 return __default_cpu_present_to_apicid(mps_cpu); 576 } 577 578 static inline int 579 default_check_phys_apicid_present(int phys_apicid) 580 { 581 return __default_check_phys_apicid_present(phys_apicid); 582 } 583 #else 584 extern int default_cpu_present_to_apicid(int mps_cpu); 585 extern int default_check_phys_apicid_present(int phys_apicid); 586 #endif 587 588 #endif /* CONFIG_X86_LOCAL_APIC */ 589 590 #ifdef CONFIG_X86_32 591 extern u8 cpu_2_logical_apicid[NR_CPUS]; 592 #endif 593 594 #endif /* _ASM_X86_APIC_H */ 595