1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/delay.h> 6 #include <linux/pm.h> 7 8 #include <asm/alternative.h> 9 #include <asm/cpufeature.h> 10 #include <asm/processor.h> 11 #include <asm/apicdef.h> 12 #include <asm/atomic.h> 13 #include <asm/fixmap.h> 14 #include <asm/mpspec.h> 15 #include <asm/system.h> 16 #include <asm/msr.h> 17 18 #define ARCH_APICTIMER_STOPS_ON_C3 1 19 20 /* 21 * Debugging macros 22 */ 23 #define APIC_QUIET 0 24 #define APIC_VERBOSE 1 25 #define APIC_DEBUG 2 26 27 /* 28 * Define the default level of output to be very little 29 * This can be turned up by using apic=verbose for more 30 * information and apic=debug for _lots_ of information. 31 * apic_verbosity is defined in apic.c 32 */ 33 #define apic_printk(v, s, a...) do { \ 34 if ((v) <= apic_verbosity) \ 35 printk(s, ##a); \ 36 } while (0) 37 38 39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 40 extern void generic_apic_probe(void); 41 #else 42 static inline void generic_apic_probe(void) 43 { 44 } 45 #endif 46 47 #ifdef CONFIG_X86_LOCAL_APIC 48 49 extern unsigned int apic_verbosity; 50 extern int local_apic_timer_c2_ok; 51 52 extern int disable_apic; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * Basic functions accessing APICs. 70 */ 71 #ifdef CONFIG_PARAVIRT 72 #include <asm/paravirt.h> 73 #endif 74 75 #ifdef CONFIG_X86_64 76 extern int is_vsmp_box(void); 77 #else 78 static inline int is_vsmp_box(void) 79 { 80 return 0; 81 } 82 #endif 83 extern void xapic_wait_icr_idle(void); 84 extern u32 safe_xapic_wait_icr_idle(void); 85 extern void xapic_icr_write(u32, u32); 86 extern int setup_profiling_timer(unsigned int); 87 88 static inline void native_apic_mem_write(u32 reg, u32 v) 89 { 90 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 91 92 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 93 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 94 ASM_OUTPUT2("0" (v), "m" (*addr))); 95 } 96 97 static inline u32 native_apic_mem_read(u32 reg) 98 { 99 return *((volatile u32 *)(APIC_BASE + reg)); 100 } 101 102 extern void native_apic_wait_icr_idle(void); 103 extern u32 native_safe_apic_wait_icr_idle(void); 104 extern void native_apic_icr_write(u32 low, u32 id); 105 extern u64 native_apic_icr_read(void); 106 107 extern int x2apic_mode; 108 109 #ifdef CONFIG_X86_X2APIC 110 /* 111 * Make previous memory operations globally visible before 112 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 113 * mfence for this. 114 */ 115 static inline void x2apic_wrmsr_fence(void) 116 { 117 asm volatile("mfence" : : : "memory"); 118 } 119 120 static inline void native_apic_msr_write(u32 reg, u32 v) 121 { 122 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 123 reg == APIC_LVR) 124 return; 125 126 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 127 } 128 129 static inline u32 native_apic_msr_read(u32 reg) 130 { 131 u32 low, high; 132 133 if (reg == APIC_DFR) 134 return -1; 135 136 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); 137 return low; 138 } 139 140 static inline void native_x2apic_wait_icr_idle(void) 141 { 142 /* no need to wait for icr idle in x2apic */ 143 return; 144 } 145 146 static inline u32 native_safe_x2apic_wait_icr_idle(void) 147 { 148 /* no need to wait for icr idle in x2apic */ 149 return 0; 150 } 151 152 static inline void native_x2apic_icr_write(u32 low, u32 id) 153 { 154 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 155 } 156 157 static inline u64 native_x2apic_icr_read(void) 158 { 159 unsigned long val; 160 161 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 162 return val; 163 } 164 165 extern int x2apic_phys; 166 extern void check_x2apic(void); 167 extern void enable_x2apic(void); 168 extern void x2apic_icr_write(u32 low, u32 id); 169 static inline int x2apic_enabled(void) 170 { 171 int msr, msr2; 172 173 if (!cpu_has_x2apic) 174 return 0; 175 176 rdmsr(MSR_IA32_APICBASE, msr, msr2); 177 if (msr & X2APIC_ENABLE) 178 return 1; 179 return 0; 180 } 181 182 #define x2apic_supported() (cpu_has_x2apic) 183 #else 184 static inline void check_x2apic(void) 185 { 186 } 187 static inline void enable_x2apic(void) 188 { 189 } 190 static inline int x2apic_enabled(void) 191 { 192 return 0; 193 } 194 195 #define x2apic_preenabled 0 196 #define x2apic_supported() 0 197 #endif 198 199 extern void enable_IR_x2apic(void); 200 201 extern int get_physical_broadcast(void); 202 203 extern void apic_disable(void); 204 extern int lapic_get_maxlvt(void); 205 extern void clear_local_APIC(void); 206 extern void connect_bsp_APIC(void); 207 extern void disconnect_bsp_APIC(int virt_wire_setup); 208 extern void disable_local_APIC(void); 209 extern void lapic_shutdown(void); 210 extern int verify_local_APIC(void); 211 extern void cache_APIC_registers(void); 212 extern void sync_Arb_IDs(void); 213 extern void init_bsp_APIC(void); 214 extern void setup_local_APIC(void); 215 extern void end_local_APIC_setup(void); 216 extern void init_apic_mappings(void); 217 extern void setup_boot_APIC_clock(void); 218 extern void setup_secondary_APIC_clock(void); 219 extern int APIC_init_uniprocessor(void); 220 extern void enable_NMI_through_LVT0(void); 221 222 /* 223 * On 32bit this is mach-xxx local 224 */ 225 #ifdef CONFIG_X86_64 226 extern void early_init_lapic_mapping(void); 227 extern int apic_is_clustered_box(void); 228 #else 229 static inline int apic_is_clustered_box(void) 230 { 231 return 0; 232 } 233 #endif 234 235 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 236 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 237 238 239 #else /* !CONFIG_X86_LOCAL_APIC */ 240 static inline void lapic_shutdown(void) { } 241 #define local_apic_timer_c2_ok 1 242 static inline void init_apic_mappings(void) { } 243 static inline void disable_local_APIC(void) { } 244 static inline void apic_disable(void) { } 245 # define setup_boot_APIC_clock x86_init_noop 246 # define setup_secondary_APIC_clock x86_init_noop 247 #endif /* !CONFIG_X86_LOCAL_APIC */ 248 249 #ifdef CONFIG_X86_64 250 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 251 #else 252 253 #endif 254 255 /* 256 * Copyright 2004 James Cleverdon, IBM. 257 * Subject to the GNU Public License, v.2 258 * 259 * Generic APIC sub-arch data struct. 260 * 261 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 262 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 263 * James Cleverdon. 264 */ 265 struct apic { 266 char *name; 267 268 int (*probe)(void); 269 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 270 int (*apic_id_registered)(void); 271 272 u32 irq_delivery_mode; 273 u32 irq_dest_mode; 274 275 const struct cpumask *(*target_cpus)(void); 276 277 int disable_esr; 278 279 int dest_logical; 280 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid); 281 unsigned long (*check_apicid_present)(int apicid); 282 283 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 284 void (*init_apic_ldr)(void); 285 286 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map); 287 288 void (*setup_apic_routing)(void); 289 int (*multi_timer_check)(int apic, int irq); 290 int (*apicid_to_node)(int logical_apicid); 291 int (*cpu_to_logical_apicid)(int cpu); 292 int (*cpu_present_to_apicid)(int mps_cpu); 293 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid); 294 void (*setup_portio_remap)(void); 295 int (*check_phys_apicid_present)(int boot_cpu_physical_apicid); 296 void (*enable_apic_mode)(void); 297 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 298 299 /* 300 * When one of the next two hooks returns 1 the apic 301 * is switched to this. Essentially they are additional 302 * probe functions: 303 */ 304 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 305 306 unsigned int (*get_apic_id)(unsigned long x); 307 unsigned long (*set_apic_id)(unsigned int id); 308 unsigned long apic_id_mask; 309 310 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 311 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 312 const struct cpumask *andmask); 313 314 /* ipi */ 315 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 316 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 317 int vector); 318 void (*send_IPI_allbutself)(int vector); 319 void (*send_IPI_all)(int vector); 320 void (*send_IPI_self)(int vector); 321 322 /* wakeup_secondary_cpu */ 323 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 324 325 int trampoline_phys_low; 326 int trampoline_phys_high; 327 328 void (*wait_for_init_deassert)(atomic_t *deassert); 329 void (*smp_callin_clear_local_apic)(void); 330 void (*inquire_remote_apic)(int apicid); 331 332 /* apic ops */ 333 u32 (*read)(u32 reg); 334 void (*write)(u32 reg, u32 v); 335 u64 (*icr_read)(void); 336 void (*icr_write)(u32 low, u32 high); 337 void (*wait_icr_idle)(void); 338 u32 (*safe_wait_icr_idle)(void); 339 }; 340 341 /* 342 * Pointer to the local APIC driver in use on this system (there's 343 * always just one such driver in use - the kernel decides via an 344 * early probing process which one it picks - and then sticks to it): 345 */ 346 extern struct apic *apic; 347 348 /* 349 * APIC functionality to boot other CPUs - only used on SMP: 350 */ 351 #ifdef CONFIG_SMP 352 extern atomic_t init_deasserted; 353 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 354 #endif 355 356 static inline u32 apic_read(u32 reg) 357 { 358 return apic->read(reg); 359 } 360 361 static inline void apic_write(u32 reg, u32 val) 362 { 363 apic->write(reg, val); 364 } 365 366 static inline u64 apic_icr_read(void) 367 { 368 return apic->icr_read(); 369 } 370 371 static inline void apic_icr_write(u32 low, u32 high) 372 { 373 apic->icr_write(low, high); 374 } 375 376 static inline void apic_wait_icr_idle(void) 377 { 378 apic->wait_icr_idle(); 379 } 380 381 static inline u32 safe_apic_wait_icr_idle(void) 382 { 383 return apic->safe_wait_icr_idle(); 384 } 385 386 387 static inline void ack_APIC_irq(void) 388 { 389 #ifdef CONFIG_X86_LOCAL_APIC 390 /* 391 * ack_APIC_irq() actually gets compiled as a single instruction 392 * ... yummie. 393 */ 394 395 /* Docs say use 0 for future compatibility */ 396 apic_write(APIC_EOI, 0); 397 #endif 398 } 399 400 static inline unsigned default_get_apic_id(unsigned long x) 401 { 402 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 403 404 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 405 return (x >> 24) & 0xFF; 406 else 407 return (x >> 24) & 0x0F; 408 } 409 410 /* 411 * Warm reset vector default position: 412 */ 413 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 414 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 415 416 #ifdef CONFIG_X86_64 417 extern struct apic apic_flat; 418 extern struct apic apic_physflat; 419 extern struct apic apic_x2apic_cluster; 420 extern struct apic apic_x2apic_phys; 421 extern int default_acpi_madt_oem_check(char *, char *); 422 423 extern void apic_send_IPI_self(int vector); 424 425 extern struct apic apic_x2apic_uv_x; 426 DECLARE_PER_CPU(int, x2apic_extra_bits); 427 428 extern int default_cpu_present_to_apicid(int mps_cpu); 429 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); 430 #endif 431 432 static inline void default_wait_for_init_deassert(atomic_t *deassert) 433 { 434 while (!atomic_read(deassert)) 435 cpu_relax(); 436 return; 437 } 438 439 extern void generic_bigsmp_probe(void); 440 441 442 #ifdef CONFIG_X86_LOCAL_APIC 443 444 #include <asm/smp.h> 445 446 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 447 448 static inline const struct cpumask *default_target_cpus(void) 449 { 450 #ifdef CONFIG_SMP 451 return cpu_online_mask; 452 #else 453 return cpumask_of(0); 454 #endif 455 } 456 457 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 458 459 460 static inline unsigned int read_apic_id(void) 461 { 462 unsigned int reg; 463 464 reg = apic_read(APIC_ID); 465 466 return apic->get_apic_id(reg); 467 } 468 469 extern void default_setup_apic_routing(void); 470 471 #ifdef CONFIG_X86_32 472 473 extern struct apic apic_default; 474 475 /* 476 * Set up the logical destination ID. 477 * 478 * Intel recommends to set DFR, LDR and TPR before enabling 479 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 480 * document number 292116). So here it goes... 481 */ 482 extern void default_init_apic_ldr(void); 483 484 static inline int default_apic_id_registered(void) 485 { 486 return physid_isset(read_apic_id(), phys_cpu_present_map); 487 } 488 489 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 490 { 491 return cpuid_apic >> index_msb; 492 } 493 494 extern int default_apicid_to_node(int logical_apicid); 495 496 #endif 497 498 static inline unsigned int 499 default_cpu_mask_to_apicid(const struct cpumask *cpumask) 500 { 501 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 502 } 503 504 static inline unsigned int 505 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 506 const struct cpumask *andmask) 507 { 508 unsigned long mask1 = cpumask_bits(cpumask)[0]; 509 unsigned long mask2 = cpumask_bits(andmask)[0]; 510 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 511 512 return (unsigned int)(mask1 & mask2 & mask3); 513 } 514 515 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) 516 { 517 return physid_isset(apicid, bitmap); 518 } 519 520 static inline unsigned long default_check_apicid_present(int bit) 521 { 522 return physid_isset(bit, phys_cpu_present_map); 523 } 524 525 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) 526 { 527 return phys_map; 528 } 529 530 /* Mapping from cpu number to logical apicid */ 531 static inline int default_cpu_to_logical_apicid(int cpu) 532 { 533 return 1 << cpu; 534 } 535 536 static inline int __default_cpu_present_to_apicid(int mps_cpu) 537 { 538 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 539 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 540 else 541 return BAD_APICID; 542 } 543 544 static inline int 545 __default_check_phys_apicid_present(int boot_cpu_physical_apicid) 546 { 547 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); 548 } 549 550 #ifdef CONFIG_X86_32 551 static inline int default_cpu_present_to_apicid(int mps_cpu) 552 { 553 return __default_cpu_present_to_apicid(mps_cpu); 554 } 555 556 static inline int 557 default_check_phys_apicid_present(int boot_cpu_physical_apicid) 558 { 559 return __default_check_phys_apicid_present(boot_cpu_physical_apicid); 560 } 561 #else 562 extern int default_cpu_present_to_apicid(int mps_cpu); 563 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); 564 #endif 565 566 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) 567 { 568 return physid_mask_of_physid(phys_apicid); 569 } 570 571 #endif /* CONFIG_X86_LOCAL_APIC */ 572 573 #ifdef CONFIG_X86_32 574 extern u8 cpu_2_logical_apicid[NR_CPUS]; 575 #endif 576 577 #endif /* _ASM_X86_APIC_H */ 578