1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/idle.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* 27 * Define the default level of output to be very little 28 * This can be turned up by using apic=verbose for more 29 * information and apic=debug for _lots_ of information. 30 * apic_verbosity is defined in apic.c 31 */ 32 #define apic_printk(v, s, a...) do { \ 33 if ((v) <= apic_verbosity) \ 34 printk(s, ##a); \ 35 } while (0) 36 37 38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39 extern void generic_apic_probe(void); 40 #else 41 static inline void generic_apic_probe(void) 42 { 43 } 44 #endif 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 48 extern unsigned int apic_verbosity; 49 extern int local_apic_timer_c2_ok; 50 51 extern int disable_apic; 52 extern unsigned int lapic_timer_frequency; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 #ifdef CONFIG_X86_64 89 extern int is_vsmp_box(void); 90 #else 91 static inline int is_vsmp_box(void) 92 { 93 return 0; 94 } 95 #endif 96 extern int setup_profiling_timer(unsigned int); 97 98 static inline void native_apic_mem_write(u32 reg, u32 v) 99 { 100 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 101 102 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 103 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 104 ASM_OUTPUT2("0" (v), "m" (*addr))); 105 } 106 107 static inline u32 native_apic_mem_read(u32 reg) 108 { 109 return *((volatile u32 *)(APIC_BASE + reg)); 110 } 111 112 extern void native_apic_wait_icr_idle(void); 113 extern u32 native_safe_apic_wait_icr_idle(void); 114 extern void native_apic_icr_write(u32 low, u32 id); 115 extern u64 native_apic_icr_read(void); 116 117 extern int x2apic_mode; 118 119 #ifdef CONFIG_X86_X2APIC 120 /* 121 * Make previous memory operations globally visible before 122 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 123 * mfence for this. 124 */ 125 static inline void x2apic_wrmsr_fence(void) 126 { 127 asm volatile("mfence" : : : "memory"); 128 } 129 130 static inline void native_apic_msr_write(u32 reg, u32 v) 131 { 132 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 133 reg == APIC_LVR) 134 return; 135 136 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 137 } 138 139 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 140 { 141 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 142 } 143 144 static inline u32 native_apic_msr_read(u32 reg) 145 { 146 u64 msr; 147 148 if (reg == APIC_DFR) 149 return -1; 150 151 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 152 return (u32)msr; 153 } 154 155 static inline void native_x2apic_wait_icr_idle(void) 156 { 157 /* no need to wait for icr idle in x2apic */ 158 return; 159 } 160 161 static inline u32 native_safe_x2apic_wait_icr_idle(void) 162 { 163 /* no need to wait for icr idle in x2apic */ 164 return 0; 165 } 166 167 static inline void native_x2apic_icr_write(u32 low, u32 id) 168 { 169 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 170 } 171 172 static inline u64 native_x2apic_icr_read(void) 173 { 174 unsigned long val; 175 176 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 177 return val; 178 } 179 180 extern int x2apic_phys; 181 extern int x2apic_preenabled; 182 extern void check_x2apic(void); 183 extern void enable_x2apic(void); 184 static inline int x2apic_enabled(void) 185 { 186 u64 msr; 187 188 if (!cpu_has_x2apic) 189 return 0; 190 191 rdmsrl(MSR_IA32_APICBASE, msr); 192 if (msr & X2APIC_ENABLE) 193 return 1; 194 return 0; 195 } 196 197 #define x2apic_supported() (cpu_has_x2apic) 198 static inline void x2apic_force_phys(void) 199 { 200 x2apic_phys = 1; 201 } 202 #else 203 static inline void disable_x2apic(void) 204 { 205 } 206 static inline void check_x2apic(void) 207 { 208 } 209 static inline void enable_x2apic(void) 210 { 211 } 212 static inline int x2apic_enabled(void) 213 { 214 return 0; 215 } 216 static inline void x2apic_force_phys(void) 217 { 218 } 219 220 #define nox2apic 0 221 #define x2apic_preenabled 0 222 #define x2apic_supported() 0 223 #endif 224 225 extern void enable_IR_x2apic(void); 226 227 extern int get_physical_broadcast(void); 228 229 extern int lapic_get_maxlvt(void); 230 extern void clear_local_APIC(void); 231 extern void connect_bsp_APIC(void); 232 extern void disconnect_bsp_APIC(int virt_wire_setup); 233 extern void disable_local_APIC(void); 234 extern void lapic_shutdown(void); 235 extern int verify_local_APIC(void); 236 extern void sync_Arb_IDs(void); 237 extern void init_bsp_APIC(void); 238 extern void setup_local_APIC(void); 239 extern void end_local_APIC_setup(void); 240 extern void bsp_end_local_APIC_setup(void); 241 extern void init_apic_mappings(void); 242 void register_lapic_address(unsigned long address); 243 extern void setup_boot_APIC_clock(void); 244 extern void setup_secondary_APIC_clock(void); 245 extern int APIC_init_uniprocessor(void); 246 extern int apic_force_enable(unsigned long addr); 247 248 /* 249 * On 32bit this is mach-xxx local 250 */ 251 #ifdef CONFIG_X86_64 252 extern int apic_is_clustered_box(void); 253 #else 254 static inline int apic_is_clustered_box(void) 255 { 256 return 0; 257 } 258 #endif 259 260 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 261 262 #else /* !CONFIG_X86_LOCAL_APIC */ 263 static inline void lapic_shutdown(void) { } 264 #define local_apic_timer_c2_ok 1 265 static inline void init_apic_mappings(void) { } 266 static inline void disable_local_APIC(void) { } 267 # define setup_boot_APIC_clock x86_init_noop 268 # define setup_secondary_APIC_clock x86_init_noop 269 #endif /* !CONFIG_X86_LOCAL_APIC */ 270 271 #ifdef CONFIG_X86_64 272 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 273 #else 274 275 #endif 276 277 /* 278 * Copyright 2004 James Cleverdon, IBM. 279 * Subject to the GNU Public License, v.2 280 * 281 * Generic APIC sub-arch data struct. 282 * 283 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 284 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 285 * James Cleverdon. 286 */ 287 struct apic { 288 char *name; 289 290 int (*probe)(void); 291 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 292 int (*apic_id_valid)(int apicid); 293 int (*apic_id_registered)(void); 294 295 u32 irq_delivery_mode; 296 u32 irq_dest_mode; 297 298 const struct cpumask *(*target_cpus)(void); 299 300 int disable_esr; 301 302 int dest_logical; 303 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 304 unsigned long (*check_apicid_present)(int apicid); 305 306 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 307 const struct cpumask *mask); 308 void (*init_apic_ldr)(void); 309 310 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 311 312 void (*setup_apic_routing)(void); 313 int (*multi_timer_check)(int apic, int irq); 314 int (*cpu_present_to_apicid)(int mps_cpu); 315 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 316 void (*setup_portio_remap)(void); 317 int (*check_phys_apicid_present)(int phys_apicid); 318 void (*enable_apic_mode)(void); 319 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 320 321 /* 322 * When one of the next two hooks returns 1 the apic 323 * is switched to this. Essentially they are additional 324 * probe functions: 325 */ 326 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 327 328 unsigned int (*get_apic_id)(unsigned long x); 329 unsigned long (*set_apic_id)(unsigned int id); 330 unsigned long apic_id_mask; 331 332 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 333 const struct cpumask *andmask, 334 unsigned int *apicid); 335 336 /* ipi */ 337 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 338 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 339 int vector); 340 void (*send_IPI_allbutself)(int vector); 341 void (*send_IPI_all)(int vector); 342 void (*send_IPI_self)(int vector); 343 344 /* wakeup_secondary_cpu */ 345 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 346 347 int trampoline_phys_low; 348 int trampoline_phys_high; 349 350 bool wait_for_init_deassert; 351 void (*smp_callin_clear_local_apic)(void); 352 void (*inquire_remote_apic)(int apicid); 353 354 /* apic ops */ 355 u32 (*read)(u32 reg); 356 void (*write)(u32 reg, u32 v); 357 /* 358 * ->eoi_write() has the same signature as ->write(). 359 * 360 * Drivers can support both ->eoi_write() and ->write() by passing the same 361 * callback value. Kernel can override ->eoi_write() and fall back 362 * on write for EOI. 363 */ 364 void (*eoi_write)(u32 reg, u32 v); 365 u64 (*icr_read)(void); 366 void (*icr_write)(u32 low, u32 high); 367 void (*wait_icr_idle)(void); 368 u32 (*safe_wait_icr_idle)(void); 369 370 #ifdef CONFIG_X86_32 371 /* 372 * Called very early during boot from get_smp_config(). It should 373 * return the logical apicid. x86_[bios]_cpu_to_apicid is 374 * initialized before this function is called. 375 * 376 * If logical apicid can't be determined that early, the function 377 * may return BAD_APICID. Logical apicid will be configured after 378 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 379 * won't be applied properly during early boot in this case. 380 */ 381 int (*x86_32_early_logical_apicid)(int cpu); 382 383 /* 384 * Optional method called from setup_local_APIC() after logical 385 * apicid is guaranteed to be known to initialize apicid -> node 386 * mapping if NUMA initialization hasn't done so already. Don't 387 * add new users. 388 */ 389 int (*x86_32_numa_cpu_node)(int cpu); 390 #endif 391 }; 392 393 /* 394 * Pointer to the local APIC driver in use on this system (there's 395 * always just one such driver in use - the kernel decides via an 396 * early probing process which one it picks - and then sticks to it): 397 */ 398 extern struct apic *apic; 399 400 /* 401 * APIC drivers are probed based on how they are listed in the .apicdrivers 402 * section. So the order is important and enforced by the ordering 403 * of different apic driver files in the Makefile. 404 * 405 * For the files having two apic drivers, we use apic_drivers() 406 * to enforce the order with in them. 407 */ 408 #define apic_driver(sym) \ 409 static const struct apic *__apicdrivers_##sym __used \ 410 __aligned(sizeof(struct apic *)) \ 411 __section(.apicdrivers) = { &sym } 412 413 #define apic_drivers(sym1, sym2) \ 414 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 415 __aligned(sizeof(struct apic *)) \ 416 __section(.apicdrivers) = { &sym1, &sym2 } 417 418 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 419 420 /* 421 * APIC functionality to boot other CPUs - only used on SMP: 422 */ 423 #ifdef CONFIG_SMP 424 extern atomic_t init_deasserted; 425 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 426 #endif 427 428 #ifdef CONFIG_X86_LOCAL_APIC 429 430 static inline u32 apic_read(u32 reg) 431 { 432 return apic->read(reg); 433 } 434 435 static inline void apic_write(u32 reg, u32 val) 436 { 437 apic->write(reg, val); 438 } 439 440 static inline void apic_eoi(void) 441 { 442 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 443 } 444 445 static inline u64 apic_icr_read(void) 446 { 447 return apic->icr_read(); 448 } 449 450 static inline void apic_icr_write(u32 low, u32 high) 451 { 452 apic->icr_write(low, high); 453 } 454 455 static inline void apic_wait_icr_idle(void) 456 { 457 apic->wait_icr_idle(); 458 } 459 460 static inline u32 safe_apic_wait_icr_idle(void) 461 { 462 return apic->safe_wait_icr_idle(); 463 } 464 465 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 466 467 #else /* CONFIG_X86_LOCAL_APIC */ 468 469 static inline u32 apic_read(u32 reg) { return 0; } 470 static inline void apic_write(u32 reg, u32 val) { } 471 static inline void apic_eoi(void) { } 472 static inline u64 apic_icr_read(void) { return 0; } 473 static inline void apic_icr_write(u32 low, u32 high) { } 474 static inline void apic_wait_icr_idle(void) { } 475 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 476 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 477 478 #endif /* CONFIG_X86_LOCAL_APIC */ 479 480 static inline void ack_APIC_irq(void) 481 { 482 /* 483 * ack_APIC_irq() actually gets compiled as a single instruction 484 * ... yummie. 485 */ 486 apic_eoi(); 487 } 488 489 static inline unsigned default_get_apic_id(unsigned long x) 490 { 491 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 492 493 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 494 return (x >> 24) & 0xFF; 495 else 496 return (x >> 24) & 0x0F; 497 } 498 499 /* 500 * Warm reset vector default position: 501 */ 502 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 503 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 504 505 #ifdef CONFIG_X86_64 506 extern int default_acpi_madt_oem_check(char *, char *); 507 508 extern void apic_send_IPI_self(int vector); 509 510 DECLARE_PER_CPU(int, x2apic_extra_bits); 511 512 extern int default_cpu_present_to_apicid(int mps_cpu); 513 extern int default_check_phys_apicid_present(int phys_apicid); 514 #endif 515 516 extern void generic_bigsmp_probe(void); 517 518 519 #ifdef CONFIG_X86_LOCAL_APIC 520 521 #include <asm/smp.h> 522 523 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 524 525 static inline const struct cpumask *default_target_cpus(void) 526 { 527 #ifdef CONFIG_SMP 528 return cpu_online_mask; 529 #else 530 return cpumask_of(0); 531 #endif 532 } 533 534 static inline const struct cpumask *online_target_cpus(void) 535 { 536 return cpu_online_mask; 537 } 538 539 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 540 541 542 static inline unsigned int read_apic_id(void) 543 { 544 unsigned int reg; 545 546 reg = apic_read(APIC_ID); 547 548 return apic->get_apic_id(reg); 549 } 550 551 static inline int default_apic_id_valid(int apicid) 552 { 553 return (apicid < 255); 554 } 555 556 extern void default_setup_apic_routing(void); 557 558 extern struct apic apic_noop; 559 560 #ifdef CONFIG_X86_32 561 562 static inline int noop_x86_32_early_logical_apicid(int cpu) 563 { 564 return BAD_APICID; 565 } 566 567 /* 568 * Set up the logical destination ID. 569 * 570 * Intel recommends to set DFR, LDR and TPR before enabling 571 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 572 * document number 292116). So here it goes... 573 */ 574 extern void default_init_apic_ldr(void); 575 576 static inline int default_apic_id_registered(void) 577 { 578 return physid_isset(read_apic_id(), phys_cpu_present_map); 579 } 580 581 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 582 { 583 return cpuid_apic >> index_msb; 584 } 585 586 #endif 587 588 static inline int 589 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 590 const struct cpumask *andmask, 591 unsigned int *apicid) 592 { 593 unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 594 cpumask_bits(andmask)[0] & 595 cpumask_bits(cpu_online_mask)[0] & 596 APIC_ALL_CPUS; 597 598 if (likely(cpu_mask)) { 599 *apicid = (unsigned int)cpu_mask; 600 return 0; 601 } else { 602 return -EINVAL; 603 } 604 } 605 606 extern int 607 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 608 const struct cpumask *andmask, 609 unsigned int *apicid); 610 611 static inline void 612 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 613 const struct cpumask *mask) 614 { 615 /* Careful. Some cpus do not strictly honor the set of cpus 616 * specified in the interrupt destination when using lowest 617 * priority interrupt delivery mode. 618 * 619 * In particular there was a hyperthreading cpu observed to 620 * deliver interrupts to the wrong hyperthread when only one 621 * hyperthread was specified in the interrupt desitination. 622 */ 623 cpumask_clear(retmask); 624 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 625 } 626 627 static inline void 628 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 629 const struct cpumask *mask) 630 { 631 cpumask_copy(retmask, cpumask_of(cpu)); 632 } 633 634 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 635 { 636 return physid_isset(apicid, *map); 637 } 638 639 static inline unsigned long default_check_apicid_present(int bit) 640 { 641 return physid_isset(bit, phys_cpu_present_map); 642 } 643 644 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 645 { 646 *retmap = *phys_map; 647 } 648 649 static inline int __default_cpu_present_to_apicid(int mps_cpu) 650 { 651 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 652 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 653 else 654 return BAD_APICID; 655 } 656 657 static inline int 658 __default_check_phys_apicid_present(int phys_apicid) 659 { 660 return physid_isset(phys_apicid, phys_cpu_present_map); 661 } 662 663 #ifdef CONFIG_X86_32 664 static inline int default_cpu_present_to_apicid(int mps_cpu) 665 { 666 return __default_cpu_present_to_apicid(mps_cpu); 667 } 668 669 static inline int 670 default_check_phys_apicid_present(int phys_apicid) 671 { 672 return __default_check_phys_apicid_present(phys_apicid); 673 } 674 #else 675 extern int default_cpu_present_to_apicid(int mps_cpu); 676 extern int default_check_phys_apicid_present(int phys_apicid); 677 #endif 678 679 #endif /* CONFIG_X86_LOCAL_APIC */ 680 extern void irq_enter(void); 681 extern void irq_exit(void); 682 683 static inline void entering_irq(void) 684 { 685 irq_enter(); 686 exit_idle(); 687 } 688 689 static inline void entering_ack_irq(void) 690 { 691 ack_APIC_irq(); 692 entering_irq(); 693 } 694 695 static inline void exiting_irq(void) 696 { 697 irq_exit(); 698 } 699 700 static inline void exiting_ack_irq(void) 701 { 702 irq_exit(); 703 /* Ack only at the end to avoid potential reentry */ 704 ack_APIC_irq(); 705 } 706 707 extern void ioapic_zap_locks(void); 708 709 #endif /* _ASM_X86_APIC_H */ 710