1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/apicdef.h> 10 #include <linux/atomic.h> 11 #include <asm/fixmap.h> 12 #include <asm/mpspec.h> 13 #include <asm/msr.h> 14 #include <asm/hardirq.h> 15 16 #define ARCH_APICTIMER_STOPS_ON_C3 1 17 18 /* 19 * Debugging macros 20 */ 21 #define APIC_QUIET 0 22 #define APIC_VERBOSE 1 23 #define APIC_DEBUG 2 24 25 /* Macros for apic_extnmi which controls external NMI masking */ 26 #define APIC_EXTNMI_BSP 0 /* Default */ 27 #define APIC_EXTNMI_ALL 1 28 #define APIC_EXTNMI_NONE 2 29 30 /* 31 * Define the default level of output to be very little 32 * This can be turned up by using apic=verbose for more 33 * information and apic=debug for _lots_ of information. 34 * apic_verbosity is defined in apic.c 35 */ 36 #define apic_printk(v, s, a...) do { \ 37 if ((v) <= apic_verbosity) \ 38 printk(s, ##a); \ 39 } while (0) 40 41 42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 43 extern void generic_apic_probe(void); 44 #else 45 static inline void generic_apic_probe(void) 46 { 47 } 48 #endif 49 50 #ifdef CONFIG_X86_LOCAL_APIC 51 52 extern int apic_verbosity; 53 extern int local_apic_timer_c2_ok; 54 55 extern int disable_apic; 56 extern unsigned int lapic_timer_period; 57 58 extern enum apic_intr_mode_id apic_intr_mode; 59 enum apic_intr_mode_id { 60 APIC_PIC, 61 APIC_VIRTUAL_WIRE, 62 APIC_VIRTUAL_WIRE_NO_CONFIG, 63 APIC_SYMMETRIC_IO, 64 APIC_SYMMETRIC_IO_NO_ROUTING 65 }; 66 67 #ifdef CONFIG_SMP 68 extern void __inquire_remote_apic(int apicid); 69 #else /* CONFIG_SMP */ 70 static inline void __inquire_remote_apic(int apicid) 71 { 72 } 73 #endif /* CONFIG_SMP */ 74 75 static inline void default_inquire_remote_apic(int apicid) 76 { 77 if (apic_verbosity >= APIC_DEBUG) 78 __inquire_remote_apic(apicid); 79 } 80 81 /* 82 * With 82489DX we can't rely on apic feature bit 83 * retrieved via cpuid but still have to deal with 84 * such an apic chip so we assume that SMP configuration 85 * is found from MP table (64bit case uses ACPI mostly 86 * which set smp presence flag as well so we are safe 87 * to use this helper too). 88 */ 89 static inline bool apic_from_smp_config(void) 90 { 91 return smp_found_config && !disable_apic; 92 } 93 94 /* 95 * Basic functions accessing APICs. 96 */ 97 #ifdef CONFIG_PARAVIRT 98 #include <asm/paravirt.h> 99 #endif 100 101 extern int setup_profiling_timer(unsigned int); 102 103 static inline void native_apic_mem_write(u32 reg, u32 v) 104 { 105 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 106 107 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 108 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 109 ASM_OUTPUT2("0" (v), "m" (*addr))); 110 } 111 112 static inline u32 native_apic_mem_read(u32 reg) 113 { 114 return *((volatile u32 *)(APIC_BASE + reg)); 115 } 116 117 extern void native_apic_wait_icr_idle(void); 118 extern u32 native_safe_apic_wait_icr_idle(void); 119 extern void native_apic_icr_write(u32 low, u32 id); 120 extern u64 native_apic_icr_read(void); 121 122 static inline bool apic_is_x2apic_enabled(void) 123 { 124 u64 msr; 125 126 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 127 return false; 128 return msr & X2APIC_ENABLE; 129 } 130 131 extern void enable_IR_x2apic(void); 132 133 extern int get_physical_broadcast(void); 134 135 extern int lapic_get_maxlvt(void); 136 extern void clear_local_APIC(void); 137 extern void disconnect_bsp_APIC(int virt_wire_setup); 138 extern void disable_local_APIC(void); 139 extern void apic_soft_disable(void); 140 extern void lapic_shutdown(void); 141 extern void sync_Arb_IDs(void); 142 extern void init_bsp_APIC(void); 143 extern void apic_intr_mode_init(void); 144 extern void init_apic_mappings(void); 145 void register_lapic_address(unsigned long address); 146 extern void setup_boot_APIC_clock(void); 147 extern void setup_secondary_APIC_clock(void); 148 extern void lapic_update_tsc_freq(void); 149 150 #ifdef CONFIG_X86_64 151 static inline int apic_force_enable(unsigned long addr) 152 { 153 return -1; 154 } 155 #else 156 extern int apic_force_enable(unsigned long addr); 157 #endif 158 159 extern void apic_ap_setup(void); 160 161 /* 162 * On 32bit this is mach-xxx local 163 */ 164 #ifdef CONFIG_X86_64 165 extern int apic_is_clustered_box(void); 166 #else 167 static inline int apic_is_clustered_box(void) 168 { 169 return 0; 170 } 171 #endif 172 173 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 174 extern void lapic_assign_system_vectors(void); 175 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 176 extern void lapic_online(void); 177 extern void lapic_offline(void); 178 extern bool apic_needs_pit(void); 179 180 #else /* !CONFIG_X86_LOCAL_APIC */ 181 static inline void lapic_shutdown(void) { } 182 #define local_apic_timer_c2_ok 1 183 static inline void init_apic_mappings(void) { } 184 static inline void disable_local_APIC(void) { } 185 # define setup_boot_APIC_clock x86_init_noop 186 # define setup_secondary_APIC_clock x86_init_noop 187 static inline void lapic_update_tsc_freq(void) { } 188 static inline void init_bsp_APIC(void) { } 189 static inline void apic_intr_mode_init(void) { } 190 static inline void lapic_assign_system_vectors(void) { } 191 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 192 static inline bool apic_needs_pit(void) { return true; } 193 #endif /* !CONFIG_X86_LOCAL_APIC */ 194 195 #ifdef CONFIG_X86_X2APIC 196 /* 197 * Make previous memory operations globally visible before 198 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 199 * mfence for this. 200 */ 201 static inline void x2apic_wrmsr_fence(void) 202 { 203 asm volatile("mfence" : : : "memory"); 204 } 205 206 static inline void native_apic_msr_write(u32 reg, u32 v) 207 { 208 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 209 reg == APIC_LVR) 210 return; 211 212 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 213 } 214 215 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 216 { 217 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 218 } 219 220 static inline u32 native_apic_msr_read(u32 reg) 221 { 222 u64 msr; 223 224 if (reg == APIC_DFR) 225 return -1; 226 227 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 228 return (u32)msr; 229 } 230 231 static inline void native_x2apic_wait_icr_idle(void) 232 { 233 /* no need to wait for icr idle in x2apic */ 234 return; 235 } 236 237 static inline u32 native_safe_x2apic_wait_icr_idle(void) 238 { 239 /* no need to wait for icr idle in x2apic */ 240 return 0; 241 } 242 243 static inline void native_x2apic_icr_write(u32 low, u32 id) 244 { 245 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 246 } 247 248 static inline u64 native_x2apic_icr_read(void) 249 { 250 unsigned long val; 251 252 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 253 return val; 254 } 255 256 extern int x2apic_mode; 257 extern int x2apic_phys; 258 extern void __init check_x2apic(void); 259 extern void x2apic_setup(void); 260 static inline int x2apic_enabled(void) 261 { 262 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 263 } 264 265 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 266 #else /* !CONFIG_X86_X2APIC */ 267 static inline void check_x2apic(void) { } 268 static inline void x2apic_setup(void) { } 269 static inline int x2apic_enabled(void) { return 0; } 270 271 #define x2apic_mode (0) 272 #define x2apic_supported() (0) 273 #endif /* !CONFIG_X86_X2APIC */ 274 275 struct irq_data; 276 277 /* 278 * Copyright 2004 James Cleverdon, IBM. 279 * 280 * Generic APIC sub-arch data struct. 281 * 282 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 283 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 284 * James Cleverdon. 285 */ 286 struct apic { 287 /* Hotpath functions first */ 288 void (*eoi_write)(u32 reg, u32 v); 289 void (*native_eoi_write)(u32 reg, u32 v); 290 void (*write)(u32 reg, u32 v); 291 u32 (*read)(u32 reg); 292 293 /* IPI related functions */ 294 void (*wait_icr_idle)(void); 295 u32 (*safe_wait_icr_idle)(void); 296 297 void (*send_IPI)(int cpu, int vector); 298 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 299 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 300 void (*send_IPI_allbutself)(int vector); 301 void (*send_IPI_all)(int vector); 302 void (*send_IPI_self)(int vector); 303 304 /* dest_logical is used by the IPI functions */ 305 u32 dest_logical; 306 u32 disable_esr; 307 u32 irq_delivery_mode; 308 u32 irq_dest_mode; 309 310 u32 (*calc_dest_apicid)(unsigned int cpu); 311 312 /* ICR related functions */ 313 u64 (*icr_read)(void); 314 void (*icr_write)(u32 low, u32 high); 315 316 /* Probe, setup and smpboot functions */ 317 int (*probe)(void); 318 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 319 int (*apic_id_valid)(u32 apicid); 320 int (*apic_id_registered)(void); 321 322 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 323 void (*init_apic_ldr)(void); 324 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 325 void (*setup_apic_routing)(void); 326 int (*cpu_present_to_apicid)(int mps_cpu); 327 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 328 int (*check_phys_apicid_present)(int phys_apicid); 329 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 330 331 u32 (*get_apic_id)(unsigned long x); 332 u32 (*set_apic_id)(unsigned int id); 333 334 /* wakeup_secondary_cpu */ 335 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 336 337 void (*inquire_remote_apic)(int apicid); 338 339 #ifdef CONFIG_X86_32 340 /* 341 * Called very early during boot from get_smp_config(). It should 342 * return the logical apicid. x86_[bios]_cpu_to_apicid is 343 * initialized before this function is called. 344 * 345 * If logical apicid can't be determined that early, the function 346 * may return BAD_APICID. Logical apicid will be configured after 347 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 348 * won't be applied properly during early boot in this case. 349 */ 350 int (*x86_32_early_logical_apicid)(int cpu); 351 #endif 352 char *name; 353 }; 354 355 /* 356 * Pointer to the local APIC driver in use on this system (there's 357 * always just one such driver in use - the kernel decides via an 358 * early probing process which one it picks - and then sticks to it): 359 */ 360 extern struct apic *apic; 361 362 /* 363 * APIC drivers are probed based on how they are listed in the .apicdrivers 364 * section. So the order is important and enforced by the ordering 365 * of different apic driver files in the Makefile. 366 * 367 * For the files having two apic drivers, we use apic_drivers() 368 * to enforce the order with in them. 369 */ 370 #define apic_driver(sym) \ 371 static const struct apic *__apicdrivers_##sym __used \ 372 __aligned(sizeof(struct apic *)) \ 373 __section(.apicdrivers) = { &sym } 374 375 #define apic_drivers(sym1, sym2) \ 376 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 377 __aligned(sizeof(struct apic *)) \ 378 __section(.apicdrivers) = { &sym1, &sym2 } 379 380 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 381 382 /* 383 * APIC functionality to boot other CPUs - only used on SMP: 384 */ 385 #ifdef CONFIG_SMP 386 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 387 extern int lapic_can_unplug_cpu(void); 388 #endif 389 390 #ifdef CONFIG_X86_LOCAL_APIC 391 392 static inline u32 apic_read(u32 reg) 393 { 394 return apic->read(reg); 395 } 396 397 static inline void apic_write(u32 reg, u32 val) 398 { 399 apic->write(reg, val); 400 } 401 402 static inline void apic_eoi(void) 403 { 404 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 405 } 406 407 static inline u64 apic_icr_read(void) 408 { 409 return apic->icr_read(); 410 } 411 412 static inline void apic_icr_write(u32 low, u32 high) 413 { 414 apic->icr_write(low, high); 415 } 416 417 static inline void apic_wait_icr_idle(void) 418 { 419 apic->wait_icr_idle(); 420 } 421 422 static inline u32 safe_apic_wait_icr_idle(void) 423 { 424 return apic->safe_wait_icr_idle(); 425 } 426 427 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 428 429 #else /* CONFIG_X86_LOCAL_APIC */ 430 431 static inline u32 apic_read(u32 reg) { return 0; } 432 static inline void apic_write(u32 reg, u32 val) { } 433 static inline void apic_eoi(void) { } 434 static inline u64 apic_icr_read(void) { return 0; } 435 static inline void apic_icr_write(u32 low, u32 high) { } 436 static inline void apic_wait_icr_idle(void) { } 437 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 438 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 439 440 #endif /* CONFIG_X86_LOCAL_APIC */ 441 442 extern void apic_ack_irq(struct irq_data *data); 443 444 static inline void ack_APIC_irq(void) 445 { 446 /* 447 * ack_APIC_irq() actually gets compiled as a single instruction 448 * ... yummie. 449 */ 450 apic_eoi(); 451 } 452 453 static inline unsigned default_get_apic_id(unsigned long x) 454 { 455 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 456 457 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 458 return (x >> 24) & 0xFF; 459 else 460 return (x >> 24) & 0x0F; 461 } 462 463 /* 464 * Warm reset vector position: 465 */ 466 #define TRAMPOLINE_PHYS_LOW 0x467 467 #define TRAMPOLINE_PHYS_HIGH 0x469 468 469 #ifdef CONFIG_X86_64 470 extern void apic_send_IPI_self(int vector); 471 #endif 472 473 extern void generic_bigsmp_probe(void); 474 475 #ifdef CONFIG_X86_LOCAL_APIC 476 477 #include <asm/smp.h> 478 479 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 480 481 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 482 483 extern struct apic apic_noop; 484 485 static inline unsigned int read_apic_id(void) 486 { 487 unsigned int reg = apic_read(APIC_ID); 488 489 return apic->get_apic_id(reg); 490 } 491 492 extern int default_apic_id_valid(u32 apicid); 493 extern int default_acpi_madt_oem_check(char *, char *); 494 extern void default_setup_apic_routing(void); 495 496 extern u32 apic_default_calc_apicid(unsigned int cpu); 497 extern u32 apic_flat_calc_apicid(unsigned int cpu); 498 499 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 500 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 501 extern int default_cpu_present_to_apicid(int mps_cpu); 502 extern int default_check_phys_apicid_present(int phys_apicid); 503 504 #endif /* CONFIG_X86_LOCAL_APIC */ 505 506 #ifdef CONFIG_SMP 507 bool apic_id_is_primary_thread(unsigned int id); 508 void apic_smt_update(void); 509 #else 510 static inline bool apic_id_is_primary_thread(unsigned int id) { return false; } 511 static inline void apic_smt_update(void) { } 512 #endif 513 514 extern void irq_enter(void); 515 extern void irq_exit(void); 516 517 static inline void entering_irq(void) 518 { 519 irq_enter(); 520 kvm_set_cpu_l1tf_flush_l1d(); 521 } 522 523 static inline void entering_ack_irq(void) 524 { 525 entering_irq(); 526 ack_APIC_irq(); 527 } 528 529 static inline void ipi_entering_ack_irq(void) 530 { 531 irq_enter(); 532 ack_APIC_irq(); 533 kvm_set_cpu_l1tf_flush_l1d(); 534 } 535 536 static inline void exiting_irq(void) 537 { 538 irq_exit(); 539 } 540 541 static inline void exiting_ack_irq(void) 542 { 543 ack_APIC_irq(); 544 irq_exit(); 545 } 546 547 extern void ioapic_zap_locks(void); 548 549 #endif /* _ASM_X86_APIC_H */ 550