1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/delay.h> 6 #include <linux/pm.h> 7 8 #include <asm/alternative.h> 9 #include <asm/cpufeature.h> 10 #include <asm/processor.h> 11 #include <asm/apicdef.h> 12 #include <asm/atomic.h> 13 #include <asm/fixmap.h> 14 #include <asm/mpspec.h> 15 #include <asm/system.h> 16 #include <asm/msr.h> 17 18 #define ARCH_APICTIMER_STOPS_ON_C3 1 19 20 /* 21 * Debugging macros 22 */ 23 #define APIC_QUIET 0 24 #define APIC_VERBOSE 1 25 #define APIC_DEBUG 2 26 27 /* 28 * Define the default level of output to be very little 29 * This can be turned up by using apic=verbose for more 30 * information and apic=debug for _lots_ of information. 31 * apic_verbosity is defined in apic.c 32 */ 33 #define apic_printk(v, s, a...) do { \ 34 if ((v) <= apic_verbosity) \ 35 printk(s, ##a); \ 36 } while (0) 37 38 39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 40 extern void generic_apic_probe(void); 41 #else 42 static inline void generic_apic_probe(void) 43 { 44 } 45 #endif 46 47 #ifdef CONFIG_X86_LOCAL_APIC 48 49 extern unsigned int apic_verbosity; 50 extern int local_apic_timer_c2_ok; 51 52 extern int disable_apic; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * Basic functions accessing APICs. 70 */ 71 #ifdef CONFIG_PARAVIRT 72 #include <asm/paravirt.h> 73 #else 74 #define setup_boot_clock setup_boot_APIC_clock 75 #define setup_secondary_clock setup_secondary_APIC_clock 76 #endif 77 78 #ifdef CONFIG_X86_64 79 extern int is_vsmp_box(void); 80 #else 81 static inline int is_vsmp_box(void) 82 { 83 return 0; 84 } 85 #endif 86 extern void xapic_wait_icr_idle(void); 87 extern u32 safe_xapic_wait_icr_idle(void); 88 extern void xapic_icr_write(u32, u32); 89 extern int setup_profiling_timer(unsigned int); 90 91 static inline void native_apic_mem_write(u32 reg, u32 v) 92 { 93 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 94 95 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 96 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 97 ASM_OUTPUT2("0" (v), "m" (*addr))); 98 } 99 100 static inline u32 native_apic_mem_read(u32 reg) 101 { 102 return *((volatile u32 *)(APIC_BASE + reg)); 103 } 104 105 extern void native_apic_wait_icr_idle(void); 106 extern u32 native_safe_apic_wait_icr_idle(void); 107 extern void native_apic_icr_write(u32 low, u32 id); 108 extern u64 native_apic_icr_read(void); 109 110 #define EIM_8BIT_APIC_ID 0 111 #define EIM_32BIT_APIC_ID 1 112 113 #ifdef CONFIG_X86_X2APIC 114 /* 115 * Make previous memory operations globally visible before 116 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 117 * mfence for this. 118 */ 119 static inline void x2apic_wrmsr_fence(void) 120 { 121 asm volatile("mfence" : : : "memory"); 122 } 123 124 static inline void native_apic_msr_write(u32 reg, u32 v) 125 { 126 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 127 reg == APIC_LVR) 128 return; 129 130 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 131 } 132 133 static inline u32 native_apic_msr_read(u32 reg) 134 { 135 u32 low, high; 136 137 if (reg == APIC_DFR) 138 return -1; 139 140 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); 141 return low; 142 } 143 144 static inline void native_x2apic_wait_icr_idle(void) 145 { 146 /* no need to wait for icr idle in x2apic */ 147 return; 148 } 149 150 static inline u32 native_safe_x2apic_wait_icr_idle(void) 151 { 152 /* no need to wait for icr idle in x2apic */ 153 return 0; 154 } 155 156 static inline void native_x2apic_icr_write(u32 low, u32 id) 157 { 158 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 159 } 160 161 static inline u64 native_x2apic_icr_read(void) 162 { 163 unsigned long val; 164 165 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 166 return val; 167 } 168 169 extern int x2apic, x2apic_phys; 170 extern void check_x2apic(void); 171 extern void enable_x2apic(void); 172 extern void enable_IR_x2apic(void); 173 extern void x2apic_icr_write(u32 low, u32 id); 174 static inline int x2apic_enabled(void) 175 { 176 int msr, msr2; 177 178 if (!cpu_has_x2apic) 179 return 0; 180 181 rdmsr(MSR_IA32_APICBASE, msr, msr2); 182 if (msr & X2APIC_ENABLE) 183 return 1; 184 return 0; 185 } 186 #else 187 static inline void check_x2apic(void) 188 { 189 } 190 static inline void enable_x2apic(void) 191 { 192 } 193 static inline void enable_IR_x2apic(void) 194 { 195 } 196 static inline int x2apic_enabled(void) 197 { 198 return 0; 199 } 200 201 #define x2apic 0 202 203 #endif 204 205 extern int get_physical_broadcast(void); 206 207 extern void apic_disable(void); 208 extern int lapic_get_maxlvt(void); 209 extern void clear_local_APIC(void); 210 extern void connect_bsp_APIC(void); 211 extern void disconnect_bsp_APIC(int virt_wire_setup); 212 extern void disable_local_APIC(void); 213 extern void lapic_shutdown(void); 214 extern int verify_local_APIC(void); 215 extern void cache_APIC_registers(void); 216 extern void sync_Arb_IDs(void); 217 extern void init_bsp_APIC(void); 218 extern void setup_local_APIC(void); 219 extern void end_local_APIC_setup(void); 220 extern void init_apic_mappings(void); 221 extern void setup_boot_APIC_clock(void); 222 extern void setup_secondary_APIC_clock(void); 223 extern int APIC_init_uniprocessor(void); 224 extern void enable_NMI_through_LVT0(void); 225 226 /* 227 * On 32bit this is mach-xxx local 228 */ 229 #ifdef CONFIG_X86_64 230 extern void early_init_lapic_mapping(void); 231 extern int apic_is_clustered_box(void); 232 #else 233 static inline int apic_is_clustered_box(void) 234 { 235 return 0; 236 } 237 #endif 238 239 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 240 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 241 242 243 #else /* !CONFIG_X86_LOCAL_APIC */ 244 static inline void lapic_shutdown(void) { } 245 #define local_apic_timer_c2_ok 1 246 static inline void init_apic_mappings(void) { } 247 static inline void disable_local_APIC(void) { } 248 static inline void apic_disable(void) { } 249 #endif /* !CONFIG_X86_LOCAL_APIC */ 250 251 #ifdef CONFIG_X86_64 252 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 253 #else 254 255 #endif 256 257 /* 258 * Copyright 2004 James Cleverdon, IBM. 259 * Subject to the GNU Public License, v.2 260 * 261 * Generic APIC sub-arch data struct. 262 * 263 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 264 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 265 * James Cleverdon. 266 */ 267 struct apic { 268 char *name; 269 270 int (*probe)(void); 271 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 272 int (*apic_id_registered)(void); 273 274 u32 irq_delivery_mode; 275 u32 irq_dest_mode; 276 277 const struct cpumask *(*target_cpus)(void); 278 279 int disable_esr; 280 281 int dest_logical; 282 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid); 283 unsigned long (*check_apicid_present)(int apicid); 284 285 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 286 void (*init_apic_ldr)(void); 287 288 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map); 289 290 void (*setup_apic_routing)(void); 291 int (*multi_timer_check)(int apic, int irq); 292 int (*apicid_to_node)(int logical_apicid); 293 int (*cpu_to_logical_apicid)(int cpu); 294 int (*cpu_present_to_apicid)(int mps_cpu); 295 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid); 296 void (*setup_portio_remap)(void); 297 int (*check_phys_apicid_present)(int boot_cpu_physical_apicid); 298 void (*enable_apic_mode)(void); 299 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 300 301 /* 302 * When one of the next two hooks returns 1 the apic 303 * is switched to this. Essentially they are additional 304 * probe functions: 305 */ 306 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 307 308 unsigned int (*get_apic_id)(unsigned long x); 309 unsigned long (*set_apic_id)(unsigned int id); 310 unsigned long apic_id_mask; 311 312 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 313 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 314 const struct cpumask *andmask); 315 316 /* ipi */ 317 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 318 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 319 int vector); 320 void (*send_IPI_allbutself)(int vector); 321 void (*send_IPI_all)(int vector); 322 void (*send_IPI_self)(int vector); 323 324 /* wakeup_secondary_cpu */ 325 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 326 327 int trampoline_phys_low; 328 int trampoline_phys_high; 329 330 void (*wait_for_init_deassert)(atomic_t *deassert); 331 void (*smp_callin_clear_local_apic)(void); 332 void (*inquire_remote_apic)(int apicid); 333 334 /* apic ops */ 335 u32 (*read)(u32 reg); 336 void (*write)(u32 reg, u32 v); 337 u64 (*icr_read)(void); 338 void (*icr_write)(u32 low, u32 high); 339 void (*wait_icr_idle)(void); 340 u32 (*safe_wait_icr_idle)(void); 341 }; 342 343 /* 344 * Pointer to the local APIC driver in use on this system (there's 345 * always just one such driver in use - the kernel decides via an 346 * early probing process which one it picks - and then sticks to it): 347 */ 348 extern struct apic *apic; 349 350 /* 351 * APIC functionality to boot other CPUs - only used on SMP: 352 */ 353 #ifdef CONFIG_SMP 354 extern atomic_t init_deasserted; 355 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 356 #endif 357 358 static inline u32 apic_read(u32 reg) 359 { 360 return apic->read(reg); 361 } 362 363 static inline void apic_write(u32 reg, u32 val) 364 { 365 apic->write(reg, val); 366 } 367 368 static inline u64 apic_icr_read(void) 369 { 370 return apic->icr_read(); 371 } 372 373 static inline void apic_icr_write(u32 low, u32 high) 374 { 375 apic->icr_write(low, high); 376 } 377 378 static inline void apic_wait_icr_idle(void) 379 { 380 apic->wait_icr_idle(); 381 } 382 383 static inline u32 safe_apic_wait_icr_idle(void) 384 { 385 return apic->safe_wait_icr_idle(); 386 } 387 388 389 static inline void ack_APIC_irq(void) 390 { 391 #ifdef CONFIG_X86_LOCAL_APIC 392 /* 393 * ack_APIC_irq() actually gets compiled as a single instruction 394 * ... yummie. 395 */ 396 397 /* Docs say use 0 for future compatibility */ 398 apic_write(APIC_EOI, 0); 399 #endif 400 } 401 402 static inline unsigned default_get_apic_id(unsigned long x) 403 { 404 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 405 406 if (APIC_XAPIC(ver)) 407 return (x >> 24) & 0xFF; 408 else 409 return (x >> 24) & 0x0F; 410 } 411 412 /* 413 * Warm reset vector default position: 414 */ 415 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 416 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 417 418 #ifdef CONFIG_X86_64 419 extern struct apic apic_flat; 420 extern struct apic apic_physflat; 421 extern struct apic apic_x2apic_cluster; 422 extern struct apic apic_x2apic_phys; 423 extern int default_acpi_madt_oem_check(char *, char *); 424 425 extern void apic_send_IPI_self(int vector); 426 427 extern struct apic apic_x2apic_uv_x; 428 DECLARE_PER_CPU(int, x2apic_extra_bits); 429 430 extern int default_cpu_present_to_apicid(int mps_cpu); 431 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); 432 #endif 433 434 static inline void default_wait_for_init_deassert(atomic_t *deassert) 435 { 436 while (!atomic_read(deassert)) 437 cpu_relax(); 438 return; 439 } 440 441 extern void generic_bigsmp_probe(void); 442 443 444 #ifdef CONFIG_X86_LOCAL_APIC 445 446 #include <asm/smp.h> 447 448 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 449 450 static inline const struct cpumask *default_target_cpus(void) 451 { 452 #ifdef CONFIG_SMP 453 return cpu_online_mask; 454 #else 455 return cpumask_of(0); 456 #endif 457 } 458 459 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 460 461 462 static inline unsigned int read_apic_id(void) 463 { 464 unsigned int reg; 465 466 reg = apic_read(APIC_ID); 467 468 return apic->get_apic_id(reg); 469 } 470 471 extern void default_setup_apic_routing(void); 472 473 #ifdef CONFIG_X86_32 474 /* 475 * Set up the logical destination ID. 476 * 477 * Intel recommends to set DFR, LDR and TPR before enabling 478 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 479 * document number 292116). So here it goes... 480 */ 481 extern void default_init_apic_ldr(void); 482 483 static inline int default_apic_id_registered(void) 484 { 485 return physid_isset(read_apic_id(), phys_cpu_present_map); 486 } 487 488 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 489 { 490 return cpuid_apic >> index_msb; 491 } 492 493 extern int default_apicid_to_node(int logical_apicid); 494 495 #endif 496 497 static inline unsigned int 498 default_cpu_mask_to_apicid(const struct cpumask *cpumask) 499 { 500 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 501 } 502 503 static inline unsigned int 504 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 505 const struct cpumask *andmask) 506 { 507 unsigned long mask1 = cpumask_bits(cpumask)[0]; 508 unsigned long mask2 = cpumask_bits(andmask)[0]; 509 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 510 511 return (unsigned int)(mask1 & mask2 & mask3); 512 } 513 514 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) 515 { 516 return physid_isset(apicid, bitmap); 517 } 518 519 static inline unsigned long default_check_apicid_present(int bit) 520 { 521 return physid_isset(bit, phys_cpu_present_map); 522 } 523 524 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) 525 { 526 return phys_map; 527 } 528 529 /* Mapping from cpu number to logical apicid */ 530 static inline int default_cpu_to_logical_apicid(int cpu) 531 { 532 return 1 << cpu; 533 } 534 535 static inline int __default_cpu_present_to_apicid(int mps_cpu) 536 { 537 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 538 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 539 else 540 return BAD_APICID; 541 } 542 543 static inline int 544 __default_check_phys_apicid_present(int boot_cpu_physical_apicid) 545 { 546 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); 547 } 548 549 #ifdef CONFIG_X86_32 550 static inline int default_cpu_present_to_apicid(int mps_cpu) 551 { 552 return __default_cpu_present_to_apicid(mps_cpu); 553 } 554 555 static inline int 556 default_check_phys_apicid_present(int boot_cpu_physical_apicid) 557 { 558 return __default_check_phys_apicid_present(boot_cpu_physical_apicid); 559 } 560 #else 561 extern int default_cpu_present_to_apicid(int mps_cpu); 562 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); 563 #endif 564 565 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) 566 { 567 return physid_mask_of_physid(phys_apicid); 568 } 569 570 #endif /* CONFIG_X86_LOCAL_APIC */ 571 572 #ifdef CONFIG_X86_32 573 extern u8 cpu_2_logical_apicid[NR_CPUS]; 574 #endif 575 576 #endif /* _ASM_X86_APIC_H */ 577