1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/idle.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* 27 * Define the default level of output to be very little 28 * This can be turned up by using apic=verbose for more 29 * information and apic=debug for _lots_ of information. 30 * apic_verbosity is defined in apic.c 31 */ 32 #define apic_printk(v, s, a...) do { \ 33 if ((v) <= apic_verbosity) \ 34 printk(s, ##a); \ 35 } while (0) 36 37 38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39 extern void generic_apic_probe(void); 40 #else 41 static inline void generic_apic_probe(void) 42 { 43 } 44 #endif 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 48 extern unsigned int apic_verbosity; 49 extern int local_apic_timer_c2_ok; 50 51 extern int disable_apic; 52 extern unsigned int lapic_timer_frequency; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 extern int setup_profiling_timer(unsigned int); 89 90 static inline void native_apic_mem_write(u32 reg, u32 v) 91 { 92 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 93 94 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, 95 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 96 ASM_OUTPUT2("0" (v), "m" (*addr))); 97 } 98 99 static inline u32 native_apic_mem_read(u32 reg) 100 { 101 return *((volatile u32 *)(APIC_BASE + reg)); 102 } 103 104 extern void native_apic_wait_icr_idle(void); 105 extern u32 native_safe_apic_wait_icr_idle(void); 106 extern void native_apic_icr_write(u32 low, u32 id); 107 extern u64 native_apic_icr_read(void); 108 109 static inline bool apic_is_x2apic_enabled(void) 110 { 111 u64 msr; 112 113 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 114 return false; 115 return msr & X2APIC_ENABLE; 116 } 117 118 #ifdef CONFIG_X86_X2APIC 119 /* 120 * Make previous memory operations globally visible before 121 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 122 * mfence for this. 123 */ 124 static inline void x2apic_wrmsr_fence(void) 125 { 126 asm volatile("mfence" : : : "memory"); 127 } 128 129 static inline void native_apic_msr_write(u32 reg, u32 v) 130 { 131 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 132 reg == APIC_LVR) 133 return; 134 135 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 136 } 137 138 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 139 { 140 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 141 } 142 143 static inline u32 native_apic_msr_read(u32 reg) 144 { 145 u64 msr; 146 147 if (reg == APIC_DFR) 148 return -1; 149 150 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 151 return (u32)msr; 152 } 153 154 static inline void native_x2apic_wait_icr_idle(void) 155 { 156 /* no need to wait for icr idle in x2apic */ 157 return; 158 } 159 160 static inline u32 native_safe_x2apic_wait_icr_idle(void) 161 { 162 /* no need to wait for icr idle in x2apic */ 163 return 0; 164 } 165 166 static inline void native_x2apic_icr_write(u32 low, u32 id) 167 { 168 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 169 } 170 171 static inline u64 native_x2apic_icr_read(void) 172 { 173 unsigned long val; 174 175 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 176 return val; 177 } 178 179 extern int x2apic_mode; 180 extern int x2apic_phys; 181 extern void __init check_x2apic(void); 182 extern void enable_x2apic(void); 183 static inline int x2apic_enabled(void) 184 { 185 return cpu_has_x2apic && apic_is_x2apic_enabled(); 186 } 187 188 #define x2apic_supported() (cpu_has_x2apic) 189 #else 190 static inline void disable_x2apic(void) { } 191 static inline void check_x2apic(void) { } 192 static inline void enable_x2apic(void) { } 193 static inline int x2apic_enabled(void) { return 0; } 194 195 #define x2apic_mode (0) 196 #define x2apic_supported() (0) 197 #endif 198 199 extern void enable_IR_x2apic(void); 200 201 extern int get_physical_broadcast(void); 202 203 extern int lapic_get_maxlvt(void); 204 extern void clear_local_APIC(void); 205 extern void connect_bsp_APIC(void); 206 extern void disconnect_bsp_APIC(int virt_wire_setup); 207 extern void disable_local_APIC(void); 208 extern void lapic_shutdown(void); 209 extern int verify_local_APIC(void); 210 extern void sync_Arb_IDs(void); 211 extern void init_bsp_APIC(void); 212 extern void setup_local_APIC(void); 213 extern void end_local_APIC_setup(void); 214 extern void bsp_end_local_APIC_setup(void); 215 extern void init_apic_mappings(void); 216 void register_lapic_address(unsigned long address); 217 extern void setup_boot_APIC_clock(void); 218 extern void setup_secondary_APIC_clock(void); 219 extern int APIC_init_uniprocessor(void); 220 extern int apic_force_enable(unsigned long addr); 221 222 /* 223 * On 32bit this is mach-xxx local 224 */ 225 #ifdef CONFIG_X86_64 226 extern int apic_is_clustered_box(void); 227 #else 228 static inline int apic_is_clustered_box(void) 229 { 230 return 0; 231 } 232 #endif 233 234 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 235 236 #else /* !CONFIG_X86_LOCAL_APIC */ 237 static inline void lapic_shutdown(void) { } 238 #define local_apic_timer_c2_ok 1 239 static inline void init_apic_mappings(void) { } 240 static inline void disable_local_APIC(void) { } 241 # define setup_boot_APIC_clock x86_init_noop 242 # define setup_secondary_APIC_clock x86_init_noop 243 #endif /* !CONFIG_X86_LOCAL_APIC */ 244 245 #ifdef CONFIG_X86_64 246 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 247 #else 248 249 #endif 250 251 /* 252 * Copyright 2004 James Cleverdon, IBM. 253 * Subject to the GNU Public License, v.2 254 * 255 * Generic APIC sub-arch data struct. 256 * 257 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 258 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 259 * James Cleverdon. 260 */ 261 struct apic { 262 char *name; 263 264 int (*probe)(void); 265 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 266 int (*apic_id_valid)(int apicid); 267 int (*apic_id_registered)(void); 268 269 u32 irq_delivery_mode; 270 u32 irq_dest_mode; 271 272 const struct cpumask *(*target_cpus)(void); 273 274 int disable_esr; 275 276 int dest_logical; 277 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 278 279 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 280 const struct cpumask *mask); 281 void (*init_apic_ldr)(void); 282 283 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 284 285 void (*setup_apic_routing)(void); 286 int (*cpu_present_to_apicid)(int mps_cpu); 287 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 288 int (*check_phys_apicid_present)(int phys_apicid); 289 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 290 291 unsigned int (*get_apic_id)(unsigned long x); 292 unsigned long (*set_apic_id)(unsigned int id); 293 unsigned long apic_id_mask; 294 295 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 296 const struct cpumask *andmask, 297 unsigned int *apicid); 298 299 /* ipi */ 300 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 301 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 302 int vector); 303 void (*send_IPI_allbutself)(int vector); 304 void (*send_IPI_all)(int vector); 305 void (*send_IPI_self)(int vector); 306 307 /* wakeup_secondary_cpu */ 308 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 309 310 bool wait_for_init_deassert; 311 void (*inquire_remote_apic)(int apicid); 312 313 /* apic ops */ 314 u32 (*read)(u32 reg); 315 void (*write)(u32 reg, u32 v); 316 /* 317 * ->eoi_write() has the same signature as ->write(). 318 * 319 * Drivers can support both ->eoi_write() and ->write() by passing the same 320 * callback value. Kernel can override ->eoi_write() and fall back 321 * on write for EOI. 322 */ 323 void (*eoi_write)(u32 reg, u32 v); 324 u64 (*icr_read)(void); 325 void (*icr_write)(u32 low, u32 high); 326 void (*wait_icr_idle)(void); 327 u32 (*safe_wait_icr_idle)(void); 328 329 #ifdef CONFIG_X86_32 330 /* 331 * Called very early during boot from get_smp_config(). It should 332 * return the logical apicid. x86_[bios]_cpu_to_apicid is 333 * initialized before this function is called. 334 * 335 * If logical apicid can't be determined that early, the function 336 * may return BAD_APICID. Logical apicid will be configured after 337 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 338 * won't be applied properly during early boot in this case. 339 */ 340 int (*x86_32_early_logical_apicid)(int cpu); 341 #endif 342 }; 343 344 /* 345 * Pointer to the local APIC driver in use on this system (there's 346 * always just one such driver in use - the kernel decides via an 347 * early probing process which one it picks - and then sticks to it): 348 */ 349 extern struct apic *apic; 350 351 /* 352 * APIC drivers are probed based on how they are listed in the .apicdrivers 353 * section. So the order is important and enforced by the ordering 354 * of different apic driver files in the Makefile. 355 * 356 * For the files having two apic drivers, we use apic_drivers() 357 * to enforce the order with in them. 358 */ 359 #define apic_driver(sym) \ 360 static const struct apic *__apicdrivers_##sym __used \ 361 __aligned(sizeof(struct apic *)) \ 362 __section(.apicdrivers) = { &sym } 363 364 #define apic_drivers(sym1, sym2) \ 365 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 366 __aligned(sizeof(struct apic *)) \ 367 __section(.apicdrivers) = { &sym1, &sym2 } 368 369 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 370 371 /* 372 * APIC functionality to boot other CPUs - only used on SMP: 373 */ 374 #ifdef CONFIG_SMP 375 extern atomic_t init_deasserted; 376 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 377 #endif 378 379 #ifdef CONFIG_X86_LOCAL_APIC 380 381 static inline u32 apic_read(u32 reg) 382 { 383 return apic->read(reg); 384 } 385 386 static inline void apic_write(u32 reg, u32 val) 387 { 388 apic->write(reg, val); 389 } 390 391 static inline void apic_eoi(void) 392 { 393 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 394 } 395 396 static inline u64 apic_icr_read(void) 397 { 398 return apic->icr_read(); 399 } 400 401 static inline void apic_icr_write(u32 low, u32 high) 402 { 403 apic->icr_write(low, high); 404 } 405 406 static inline void apic_wait_icr_idle(void) 407 { 408 apic->wait_icr_idle(); 409 } 410 411 static inline u32 safe_apic_wait_icr_idle(void) 412 { 413 return apic->safe_wait_icr_idle(); 414 } 415 416 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 417 418 #else /* CONFIG_X86_LOCAL_APIC */ 419 420 static inline u32 apic_read(u32 reg) { return 0; } 421 static inline void apic_write(u32 reg, u32 val) { } 422 static inline void apic_eoi(void) { } 423 static inline u64 apic_icr_read(void) { return 0; } 424 static inline void apic_icr_write(u32 low, u32 high) { } 425 static inline void apic_wait_icr_idle(void) { } 426 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 427 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 428 429 #endif /* CONFIG_X86_LOCAL_APIC */ 430 431 static inline void ack_APIC_irq(void) 432 { 433 /* 434 * ack_APIC_irq() actually gets compiled as a single instruction 435 * ... yummie. 436 */ 437 apic_eoi(); 438 } 439 440 static inline unsigned default_get_apic_id(unsigned long x) 441 { 442 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 443 444 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 445 return (x >> 24) & 0xFF; 446 else 447 return (x >> 24) & 0x0F; 448 } 449 450 /* 451 * Warm reset vector position: 452 */ 453 #define TRAMPOLINE_PHYS_LOW 0x467 454 #define TRAMPOLINE_PHYS_HIGH 0x469 455 456 #ifdef CONFIG_X86_64 457 extern void apic_send_IPI_self(int vector); 458 459 DECLARE_PER_CPU(int, x2apic_extra_bits); 460 461 extern int default_cpu_present_to_apicid(int mps_cpu); 462 extern int default_check_phys_apicid_present(int phys_apicid); 463 #endif 464 465 extern void generic_bigsmp_probe(void); 466 467 468 #ifdef CONFIG_X86_LOCAL_APIC 469 470 #include <asm/smp.h> 471 472 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 473 474 static inline const struct cpumask *default_target_cpus(void) 475 { 476 #ifdef CONFIG_SMP 477 return cpu_online_mask; 478 #else 479 return cpumask_of(0); 480 #endif 481 } 482 483 static inline const struct cpumask *online_target_cpus(void) 484 { 485 return cpu_online_mask; 486 } 487 488 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 489 490 491 static inline unsigned int read_apic_id(void) 492 { 493 unsigned int reg; 494 495 reg = apic_read(APIC_ID); 496 497 return apic->get_apic_id(reg); 498 } 499 500 static inline int default_apic_id_valid(int apicid) 501 { 502 return (apicid < 255); 503 } 504 505 extern int default_acpi_madt_oem_check(char *, char *); 506 507 extern void default_setup_apic_routing(void); 508 509 extern struct apic apic_noop; 510 511 #ifdef CONFIG_X86_32 512 513 static inline int noop_x86_32_early_logical_apicid(int cpu) 514 { 515 return BAD_APICID; 516 } 517 518 /* 519 * Set up the logical destination ID. 520 * 521 * Intel recommends to set DFR, LDR and TPR before enabling 522 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 523 * document number 292116). So here it goes... 524 */ 525 extern void default_init_apic_ldr(void); 526 527 static inline int default_apic_id_registered(void) 528 { 529 return physid_isset(read_apic_id(), phys_cpu_present_map); 530 } 531 532 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 533 { 534 return cpuid_apic >> index_msb; 535 } 536 537 #endif 538 539 static inline int 540 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 541 const struct cpumask *andmask, 542 unsigned int *apicid) 543 { 544 unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 545 cpumask_bits(andmask)[0] & 546 cpumask_bits(cpu_online_mask)[0] & 547 APIC_ALL_CPUS; 548 549 if (likely(cpu_mask)) { 550 *apicid = (unsigned int)cpu_mask; 551 return 0; 552 } else { 553 return -EINVAL; 554 } 555 } 556 557 extern int 558 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 559 const struct cpumask *andmask, 560 unsigned int *apicid); 561 562 static inline void 563 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 564 const struct cpumask *mask) 565 { 566 /* Careful. Some cpus do not strictly honor the set of cpus 567 * specified in the interrupt destination when using lowest 568 * priority interrupt delivery mode. 569 * 570 * In particular there was a hyperthreading cpu observed to 571 * deliver interrupts to the wrong hyperthread when only one 572 * hyperthread was specified in the interrupt desitination. 573 */ 574 cpumask_clear(retmask); 575 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 576 } 577 578 static inline void 579 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 580 const struct cpumask *mask) 581 { 582 cpumask_copy(retmask, cpumask_of(cpu)); 583 } 584 585 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 586 { 587 return physid_isset(apicid, *map); 588 } 589 590 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 591 { 592 *retmap = *phys_map; 593 } 594 595 static inline int __default_cpu_present_to_apicid(int mps_cpu) 596 { 597 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 598 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 599 else 600 return BAD_APICID; 601 } 602 603 static inline int 604 __default_check_phys_apicid_present(int phys_apicid) 605 { 606 return physid_isset(phys_apicid, phys_cpu_present_map); 607 } 608 609 #ifdef CONFIG_X86_32 610 static inline int default_cpu_present_to_apicid(int mps_cpu) 611 { 612 return __default_cpu_present_to_apicid(mps_cpu); 613 } 614 615 static inline int 616 default_check_phys_apicid_present(int phys_apicid) 617 { 618 return __default_check_phys_apicid_present(phys_apicid); 619 } 620 #else 621 extern int default_cpu_present_to_apicid(int mps_cpu); 622 extern int default_check_phys_apicid_present(int phys_apicid); 623 #endif 624 625 #endif /* CONFIG_X86_LOCAL_APIC */ 626 extern void irq_enter(void); 627 extern void irq_exit(void); 628 629 static inline void entering_irq(void) 630 { 631 irq_enter(); 632 exit_idle(); 633 } 634 635 static inline void entering_ack_irq(void) 636 { 637 ack_APIC_irq(); 638 entering_irq(); 639 } 640 641 static inline void exiting_irq(void) 642 { 643 irq_exit(); 644 } 645 646 static inline void exiting_ack_irq(void) 647 { 648 irq_exit(); 649 /* Ack only at the end to avoid potential reentry */ 650 ack_APIC_irq(); 651 } 652 653 extern void ioapic_zap_locks(void); 654 655 #endif /* _ASM_X86_APIC_H */ 656