1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 16 #define ARCH_APICTIMER_STOPS_ON_C3 1 17 18 /* 19 * Debugging macros 20 */ 21 #define APIC_QUIET 0 22 #define APIC_VERBOSE 1 23 #define APIC_DEBUG 2 24 25 /* 26 * Define the default level of output to be very little 27 * This can be turned up by using apic=verbose for more 28 * information and apic=debug for _lots_ of information. 29 * apic_verbosity is defined in apic.c 30 */ 31 #define apic_printk(v, s, a...) do { \ 32 if ((v) <= apic_verbosity) \ 33 printk(s, ##a); \ 34 } while (0) 35 36 37 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 38 extern void generic_apic_probe(void); 39 #else 40 static inline void generic_apic_probe(void) 41 { 42 } 43 #endif 44 45 #ifdef CONFIG_X86_LOCAL_APIC 46 47 extern unsigned int apic_verbosity; 48 extern int local_apic_timer_c2_ok; 49 50 extern int disable_apic; 51 extern unsigned int lapic_timer_frequency; 52 53 #ifdef CONFIG_SMP 54 extern void __inquire_remote_apic(int apicid); 55 #else /* CONFIG_SMP */ 56 static inline void __inquire_remote_apic(int apicid) 57 { 58 } 59 #endif /* CONFIG_SMP */ 60 61 static inline void default_inquire_remote_apic(int apicid) 62 { 63 if (apic_verbosity >= APIC_DEBUG) 64 __inquire_remote_apic(apicid); 65 } 66 67 /* 68 * With 82489DX we can't rely on apic feature bit 69 * retrieved via cpuid but still have to deal with 70 * such an apic chip so we assume that SMP configuration 71 * is found from MP table (64bit case uses ACPI mostly 72 * which set smp presence flag as well so we are safe 73 * to use this helper too). 74 */ 75 static inline bool apic_from_smp_config(void) 76 { 77 return smp_found_config && !disable_apic; 78 } 79 80 /* 81 * Basic functions accessing APICs. 82 */ 83 #ifdef CONFIG_PARAVIRT 84 #include <asm/paravirt.h> 85 #endif 86 87 #ifdef CONFIG_X86_64 88 extern int is_vsmp_box(void); 89 #else 90 static inline int is_vsmp_box(void) 91 { 92 return 0; 93 } 94 #endif 95 extern void xapic_wait_icr_idle(void); 96 extern u32 safe_xapic_wait_icr_idle(void); 97 extern void xapic_icr_write(u32, u32); 98 extern int setup_profiling_timer(unsigned int); 99 100 static inline void native_apic_mem_write(u32 reg, u32 v) 101 { 102 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 103 104 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 105 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 106 ASM_OUTPUT2("0" (v), "m" (*addr))); 107 } 108 109 static inline u32 native_apic_mem_read(u32 reg) 110 { 111 return *((volatile u32 *)(APIC_BASE + reg)); 112 } 113 114 extern void native_apic_wait_icr_idle(void); 115 extern u32 native_safe_apic_wait_icr_idle(void); 116 extern void native_apic_icr_write(u32 low, u32 id); 117 extern u64 native_apic_icr_read(void); 118 119 extern int x2apic_mode; 120 121 #ifdef CONFIG_X86_X2APIC 122 /* 123 * Make previous memory operations globally visible before 124 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 125 * mfence for this. 126 */ 127 static inline void x2apic_wrmsr_fence(void) 128 { 129 asm volatile("mfence" : : : "memory"); 130 } 131 132 static inline void native_apic_msr_write(u32 reg, u32 v) 133 { 134 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 135 reg == APIC_LVR) 136 return; 137 138 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 139 } 140 141 static inline u32 native_apic_msr_read(u32 reg) 142 { 143 u64 msr; 144 145 if (reg == APIC_DFR) 146 return -1; 147 148 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 149 return (u32)msr; 150 } 151 152 static inline void native_x2apic_wait_icr_idle(void) 153 { 154 /* no need to wait for icr idle in x2apic */ 155 return; 156 } 157 158 static inline u32 native_safe_x2apic_wait_icr_idle(void) 159 { 160 /* no need to wait for icr idle in x2apic */ 161 return 0; 162 } 163 164 static inline void native_x2apic_icr_write(u32 low, u32 id) 165 { 166 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 167 } 168 169 static inline u64 native_x2apic_icr_read(void) 170 { 171 unsigned long val; 172 173 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 174 return val; 175 } 176 177 extern int x2apic_phys; 178 extern int x2apic_preenabled; 179 extern void check_x2apic(void); 180 extern void enable_x2apic(void); 181 extern void x2apic_icr_write(u32 low, u32 id); 182 static inline int x2apic_enabled(void) 183 { 184 u64 msr; 185 186 if (!cpu_has_x2apic) 187 return 0; 188 189 rdmsrl(MSR_IA32_APICBASE, msr); 190 if (msr & X2APIC_ENABLE) 191 return 1; 192 return 0; 193 } 194 195 #define x2apic_supported() (cpu_has_x2apic) 196 static inline void x2apic_force_phys(void) 197 { 198 x2apic_phys = 1; 199 } 200 #else 201 static inline void disable_x2apic(void) 202 { 203 } 204 static inline void check_x2apic(void) 205 { 206 } 207 static inline void enable_x2apic(void) 208 { 209 } 210 static inline int x2apic_enabled(void) 211 { 212 return 0; 213 } 214 static inline void x2apic_force_phys(void) 215 { 216 } 217 218 #define nox2apic 0 219 #define x2apic_preenabled 0 220 #define x2apic_supported() 0 221 #endif 222 223 extern void enable_IR_x2apic(void); 224 225 extern int get_physical_broadcast(void); 226 227 extern int lapic_get_maxlvt(void); 228 extern void clear_local_APIC(void); 229 extern void connect_bsp_APIC(void); 230 extern void disconnect_bsp_APIC(int virt_wire_setup); 231 extern void disable_local_APIC(void); 232 extern void lapic_shutdown(void); 233 extern int verify_local_APIC(void); 234 extern void sync_Arb_IDs(void); 235 extern void init_bsp_APIC(void); 236 extern void setup_local_APIC(void); 237 extern void end_local_APIC_setup(void); 238 extern void bsp_end_local_APIC_setup(void); 239 extern void init_apic_mappings(void); 240 void register_lapic_address(unsigned long address); 241 extern void setup_boot_APIC_clock(void); 242 extern void setup_secondary_APIC_clock(void); 243 extern int APIC_init_uniprocessor(void); 244 extern int apic_force_enable(unsigned long addr); 245 246 /* 247 * On 32bit this is mach-xxx local 248 */ 249 #ifdef CONFIG_X86_64 250 extern int apic_is_clustered_box(void); 251 #else 252 static inline int apic_is_clustered_box(void) 253 { 254 return 0; 255 } 256 #endif 257 258 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 259 260 #else /* !CONFIG_X86_LOCAL_APIC */ 261 static inline void lapic_shutdown(void) { } 262 #define local_apic_timer_c2_ok 1 263 static inline void init_apic_mappings(void) { } 264 static inline void disable_local_APIC(void) { } 265 # define setup_boot_APIC_clock x86_init_noop 266 # define setup_secondary_APIC_clock x86_init_noop 267 #endif /* !CONFIG_X86_LOCAL_APIC */ 268 269 #ifdef CONFIG_X86_64 270 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 271 #else 272 273 #endif 274 275 /* 276 * Copyright 2004 James Cleverdon, IBM. 277 * Subject to the GNU Public License, v.2 278 * 279 * Generic APIC sub-arch data struct. 280 * 281 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 282 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 283 * James Cleverdon. 284 */ 285 struct apic { 286 char *name; 287 288 int (*probe)(void); 289 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 290 int (*apic_id_valid)(int apicid); 291 int (*apic_id_registered)(void); 292 293 u32 irq_delivery_mode; 294 u32 irq_dest_mode; 295 296 const struct cpumask *(*target_cpus)(void); 297 298 int disable_esr; 299 300 int dest_logical; 301 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 302 unsigned long (*check_apicid_present)(int apicid); 303 304 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 305 void (*init_apic_ldr)(void); 306 307 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 308 309 void (*setup_apic_routing)(void); 310 int (*multi_timer_check)(int apic, int irq); 311 int (*cpu_present_to_apicid)(int mps_cpu); 312 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 313 void (*setup_portio_remap)(void); 314 int (*check_phys_apicid_present)(int phys_apicid); 315 void (*enable_apic_mode)(void); 316 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 317 318 /* 319 * When one of the next two hooks returns 1 the apic 320 * is switched to this. Essentially they are additional 321 * probe functions: 322 */ 323 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 324 325 unsigned int (*get_apic_id)(unsigned long x); 326 unsigned long (*set_apic_id)(unsigned int id); 327 unsigned long apic_id_mask; 328 329 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 330 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 331 const struct cpumask *andmask); 332 333 /* ipi */ 334 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 335 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 336 int vector); 337 void (*send_IPI_allbutself)(int vector); 338 void (*send_IPI_all)(int vector); 339 void (*send_IPI_self)(int vector); 340 341 /* wakeup_secondary_cpu */ 342 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 343 344 int trampoline_phys_low; 345 int trampoline_phys_high; 346 347 void (*wait_for_init_deassert)(atomic_t *deassert); 348 void (*smp_callin_clear_local_apic)(void); 349 void (*inquire_remote_apic)(int apicid); 350 351 /* apic ops */ 352 u32 (*read)(u32 reg); 353 void (*write)(u32 reg, u32 v); 354 u64 (*icr_read)(void); 355 void (*icr_write)(u32 low, u32 high); 356 void (*wait_icr_idle)(void); 357 u32 (*safe_wait_icr_idle)(void); 358 359 #ifdef CONFIG_X86_32 360 /* 361 * Called very early during boot from get_smp_config(). It should 362 * return the logical apicid. x86_[bios]_cpu_to_apicid is 363 * initialized before this function is called. 364 * 365 * If logical apicid can't be determined that early, the function 366 * may return BAD_APICID. Logical apicid will be configured after 367 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 368 * won't be applied properly during early boot in this case. 369 */ 370 int (*x86_32_early_logical_apicid)(int cpu); 371 372 /* 373 * Optional method called from setup_local_APIC() after logical 374 * apicid is guaranteed to be known to initialize apicid -> node 375 * mapping if NUMA initialization hasn't done so already. Don't 376 * add new users. 377 */ 378 int (*x86_32_numa_cpu_node)(int cpu); 379 #endif 380 }; 381 382 /* 383 * Pointer to the local APIC driver in use on this system (there's 384 * always just one such driver in use - the kernel decides via an 385 * early probing process which one it picks - and then sticks to it): 386 */ 387 extern struct apic *apic; 388 389 /* 390 * APIC drivers are probed based on how they are listed in the .apicdrivers 391 * section. So the order is important and enforced by the ordering 392 * of different apic driver files in the Makefile. 393 * 394 * For the files having two apic drivers, we use apic_drivers() 395 * to enforce the order with in them. 396 */ 397 #define apic_driver(sym) \ 398 static struct apic *__apicdrivers_##sym __used \ 399 __aligned(sizeof(struct apic *)) \ 400 __section(.apicdrivers) = { &sym } 401 402 #define apic_drivers(sym1, sym2) \ 403 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 404 __aligned(sizeof(struct apic *)) \ 405 __section(.apicdrivers) = { &sym1, &sym2 } 406 407 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 408 409 /* 410 * APIC functionality to boot other CPUs - only used on SMP: 411 */ 412 #ifdef CONFIG_SMP 413 extern atomic_t init_deasserted; 414 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 415 #endif 416 417 #ifdef CONFIG_X86_LOCAL_APIC 418 419 static inline u32 apic_read(u32 reg) 420 { 421 return apic->read(reg); 422 } 423 424 static inline void apic_write(u32 reg, u32 val) 425 { 426 apic->write(reg, val); 427 } 428 429 static inline u64 apic_icr_read(void) 430 { 431 return apic->icr_read(); 432 } 433 434 static inline void apic_icr_write(u32 low, u32 high) 435 { 436 apic->icr_write(low, high); 437 } 438 439 static inline void apic_wait_icr_idle(void) 440 { 441 apic->wait_icr_idle(); 442 } 443 444 static inline u32 safe_apic_wait_icr_idle(void) 445 { 446 return apic->safe_wait_icr_idle(); 447 } 448 449 #else /* CONFIG_X86_LOCAL_APIC */ 450 451 static inline u32 apic_read(u32 reg) { return 0; } 452 static inline void apic_write(u32 reg, u32 val) { } 453 static inline u64 apic_icr_read(void) { return 0; } 454 static inline void apic_icr_write(u32 low, u32 high) { } 455 static inline void apic_wait_icr_idle(void) { } 456 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 457 458 #endif /* CONFIG_X86_LOCAL_APIC */ 459 460 static inline void ack_APIC_irq(void) 461 { 462 /* 463 * ack_APIC_irq() actually gets compiled as a single instruction 464 * ... yummie. 465 */ 466 apic_write(APIC_EOI, APIC_EOI_ACK); 467 } 468 469 static inline unsigned default_get_apic_id(unsigned long x) 470 { 471 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 472 473 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 474 return (x >> 24) & 0xFF; 475 else 476 return (x >> 24) & 0x0F; 477 } 478 479 /* 480 * Warm reset vector default position: 481 */ 482 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 483 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 484 485 #ifdef CONFIG_X86_64 486 extern int default_acpi_madt_oem_check(char *, char *); 487 488 extern void apic_send_IPI_self(int vector); 489 490 DECLARE_PER_CPU(int, x2apic_extra_bits); 491 492 extern int default_cpu_present_to_apicid(int mps_cpu); 493 extern int default_check_phys_apicid_present(int phys_apicid); 494 #endif 495 496 static inline void default_wait_for_init_deassert(atomic_t *deassert) 497 { 498 while (!atomic_read(deassert)) 499 cpu_relax(); 500 return; 501 } 502 503 extern void generic_bigsmp_probe(void); 504 505 506 #ifdef CONFIG_X86_LOCAL_APIC 507 508 #include <asm/smp.h> 509 510 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 511 512 static inline const struct cpumask *default_target_cpus(void) 513 { 514 #ifdef CONFIG_SMP 515 return cpu_online_mask; 516 #else 517 return cpumask_of(0); 518 #endif 519 } 520 521 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 522 523 524 static inline unsigned int read_apic_id(void) 525 { 526 unsigned int reg; 527 528 reg = apic_read(APIC_ID); 529 530 return apic->get_apic_id(reg); 531 } 532 533 static inline int default_apic_id_valid(int apicid) 534 { 535 return (apicid < 255); 536 } 537 538 extern void default_setup_apic_routing(void); 539 540 extern struct apic apic_noop; 541 542 #ifdef CONFIG_X86_32 543 544 static inline int noop_x86_32_early_logical_apicid(int cpu) 545 { 546 return BAD_APICID; 547 } 548 549 /* 550 * Set up the logical destination ID. 551 * 552 * Intel recommends to set DFR, LDR and TPR before enabling 553 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 554 * document number 292116). So here it goes... 555 */ 556 extern void default_init_apic_ldr(void); 557 558 static inline int default_apic_id_registered(void) 559 { 560 return physid_isset(read_apic_id(), phys_cpu_present_map); 561 } 562 563 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 564 { 565 return cpuid_apic >> index_msb; 566 } 567 568 #endif 569 570 static inline unsigned int 571 default_cpu_mask_to_apicid(const struct cpumask *cpumask) 572 { 573 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 574 } 575 576 static inline unsigned int 577 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 578 const struct cpumask *andmask) 579 { 580 unsigned long mask1 = cpumask_bits(cpumask)[0]; 581 unsigned long mask2 = cpumask_bits(andmask)[0]; 582 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 583 584 return (unsigned int)(mask1 & mask2 & mask3); 585 } 586 587 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 588 { 589 return physid_isset(apicid, *map); 590 } 591 592 static inline unsigned long default_check_apicid_present(int bit) 593 { 594 return physid_isset(bit, phys_cpu_present_map); 595 } 596 597 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 598 { 599 *retmap = *phys_map; 600 } 601 602 static inline int __default_cpu_present_to_apicid(int mps_cpu) 603 { 604 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 605 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 606 else 607 return BAD_APICID; 608 } 609 610 static inline int 611 __default_check_phys_apicid_present(int phys_apicid) 612 { 613 return physid_isset(phys_apicid, phys_cpu_present_map); 614 } 615 616 #ifdef CONFIG_X86_32 617 static inline int default_cpu_present_to_apicid(int mps_cpu) 618 { 619 return __default_cpu_present_to_apicid(mps_cpu); 620 } 621 622 static inline int 623 default_check_phys_apicid_present(int phys_apicid) 624 { 625 return __default_check_phys_apicid_present(phys_apicid); 626 } 627 #else 628 extern int default_cpu_present_to_apicid(int mps_cpu); 629 extern int default_check_phys_apicid_present(int phys_apicid); 630 #endif 631 632 #endif /* CONFIG_X86_LOCAL_APIC */ 633 634 #endif /* _ASM_X86_APIC_H */ 635