1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 6 #include <asm/alternative.h> 7 #include <asm/cpufeature.h> 8 #include <asm/apicdef.h> 9 #include <linux/atomic.h> 10 #include <asm/fixmap.h> 11 #include <asm/mpspec.h> 12 #include <asm/msr.h> 13 14 #define ARCH_APICTIMER_STOPS_ON_C3 1 15 16 /* 17 * Debugging macros 18 */ 19 #define APIC_QUIET 0 20 #define APIC_VERBOSE 1 21 #define APIC_DEBUG 2 22 23 /* Macros for apic_extnmi which controls external NMI masking */ 24 #define APIC_EXTNMI_BSP 0 /* Default */ 25 #define APIC_EXTNMI_ALL 1 26 #define APIC_EXTNMI_NONE 2 27 28 /* 29 * Define the default level of output to be very little 30 * This can be turned up by using apic=verbose for more 31 * information and apic=debug for _lots_ of information. 32 * apic_verbosity is defined in apic.c 33 */ 34 #define apic_printk(v, s, a...) do { \ 35 if ((v) <= apic_verbosity) \ 36 printk(s, ##a); \ 37 } while (0) 38 39 40 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 41 extern void generic_apic_probe(void); 42 #else 43 static inline void generic_apic_probe(void) 44 { 45 } 46 #endif 47 48 #ifdef CONFIG_X86_LOCAL_APIC 49 50 extern unsigned int apic_verbosity; 51 extern int local_apic_timer_c2_ok; 52 53 extern int disable_apic; 54 extern unsigned int lapic_timer_frequency; 55 56 #ifdef CONFIG_SMP 57 extern void __inquire_remote_apic(int apicid); 58 #else /* CONFIG_SMP */ 59 static inline void __inquire_remote_apic(int apicid) 60 { 61 } 62 #endif /* CONFIG_SMP */ 63 64 static inline void default_inquire_remote_apic(int apicid) 65 { 66 if (apic_verbosity >= APIC_DEBUG) 67 __inquire_remote_apic(apicid); 68 } 69 70 /* 71 * With 82489DX we can't rely on apic feature bit 72 * retrieved via cpuid but still have to deal with 73 * such an apic chip so we assume that SMP configuration 74 * is found from MP table (64bit case uses ACPI mostly 75 * which set smp presence flag as well so we are safe 76 * to use this helper too). 77 */ 78 static inline bool apic_from_smp_config(void) 79 { 80 return smp_found_config && !disable_apic; 81 } 82 83 /* 84 * Basic functions accessing APICs. 85 */ 86 #ifdef CONFIG_PARAVIRT 87 #include <asm/paravirt.h> 88 #endif 89 90 extern int setup_profiling_timer(unsigned int); 91 92 static inline void native_apic_mem_write(u32 reg, u32 v) 93 { 94 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 95 96 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 97 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 98 ASM_OUTPUT2("0" (v), "m" (*addr))); 99 } 100 101 static inline u32 native_apic_mem_read(u32 reg) 102 { 103 return *((volatile u32 *)(APIC_BASE + reg)); 104 } 105 106 extern void native_apic_wait_icr_idle(void); 107 extern u32 native_safe_apic_wait_icr_idle(void); 108 extern void native_apic_icr_write(u32 low, u32 id); 109 extern u64 native_apic_icr_read(void); 110 111 static inline bool apic_is_x2apic_enabled(void) 112 { 113 u64 msr; 114 115 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 116 return false; 117 return msr & X2APIC_ENABLE; 118 } 119 120 extern void enable_IR_x2apic(void); 121 122 extern int get_physical_broadcast(void); 123 124 extern int lapic_get_maxlvt(void); 125 extern void clear_local_APIC(void); 126 extern void disconnect_bsp_APIC(int virt_wire_setup); 127 extern void disable_local_APIC(void); 128 extern void lapic_shutdown(void); 129 extern void sync_Arb_IDs(void); 130 extern void init_bsp_APIC(void); 131 extern void apic_intr_mode_init(void); 132 extern void setup_local_APIC(void); 133 extern void init_apic_mappings(void); 134 void register_lapic_address(unsigned long address); 135 extern void setup_boot_APIC_clock(void); 136 extern void setup_secondary_APIC_clock(void); 137 extern void lapic_update_tsc_freq(void); 138 extern int APIC_init_uniprocessor(void); 139 140 #ifdef CONFIG_X86_64 141 static inline int apic_force_enable(unsigned long addr) 142 { 143 return -1; 144 } 145 #else 146 extern int apic_force_enable(unsigned long addr); 147 #endif 148 149 extern void apic_bsp_setup(bool upmode); 150 extern void apic_ap_setup(void); 151 152 /* 153 * On 32bit this is mach-xxx local 154 */ 155 #ifdef CONFIG_X86_64 156 extern int apic_is_clustered_box(void); 157 #else 158 static inline int apic_is_clustered_box(void) 159 { 160 return 0; 161 } 162 #endif 163 164 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 165 166 #else /* !CONFIG_X86_LOCAL_APIC */ 167 static inline void lapic_shutdown(void) { } 168 #define local_apic_timer_c2_ok 1 169 static inline void init_apic_mappings(void) { } 170 static inline void disable_local_APIC(void) { } 171 # define setup_boot_APIC_clock x86_init_noop 172 # define setup_secondary_APIC_clock x86_init_noop 173 static inline void lapic_update_tsc_freq(void) { } 174 static inline void apic_intr_mode_init(void) { } 175 #endif /* !CONFIG_X86_LOCAL_APIC */ 176 177 #ifdef CONFIG_X86_X2APIC 178 /* 179 * Make previous memory operations globally visible before 180 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 181 * mfence for this. 182 */ 183 static inline void x2apic_wrmsr_fence(void) 184 { 185 asm volatile("mfence" : : : "memory"); 186 } 187 188 static inline void native_apic_msr_write(u32 reg, u32 v) 189 { 190 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 191 reg == APIC_LVR) 192 return; 193 194 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 195 } 196 197 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 198 { 199 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 200 } 201 202 static inline u32 native_apic_msr_read(u32 reg) 203 { 204 u64 msr; 205 206 if (reg == APIC_DFR) 207 return -1; 208 209 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 210 return (u32)msr; 211 } 212 213 static inline void native_x2apic_wait_icr_idle(void) 214 { 215 /* no need to wait for icr idle in x2apic */ 216 return; 217 } 218 219 static inline u32 native_safe_x2apic_wait_icr_idle(void) 220 { 221 /* no need to wait for icr idle in x2apic */ 222 return 0; 223 } 224 225 static inline void native_x2apic_icr_write(u32 low, u32 id) 226 { 227 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 228 } 229 230 static inline u64 native_x2apic_icr_read(void) 231 { 232 unsigned long val; 233 234 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 235 return val; 236 } 237 238 extern int x2apic_mode; 239 extern int x2apic_phys; 240 extern void __init check_x2apic(void); 241 extern void x2apic_setup(void); 242 static inline int x2apic_enabled(void) 243 { 244 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 245 } 246 247 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 248 #else /* !CONFIG_X86_X2APIC */ 249 static inline void check_x2apic(void) { } 250 static inline void x2apic_setup(void) { } 251 static inline int x2apic_enabled(void) { return 0; } 252 253 #define x2apic_mode (0) 254 #define x2apic_supported() (0) 255 #endif /* !CONFIG_X86_X2APIC */ 256 257 struct irq_data; 258 259 /* 260 * Copyright 2004 James Cleverdon, IBM. 261 * Subject to the GNU Public License, v.2 262 * 263 * Generic APIC sub-arch data struct. 264 * 265 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 266 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 267 * James Cleverdon. 268 */ 269 struct apic { 270 char *name; 271 272 int (*probe)(void); 273 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 274 int (*apic_id_valid)(int apicid); 275 int (*apic_id_registered)(void); 276 277 u32 irq_delivery_mode; 278 u32 irq_dest_mode; 279 280 const struct cpumask *(*target_cpus)(void); 281 282 int disable_esr; 283 284 int dest_logical; 285 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 286 287 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 288 const struct cpumask *mask); 289 void (*init_apic_ldr)(void); 290 291 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 292 293 void (*setup_apic_routing)(void); 294 int (*cpu_present_to_apicid)(int mps_cpu); 295 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 296 int (*check_phys_apicid_present)(int phys_apicid); 297 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 298 299 unsigned int (*get_apic_id)(unsigned long x); 300 /* Can't be NULL on 64-bit */ 301 unsigned long (*set_apic_id)(unsigned int id); 302 303 int (*cpu_mask_to_apicid)(const struct cpumask *cpumask, 304 struct irq_data *irqdata, 305 unsigned int *apicid); 306 307 /* ipi */ 308 void (*send_IPI)(int cpu, int vector); 309 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 310 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 311 int vector); 312 void (*send_IPI_allbutself)(int vector); 313 void (*send_IPI_all)(int vector); 314 void (*send_IPI_self)(int vector); 315 316 /* wakeup_secondary_cpu */ 317 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 318 319 void (*inquire_remote_apic)(int apicid); 320 321 /* apic ops */ 322 u32 (*read)(u32 reg); 323 void (*write)(u32 reg, u32 v); 324 /* 325 * ->eoi_write() has the same signature as ->write(). 326 * 327 * Drivers can support both ->eoi_write() and ->write() by passing the same 328 * callback value. Kernel can override ->eoi_write() and fall back 329 * on write for EOI. 330 */ 331 void (*eoi_write)(u32 reg, u32 v); 332 void (*native_eoi_write)(u32 reg, u32 v); 333 u64 (*icr_read)(void); 334 void (*icr_write)(u32 low, u32 high); 335 void (*wait_icr_idle)(void); 336 u32 (*safe_wait_icr_idle)(void); 337 338 #ifdef CONFIG_X86_32 339 /* 340 * Called very early during boot from get_smp_config(). It should 341 * return the logical apicid. x86_[bios]_cpu_to_apicid is 342 * initialized before this function is called. 343 * 344 * If logical apicid can't be determined that early, the function 345 * may return BAD_APICID. Logical apicid will be configured after 346 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 347 * won't be applied properly during early boot in this case. 348 */ 349 int (*x86_32_early_logical_apicid)(int cpu); 350 #endif 351 }; 352 353 /* 354 * Pointer to the local APIC driver in use on this system (there's 355 * always just one such driver in use - the kernel decides via an 356 * early probing process which one it picks - and then sticks to it): 357 */ 358 extern struct apic *apic; 359 360 /* 361 * APIC drivers are probed based on how they are listed in the .apicdrivers 362 * section. So the order is important and enforced by the ordering 363 * of different apic driver files in the Makefile. 364 * 365 * For the files having two apic drivers, we use apic_drivers() 366 * to enforce the order with in them. 367 */ 368 #define apic_driver(sym) \ 369 static const struct apic *__apicdrivers_##sym __used \ 370 __aligned(sizeof(struct apic *)) \ 371 __section(.apicdrivers) = { &sym } 372 373 #define apic_drivers(sym1, sym2) \ 374 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 375 __aligned(sizeof(struct apic *)) \ 376 __section(.apicdrivers) = { &sym1, &sym2 } 377 378 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 379 380 /* 381 * APIC functionality to boot other CPUs - only used on SMP: 382 */ 383 #ifdef CONFIG_SMP 384 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 385 #endif 386 387 #ifdef CONFIG_X86_LOCAL_APIC 388 389 static inline u32 apic_read(u32 reg) 390 { 391 return apic->read(reg); 392 } 393 394 static inline void apic_write(u32 reg, u32 val) 395 { 396 apic->write(reg, val); 397 } 398 399 static inline void apic_eoi(void) 400 { 401 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 402 } 403 404 static inline u64 apic_icr_read(void) 405 { 406 return apic->icr_read(); 407 } 408 409 static inline void apic_icr_write(u32 low, u32 high) 410 { 411 apic->icr_write(low, high); 412 } 413 414 static inline void apic_wait_icr_idle(void) 415 { 416 apic->wait_icr_idle(); 417 } 418 419 static inline u32 safe_apic_wait_icr_idle(void) 420 { 421 return apic->safe_wait_icr_idle(); 422 } 423 424 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 425 426 #else /* CONFIG_X86_LOCAL_APIC */ 427 428 static inline u32 apic_read(u32 reg) { return 0; } 429 static inline void apic_write(u32 reg, u32 val) { } 430 static inline void apic_eoi(void) { } 431 static inline u64 apic_icr_read(void) { return 0; } 432 static inline void apic_icr_write(u32 low, u32 high) { } 433 static inline void apic_wait_icr_idle(void) { } 434 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 435 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 436 437 #endif /* CONFIG_X86_LOCAL_APIC */ 438 439 static inline void ack_APIC_irq(void) 440 { 441 /* 442 * ack_APIC_irq() actually gets compiled as a single instruction 443 * ... yummie. 444 */ 445 apic_eoi(); 446 } 447 448 static inline unsigned default_get_apic_id(unsigned long x) 449 { 450 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 451 452 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 453 return (x >> 24) & 0xFF; 454 else 455 return (x >> 24) & 0x0F; 456 } 457 458 /* 459 * Warm reset vector position: 460 */ 461 #define TRAMPOLINE_PHYS_LOW 0x467 462 #define TRAMPOLINE_PHYS_HIGH 0x469 463 464 #ifdef CONFIG_X86_64 465 extern void apic_send_IPI_self(int vector); 466 467 DECLARE_PER_CPU(int, x2apic_extra_bits); 468 469 extern int default_cpu_present_to_apicid(int mps_cpu); 470 extern int default_check_phys_apicid_present(int phys_apicid); 471 #endif 472 473 extern void generic_bigsmp_probe(void); 474 475 476 #ifdef CONFIG_X86_LOCAL_APIC 477 478 #include <asm/smp.h> 479 480 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 481 482 static inline const struct cpumask *default_target_cpus(void) 483 { 484 #ifdef CONFIG_SMP 485 return cpu_online_mask; 486 #else 487 return cpumask_of(0); 488 #endif 489 } 490 491 static inline const struct cpumask *online_target_cpus(void) 492 { 493 return cpu_online_mask; 494 } 495 496 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 497 498 499 static inline unsigned int read_apic_id(void) 500 { 501 unsigned int reg; 502 503 reg = apic_read(APIC_ID); 504 505 return apic->get_apic_id(reg); 506 } 507 508 static inline int default_apic_id_valid(int apicid) 509 { 510 return (apicid < 255); 511 } 512 513 extern int default_acpi_madt_oem_check(char *, char *); 514 515 extern void default_setup_apic_routing(void); 516 517 extern struct apic apic_noop; 518 519 #ifdef CONFIG_X86_32 520 521 static inline int noop_x86_32_early_logical_apicid(int cpu) 522 { 523 return BAD_APICID; 524 } 525 526 /* 527 * Set up the logical destination ID. 528 * 529 * Intel recommends to set DFR, LDR and TPR before enabling 530 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 531 * document number 292116). So here it goes... 532 */ 533 extern void default_init_apic_ldr(void); 534 535 static inline int default_apic_id_registered(void) 536 { 537 return physid_isset(read_apic_id(), phys_cpu_present_map); 538 } 539 540 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 541 { 542 return cpuid_apic >> index_msb; 543 } 544 545 #endif 546 547 extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask, 548 struct irq_data *irqdata, 549 unsigned int *apicid); 550 extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask, 551 struct irq_data *irqdata, 552 unsigned int *apicid); 553 554 static inline void 555 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 556 const struct cpumask *mask) 557 { 558 /* Careful. Some cpus do not strictly honor the set of cpus 559 * specified in the interrupt destination when using lowest 560 * priority interrupt delivery mode. 561 * 562 * In particular there was a hyperthreading cpu observed to 563 * deliver interrupts to the wrong hyperthread when only one 564 * hyperthread was specified in the interrupt desitination. 565 */ 566 cpumask_clear(retmask); 567 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 568 } 569 570 static inline void 571 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 572 const struct cpumask *mask) 573 { 574 cpumask_copy(retmask, cpumask_of(cpu)); 575 } 576 577 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 578 { 579 return physid_isset(apicid, *map); 580 } 581 582 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 583 { 584 *retmap = *phys_map; 585 } 586 587 static inline int __default_cpu_present_to_apicid(int mps_cpu) 588 { 589 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 590 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 591 else 592 return BAD_APICID; 593 } 594 595 static inline int 596 __default_check_phys_apicid_present(int phys_apicid) 597 { 598 return physid_isset(phys_apicid, phys_cpu_present_map); 599 } 600 601 #ifdef CONFIG_X86_32 602 static inline int default_cpu_present_to_apicid(int mps_cpu) 603 { 604 return __default_cpu_present_to_apicid(mps_cpu); 605 } 606 607 static inline int 608 default_check_phys_apicid_present(int phys_apicid) 609 { 610 return __default_check_phys_apicid_present(phys_apicid); 611 } 612 #else 613 extern int default_cpu_present_to_apicid(int mps_cpu); 614 extern int default_check_phys_apicid_present(int phys_apicid); 615 #endif 616 617 #endif /* CONFIG_X86_LOCAL_APIC */ 618 extern void irq_enter(void); 619 extern void irq_exit(void); 620 621 static inline void entering_irq(void) 622 { 623 irq_enter(); 624 } 625 626 static inline void entering_ack_irq(void) 627 { 628 entering_irq(); 629 ack_APIC_irq(); 630 } 631 632 static inline void ipi_entering_ack_irq(void) 633 { 634 irq_enter(); 635 ack_APIC_irq(); 636 } 637 638 static inline void exiting_irq(void) 639 { 640 irq_exit(); 641 } 642 643 static inline void exiting_ack_irq(void) 644 { 645 ack_APIC_irq(); 646 irq_exit(); 647 } 648 649 extern void ioapic_zap_locks(void); 650 651 #endif /* _ASM_X86_APIC_H */ 652