1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/idle.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* 27 * Define the default level of output to be very little 28 * This can be turned up by using apic=verbose for more 29 * information and apic=debug for _lots_ of information. 30 * apic_verbosity is defined in apic.c 31 */ 32 #define apic_printk(v, s, a...) do { \ 33 if ((v) <= apic_verbosity) \ 34 printk(s, ##a); \ 35 } while (0) 36 37 38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39 extern void generic_apic_probe(void); 40 #else 41 static inline void generic_apic_probe(void) 42 { 43 } 44 #endif 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 48 extern unsigned int apic_verbosity; 49 extern int local_apic_timer_c2_ok; 50 51 extern int disable_apic; 52 extern unsigned int lapic_timer_frequency; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 extern int setup_profiling_timer(unsigned int); 89 90 static inline void native_apic_mem_write(u32 reg, u32 v) 91 { 92 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 93 94 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, 95 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 96 ASM_OUTPUT2("0" (v), "m" (*addr))); 97 } 98 99 static inline u32 native_apic_mem_read(u32 reg) 100 { 101 return *((volatile u32 *)(APIC_BASE + reg)); 102 } 103 104 extern void native_apic_wait_icr_idle(void); 105 extern u32 native_safe_apic_wait_icr_idle(void); 106 extern void native_apic_icr_write(u32 low, u32 id); 107 extern u64 native_apic_icr_read(void); 108 109 static inline bool apic_is_x2apic_enabled(void) 110 { 111 u64 msr; 112 113 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 114 return false; 115 return msr & X2APIC_ENABLE; 116 } 117 118 #ifdef CONFIG_X86_X2APIC 119 /* 120 * Make previous memory operations globally visible before 121 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 122 * mfence for this. 123 */ 124 static inline void x2apic_wrmsr_fence(void) 125 { 126 asm volatile("mfence" : : : "memory"); 127 } 128 129 static inline void native_apic_msr_write(u32 reg, u32 v) 130 { 131 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 132 reg == APIC_LVR) 133 return; 134 135 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 136 } 137 138 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 139 { 140 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 141 } 142 143 static inline u32 native_apic_msr_read(u32 reg) 144 { 145 u64 msr; 146 147 if (reg == APIC_DFR) 148 return -1; 149 150 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 151 return (u32)msr; 152 } 153 154 static inline void native_x2apic_wait_icr_idle(void) 155 { 156 /* no need to wait for icr idle in x2apic */ 157 return; 158 } 159 160 static inline u32 native_safe_x2apic_wait_icr_idle(void) 161 { 162 /* no need to wait for icr idle in x2apic */ 163 return 0; 164 } 165 166 static inline void native_x2apic_icr_write(u32 low, u32 id) 167 { 168 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 169 } 170 171 static inline u64 native_x2apic_icr_read(void) 172 { 173 unsigned long val; 174 175 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 176 return val; 177 } 178 179 extern int x2apic_mode; 180 extern int x2apic_phys; 181 extern void __init check_x2apic(void); 182 extern void x2apic_setup(void); 183 static inline int x2apic_enabled(void) 184 { 185 return cpu_has_x2apic && apic_is_x2apic_enabled(); 186 } 187 188 #define x2apic_supported() (cpu_has_x2apic) 189 #else 190 static inline void check_x2apic(void) { } 191 static inline void x2apic_setup(void) { } 192 static inline int x2apic_enabled(void) { return 0; } 193 194 #define x2apic_mode (0) 195 #define x2apic_supported() (0) 196 #endif 197 198 extern void enable_IR_x2apic(void); 199 200 extern int get_physical_broadcast(void); 201 202 extern int lapic_get_maxlvt(void); 203 extern void clear_local_APIC(void); 204 extern void disconnect_bsp_APIC(int virt_wire_setup); 205 extern void disable_local_APIC(void); 206 extern void lapic_shutdown(void); 207 extern int verify_local_APIC(void); 208 extern void sync_Arb_IDs(void); 209 extern void init_bsp_APIC(void); 210 extern void setup_local_APIC(void); 211 extern void init_apic_mappings(void); 212 void register_lapic_address(unsigned long address); 213 extern void setup_boot_APIC_clock(void); 214 extern void setup_secondary_APIC_clock(void); 215 extern int APIC_init_uniprocessor(void); 216 extern int apic_force_enable(unsigned long addr); 217 218 extern int apic_bsp_setup(bool upmode); 219 extern void apic_ap_setup(void); 220 221 /* 222 * On 32bit this is mach-xxx local 223 */ 224 #ifdef CONFIG_X86_64 225 extern int apic_is_clustered_box(void); 226 #else 227 static inline int apic_is_clustered_box(void) 228 { 229 return 0; 230 } 231 #endif 232 233 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 234 235 #else /* !CONFIG_X86_LOCAL_APIC */ 236 static inline void lapic_shutdown(void) { } 237 #define local_apic_timer_c2_ok 1 238 static inline void init_apic_mappings(void) { } 239 static inline void disable_local_APIC(void) { } 240 # define setup_boot_APIC_clock x86_init_noop 241 # define setup_secondary_APIC_clock x86_init_noop 242 #endif /* !CONFIG_X86_LOCAL_APIC */ 243 244 #ifdef CONFIG_X86_64 245 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 246 #else 247 248 #endif 249 250 /* 251 * Copyright 2004 James Cleverdon, IBM. 252 * Subject to the GNU Public License, v.2 253 * 254 * Generic APIC sub-arch data struct. 255 * 256 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 257 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 258 * James Cleverdon. 259 */ 260 struct apic { 261 char *name; 262 263 int (*probe)(void); 264 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 265 int (*apic_id_valid)(int apicid); 266 int (*apic_id_registered)(void); 267 268 u32 irq_delivery_mode; 269 u32 irq_dest_mode; 270 271 const struct cpumask *(*target_cpus)(void); 272 273 int disable_esr; 274 275 int dest_logical; 276 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 277 278 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 279 const struct cpumask *mask); 280 void (*init_apic_ldr)(void); 281 282 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 283 284 void (*setup_apic_routing)(void); 285 int (*cpu_present_to_apicid)(int mps_cpu); 286 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 287 int (*check_phys_apicid_present)(int phys_apicid); 288 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 289 290 unsigned int (*get_apic_id)(unsigned long x); 291 unsigned long (*set_apic_id)(unsigned int id); 292 unsigned long apic_id_mask; 293 294 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 295 const struct cpumask *andmask, 296 unsigned int *apicid); 297 298 /* ipi */ 299 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 300 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 301 int vector); 302 void (*send_IPI_allbutself)(int vector); 303 void (*send_IPI_all)(int vector); 304 void (*send_IPI_self)(int vector); 305 306 /* wakeup_secondary_cpu */ 307 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 308 309 bool wait_for_init_deassert; 310 void (*inquire_remote_apic)(int apicid); 311 312 /* apic ops */ 313 u32 (*read)(u32 reg); 314 void (*write)(u32 reg, u32 v); 315 /* 316 * ->eoi_write() has the same signature as ->write(). 317 * 318 * Drivers can support both ->eoi_write() and ->write() by passing the same 319 * callback value. Kernel can override ->eoi_write() and fall back 320 * on write for EOI. 321 */ 322 void (*eoi_write)(u32 reg, u32 v); 323 u64 (*icr_read)(void); 324 void (*icr_write)(u32 low, u32 high); 325 void (*wait_icr_idle)(void); 326 u32 (*safe_wait_icr_idle)(void); 327 328 #ifdef CONFIG_X86_32 329 /* 330 * Called very early during boot from get_smp_config(). It should 331 * return the logical apicid. x86_[bios]_cpu_to_apicid is 332 * initialized before this function is called. 333 * 334 * If logical apicid can't be determined that early, the function 335 * may return BAD_APICID. Logical apicid will be configured after 336 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 337 * won't be applied properly during early boot in this case. 338 */ 339 int (*x86_32_early_logical_apicid)(int cpu); 340 #endif 341 }; 342 343 /* 344 * Pointer to the local APIC driver in use on this system (there's 345 * always just one such driver in use - the kernel decides via an 346 * early probing process which one it picks - and then sticks to it): 347 */ 348 extern struct apic *apic; 349 350 /* 351 * APIC drivers are probed based on how they are listed in the .apicdrivers 352 * section. So the order is important and enforced by the ordering 353 * of different apic driver files in the Makefile. 354 * 355 * For the files having two apic drivers, we use apic_drivers() 356 * to enforce the order with in them. 357 */ 358 #define apic_driver(sym) \ 359 static const struct apic *__apicdrivers_##sym __used \ 360 __aligned(sizeof(struct apic *)) \ 361 __section(.apicdrivers) = { &sym } 362 363 #define apic_drivers(sym1, sym2) \ 364 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 365 __aligned(sizeof(struct apic *)) \ 366 __section(.apicdrivers) = { &sym1, &sym2 } 367 368 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 369 370 /* 371 * APIC functionality to boot other CPUs - only used on SMP: 372 */ 373 #ifdef CONFIG_SMP 374 extern atomic_t init_deasserted; 375 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 376 #endif 377 378 #ifdef CONFIG_X86_LOCAL_APIC 379 380 static inline u32 apic_read(u32 reg) 381 { 382 return apic->read(reg); 383 } 384 385 static inline void apic_write(u32 reg, u32 val) 386 { 387 apic->write(reg, val); 388 } 389 390 static inline void apic_eoi(void) 391 { 392 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 393 } 394 395 static inline u64 apic_icr_read(void) 396 { 397 return apic->icr_read(); 398 } 399 400 static inline void apic_icr_write(u32 low, u32 high) 401 { 402 apic->icr_write(low, high); 403 } 404 405 static inline void apic_wait_icr_idle(void) 406 { 407 apic->wait_icr_idle(); 408 } 409 410 static inline u32 safe_apic_wait_icr_idle(void) 411 { 412 return apic->safe_wait_icr_idle(); 413 } 414 415 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 416 417 #else /* CONFIG_X86_LOCAL_APIC */ 418 419 static inline u32 apic_read(u32 reg) { return 0; } 420 static inline void apic_write(u32 reg, u32 val) { } 421 static inline void apic_eoi(void) { } 422 static inline u64 apic_icr_read(void) { return 0; } 423 static inline void apic_icr_write(u32 low, u32 high) { } 424 static inline void apic_wait_icr_idle(void) { } 425 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 426 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 427 428 #endif /* CONFIG_X86_LOCAL_APIC */ 429 430 static inline void ack_APIC_irq(void) 431 { 432 /* 433 * ack_APIC_irq() actually gets compiled as a single instruction 434 * ... yummie. 435 */ 436 apic_eoi(); 437 } 438 439 static inline unsigned default_get_apic_id(unsigned long x) 440 { 441 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 442 443 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 444 return (x >> 24) & 0xFF; 445 else 446 return (x >> 24) & 0x0F; 447 } 448 449 /* 450 * Warm reset vector position: 451 */ 452 #define TRAMPOLINE_PHYS_LOW 0x467 453 #define TRAMPOLINE_PHYS_HIGH 0x469 454 455 #ifdef CONFIG_X86_64 456 extern void apic_send_IPI_self(int vector); 457 458 DECLARE_PER_CPU(int, x2apic_extra_bits); 459 460 extern int default_cpu_present_to_apicid(int mps_cpu); 461 extern int default_check_phys_apicid_present(int phys_apicid); 462 #endif 463 464 extern void generic_bigsmp_probe(void); 465 466 467 #ifdef CONFIG_X86_LOCAL_APIC 468 469 #include <asm/smp.h> 470 471 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 472 473 static inline const struct cpumask *default_target_cpus(void) 474 { 475 #ifdef CONFIG_SMP 476 return cpu_online_mask; 477 #else 478 return cpumask_of(0); 479 #endif 480 } 481 482 static inline const struct cpumask *online_target_cpus(void) 483 { 484 return cpu_online_mask; 485 } 486 487 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 488 489 490 static inline unsigned int read_apic_id(void) 491 { 492 unsigned int reg; 493 494 reg = apic_read(APIC_ID); 495 496 return apic->get_apic_id(reg); 497 } 498 499 static inline int default_apic_id_valid(int apicid) 500 { 501 return (apicid < 255); 502 } 503 504 extern int default_acpi_madt_oem_check(char *, char *); 505 506 extern void default_setup_apic_routing(void); 507 508 extern struct apic apic_noop; 509 510 #ifdef CONFIG_X86_32 511 512 static inline int noop_x86_32_early_logical_apicid(int cpu) 513 { 514 return BAD_APICID; 515 } 516 517 /* 518 * Set up the logical destination ID. 519 * 520 * Intel recommends to set DFR, LDR and TPR before enabling 521 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 522 * document number 292116). So here it goes... 523 */ 524 extern void default_init_apic_ldr(void); 525 526 static inline int default_apic_id_registered(void) 527 { 528 return physid_isset(read_apic_id(), phys_cpu_present_map); 529 } 530 531 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 532 { 533 return cpuid_apic >> index_msb; 534 } 535 536 #endif 537 538 static inline int 539 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 540 const struct cpumask *andmask, 541 unsigned int *apicid) 542 { 543 unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 544 cpumask_bits(andmask)[0] & 545 cpumask_bits(cpu_online_mask)[0] & 546 APIC_ALL_CPUS; 547 548 if (likely(cpu_mask)) { 549 *apicid = (unsigned int)cpu_mask; 550 return 0; 551 } else { 552 return -EINVAL; 553 } 554 } 555 556 extern int 557 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 558 const struct cpumask *andmask, 559 unsigned int *apicid); 560 561 static inline void 562 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 563 const struct cpumask *mask) 564 { 565 /* Careful. Some cpus do not strictly honor the set of cpus 566 * specified in the interrupt destination when using lowest 567 * priority interrupt delivery mode. 568 * 569 * In particular there was a hyperthreading cpu observed to 570 * deliver interrupts to the wrong hyperthread when only one 571 * hyperthread was specified in the interrupt desitination. 572 */ 573 cpumask_clear(retmask); 574 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 575 } 576 577 static inline void 578 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 579 const struct cpumask *mask) 580 { 581 cpumask_copy(retmask, cpumask_of(cpu)); 582 } 583 584 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 585 { 586 return physid_isset(apicid, *map); 587 } 588 589 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 590 { 591 *retmap = *phys_map; 592 } 593 594 static inline int __default_cpu_present_to_apicid(int mps_cpu) 595 { 596 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 597 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 598 else 599 return BAD_APICID; 600 } 601 602 static inline int 603 __default_check_phys_apicid_present(int phys_apicid) 604 { 605 return physid_isset(phys_apicid, phys_cpu_present_map); 606 } 607 608 #ifdef CONFIG_X86_32 609 static inline int default_cpu_present_to_apicid(int mps_cpu) 610 { 611 return __default_cpu_present_to_apicid(mps_cpu); 612 } 613 614 static inline int 615 default_check_phys_apicid_present(int phys_apicid) 616 { 617 return __default_check_phys_apicid_present(phys_apicid); 618 } 619 #else 620 extern int default_cpu_present_to_apicid(int mps_cpu); 621 extern int default_check_phys_apicid_present(int phys_apicid); 622 #endif 623 624 #endif /* CONFIG_X86_LOCAL_APIC */ 625 extern void irq_enter(void); 626 extern void irq_exit(void); 627 628 static inline void entering_irq(void) 629 { 630 irq_enter(); 631 exit_idle(); 632 } 633 634 static inline void entering_ack_irq(void) 635 { 636 ack_APIC_irq(); 637 entering_irq(); 638 } 639 640 static inline void exiting_irq(void) 641 { 642 irq_exit(); 643 } 644 645 static inline void exiting_ack_irq(void) 646 { 647 irq_exit(); 648 /* Ack only at the end to avoid potential reentry */ 649 ack_APIC_irq(); 650 } 651 652 extern void ioapic_zap_locks(void); 653 654 #endif /* _ASM_X86_APIC_H */ 655