1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/idle.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* 27 * Define the default level of output to be very little 28 * This can be turned up by using apic=verbose for more 29 * information and apic=debug for _lots_ of information. 30 * apic_verbosity is defined in apic.c 31 */ 32 #define apic_printk(v, s, a...) do { \ 33 if ((v) <= apic_verbosity) \ 34 printk(s, ##a); \ 35 } while (0) 36 37 38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39 extern void generic_apic_probe(void); 40 #else 41 static inline void generic_apic_probe(void) 42 { 43 } 44 #endif 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 48 extern unsigned int apic_verbosity; 49 extern int local_apic_timer_c2_ok; 50 51 extern int disable_apic; 52 extern unsigned int lapic_timer_frequency; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 extern int setup_profiling_timer(unsigned int); 89 90 static inline void native_apic_mem_write(u32 reg, u32 v) 91 { 92 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 93 94 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 95 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 96 ASM_OUTPUT2("0" (v), "m" (*addr))); 97 } 98 99 static inline u32 native_apic_mem_read(u32 reg) 100 { 101 return *((volatile u32 *)(APIC_BASE + reg)); 102 } 103 104 extern void native_apic_wait_icr_idle(void); 105 extern u32 native_safe_apic_wait_icr_idle(void); 106 extern void native_apic_icr_write(u32 low, u32 id); 107 extern u64 native_apic_icr_read(void); 108 109 extern int x2apic_mode; 110 111 #ifdef CONFIG_X86_X2APIC 112 /* 113 * Make previous memory operations globally visible before 114 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 115 * mfence for this. 116 */ 117 static inline void x2apic_wrmsr_fence(void) 118 { 119 asm volatile("mfence" : : : "memory"); 120 } 121 122 static inline void native_apic_msr_write(u32 reg, u32 v) 123 { 124 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 125 reg == APIC_LVR) 126 return; 127 128 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 129 } 130 131 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 132 { 133 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 134 } 135 136 static inline u32 native_apic_msr_read(u32 reg) 137 { 138 u64 msr; 139 140 if (reg == APIC_DFR) 141 return -1; 142 143 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 144 return (u32)msr; 145 } 146 147 static inline void native_x2apic_wait_icr_idle(void) 148 { 149 /* no need to wait for icr idle in x2apic */ 150 return; 151 } 152 153 static inline u32 native_safe_x2apic_wait_icr_idle(void) 154 { 155 /* no need to wait for icr idle in x2apic */ 156 return 0; 157 } 158 159 static inline void native_x2apic_icr_write(u32 low, u32 id) 160 { 161 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 162 } 163 164 static inline u64 native_x2apic_icr_read(void) 165 { 166 unsigned long val; 167 168 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 169 return val; 170 } 171 172 extern int x2apic_phys; 173 extern int x2apic_preenabled; 174 extern void check_x2apic(void); 175 extern void enable_x2apic(void); 176 static inline int x2apic_enabled(void) 177 { 178 u64 msr; 179 180 if (!cpu_has_x2apic) 181 return 0; 182 183 rdmsrl(MSR_IA32_APICBASE, msr); 184 if (msr & X2APIC_ENABLE) 185 return 1; 186 return 0; 187 } 188 189 #define x2apic_supported() (cpu_has_x2apic) 190 static inline void x2apic_force_phys(void) 191 { 192 x2apic_phys = 1; 193 } 194 #else 195 static inline void disable_x2apic(void) 196 { 197 } 198 static inline void check_x2apic(void) 199 { 200 } 201 static inline void enable_x2apic(void) 202 { 203 } 204 static inline int x2apic_enabled(void) 205 { 206 return 0; 207 } 208 static inline void x2apic_force_phys(void) 209 { 210 } 211 212 #define x2apic_preenabled 0 213 #define x2apic_supported() 0 214 #endif 215 216 extern void enable_IR_x2apic(void); 217 218 extern int get_physical_broadcast(void); 219 220 extern int lapic_get_maxlvt(void); 221 extern void clear_local_APIC(void); 222 extern void connect_bsp_APIC(void); 223 extern void disconnect_bsp_APIC(int virt_wire_setup); 224 extern void disable_local_APIC(void); 225 extern void lapic_shutdown(void); 226 extern int verify_local_APIC(void); 227 extern void sync_Arb_IDs(void); 228 extern void init_bsp_APIC(void); 229 extern void setup_local_APIC(void); 230 extern void end_local_APIC_setup(void); 231 extern void bsp_end_local_APIC_setup(void); 232 extern void init_apic_mappings(void); 233 void register_lapic_address(unsigned long address); 234 extern void setup_boot_APIC_clock(void); 235 extern void setup_secondary_APIC_clock(void); 236 extern int APIC_init_uniprocessor(void); 237 extern int apic_force_enable(unsigned long addr); 238 239 /* 240 * On 32bit this is mach-xxx local 241 */ 242 #ifdef CONFIG_X86_64 243 extern int apic_is_clustered_box(void); 244 #else 245 static inline int apic_is_clustered_box(void) 246 { 247 return 0; 248 } 249 #endif 250 251 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 252 253 #else /* !CONFIG_X86_LOCAL_APIC */ 254 static inline void lapic_shutdown(void) { } 255 #define local_apic_timer_c2_ok 1 256 static inline void init_apic_mappings(void) { } 257 static inline void disable_local_APIC(void) { } 258 # define setup_boot_APIC_clock x86_init_noop 259 # define setup_secondary_APIC_clock x86_init_noop 260 #endif /* !CONFIG_X86_LOCAL_APIC */ 261 262 #ifdef CONFIG_X86_64 263 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 264 #else 265 266 #endif 267 268 /* 269 * Copyright 2004 James Cleverdon, IBM. 270 * Subject to the GNU Public License, v.2 271 * 272 * Generic APIC sub-arch data struct. 273 * 274 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 275 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 276 * James Cleverdon. 277 */ 278 struct apic { 279 char *name; 280 281 int (*probe)(void); 282 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 283 int (*apic_id_valid)(int apicid); 284 int (*apic_id_registered)(void); 285 286 u32 irq_delivery_mode; 287 u32 irq_dest_mode; 288 289 const struct cpumask *(*target_cpus)(void); 290 291 int disable_esr; 292 293 int dest_logical; 294 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 295 unsigned long (*check_apicid_present)(int apicid); 296 297 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 298 const struct cpumask *mask); 299 void (*init_apic_ldr)(void); 300 301 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 302 303 void (*setup_apic_routing)(void); 304 int (*multi_timer_check)(int apic, int irq); 305 int (*cpu_present_to_apicid)(int mps_cpu); 306 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 307 void (*setup_portio_remap)(void); 308 int (*check_phys_apicid_present)(int phys_apicid); 309 void (*enable_apic_mode)(void); 310 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 311 312 /* 313 * When one of the next two hooks returns 1 the apic 314 * is switched to this. Essentially they are additional 315 * probe functions: 316 */ 317 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 318 319 unsigned int (*get_apic_id)(unsigned long x); 320 unsigned long (*set_apic_id)(unsigned int id); 321 unsigned long apic_id_mask; 322 323 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 324 const struct cpumask *andmask, 325 unsigned int *apicid); 326 327 /* ipi */ 328 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 329 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 330 int vector); 331 void (*send_IPI_allbutself)(int vector); 332 void (*send_IPI_all)(int vector); 333 void (*send_IPI_self)(int vector); 334 335 /* wakeup_secondary_cpu */ 336 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 337 338 bool wait_for_init_deassert; 339 void (*inquire_remote_apic)(int apicid); 340 341 /* apic ops */ 342 u32 (*read)(u32 reg); 343 void (*write)(u32 reg, u32 v); 344 /* 345 * ->eoi_write() has the same signature as ->write(). 346 * 347 * Drivers can support both ->eoi_write() and ->write() by passing the same 348 * callback value. Kernel can override ->eoi_write() and fall back 349 * on write for EOI. 350 */ 351 void (*eoi_write)(u32 reg, u32 v); 352 u64 (*icr_read)(void); 353 void (*icr_write)(u32 low, u32 high); 354 void (*wait_icr_idle)(void); 355 u32 (*safe_wait_icr_idle)(void); 356 357 #ifdef CONFIG_X86_32 358 /* 359 * Called very early during boot from get_smp_config(). It should 360 * return the logical apicid. x86_[bios]_cpu_to_apicid is 361 * initialized before this function is called. 362 * 363 * If logical apicid can't be determined that early, the function 364 * may return BAD_APICID. Logical apicid will be configured after 365 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 366 * won't be applied properly during early boot in this case. 367 */ 368 int (*x86_32_early_logical_apicid)(int cpu); 369 #endif 370 }; 371 372 /* 373 * Pointer to the local APIC driver in use on this system (there's 374 * always just one such driver in use - the kernel decides via an 375 * early probing process which one it picks - and then sticks to it): 376 */ 377 extern struct apic *apic; 378 379 /* 380 * APIC drivers are probed based on how they are listed in the .apicdrivers 381 * section. So the order is important and enforced by the ordering 382 * of different apic driver files in the Makefile. 383 * 384 * For the files having two apic drivers, we use apic_drivers() 385 * to enforce the order with in them. 386 */ 387 #define apic_driver(sym) \ 388 static const struct apic *__apicdrivers_##sym __used \ 389 __aligned(sizeof(struct apic *)) \ 390 __section(.apicdrivers) = { &sym } 391 392 #define apic_drivers(sym1, sym2) \ 393 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 394 __aligned(sizeof(struct apic *)) \ 395 __section(.apicdrivers) = { &sym1, &sym2 } 396 397 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 398 399 /* 400 * APIC functionality to boot other CPUs - only used on SMP: 401 */ 402 #ifdef CONFIG_SMP 403 extern atomic_t init_deasserted; 404 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 405 #endif 406 407 #ifdef CONFIG_X86_LOCAL_APIC 408 409 static inline u32 apic_read(u32 reg) 410 { 411 return apic->read(reg); 412 } 413 414 static inline void apic_write(u32 reg, u32 val) 415 { 416 apic->write(reg, val); 417 } 418 419 static inline void apic_eoi(void) 420 { 421 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 422 } 423 424 static inline u64 apic_icr_read(void) 425 { 426 return apic->icr_read(); 427 } 428 429 static inline void apic_icr_write(u32 low, u32 high) 430 { 431 apic->icr_write(low, high); 432 } 433 434 static inline void apic_wait_icr_idle(void) 435 { 436 apic->wait_icr_idle(); 437 } 438 439 static inline u32 safe_apic_wait_icr_idle(void) 440 { 441 return apic->safe_wait_icr_idle(); 442 } 443 444 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 445 446 #else /* CONFIG_X86_LOCAL_APIC */ 447 448 static inline u32 apic_read(u32 reg) { return 0; } 449 static inline void apic_write(u32 reg, u32 val) { } 450 static inline void apic_eoi(void) { } 451 static inline u64 apic_icr_read(void) { return 0; } 452 static inline void apic_icr_write(u32 low, u32 high) { } 453 static inline void apic_wait_icr_idle(void) { } 454 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 455 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 456 457 #endif /* CONFIG_X86_LOCAL_APIC */ 458 459 static inline void ack_APIC_irq(void) 460 { 461 /* 462 * ack_APIC_irq() actually gets compiled as a single instruction 463 * ... yummie. 464 */ 465 apic_eoi(); 466 } 467 468 static inline unsigned default_get_apic_id(unsigned long x) 469 { 470 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 471 472 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 473 return (x >> 24) & 0xFF; 474 else 475 return (x >> 24) & 0x0F; 476 } 477 478 /* 479 * Warm reset vector position: 480 */ 481 #define TRAMPOLINE_PHYS_LOW 0x467 482 #define TRAMPOLINE_PHYS_HIGH 0x469 483 484 #ifdef CONFIG_X86_64 485 extern void apic_send_IPI_self(int vector); 486 487 DECLARE_PER_CPU(int, x2apic_extra_bits); 488 489 extern int default_cpu_present_to_apicid(int mps_cpu); 490 extern int default_check_phys_apicid_present(int phys_apicid); 491 #endif 492 493 extern void generic_bigsmp_probe(void); 494 495 496 #ifdef CONFIG_X86_LOCAL_APIC 497 498 #include <asm/smp.h> 499 500 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 501 502 static inline const struct cpumask *default_target_cpus(void) 503 { 504 #ifdef CONFIG_SMP 505 return cpu_online_mask; 506 #else 507 return cpumask_of(0); 508 #endif 509 } 510 511 static inline const struct cpumask *online_target_cpus(void) 512 { 513 return cpu_online_mask; 514 } 515 516 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 517 518 519 static inline unsigned int read_apic_id(void) 520 { 521 unsigned int reg; 522 523 reg = apic_read(APIC_ID); 524 525 return apic->get_apic_id(reg); 526 } 527 528 static inline int default_apic_id_valid(int apicid) 529 { 530 return (apicid < 255); 531 } 532 533 extern int default_acpi_madt_oem_check(char *, char *); 534 535 extern void default_setup_apic_routing(void); 536 537 extern struct apic apic_noop; 538 539 #ifdef CONFIG_X86_32 540 541 static inline int noop_x86_32_early_logical_apicid(int cpu) 542 { 543 return BAD_APICID; 544 } 545 546 /* 547 * Set up the logical destination ID. 548 * 549 * Intel recommends to set DFR, LDR and TPR before enabling 550 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 551 * document number 292116). So here it goes... 552 */ 553 extern void default_init_apic_ldr(void); 554 555 static inline int default_apic_id_registered(void) 556 { 557 return physid_isset(read_apic_id(), phys_cpu_present_map); 558 } 559 560 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 561 { 562 return cpuid_apic >> index_msb; 563 } 564 565 #endif 566 567 static inline int 568 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 569 const struct cpumask *andmask, 570 unsigned int *apicid) 571 { 572 unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 573 cpumask_bits(andmask)[0] & 574 cpumask_bits(cpu_online_mask)[0] & 575 APIC_ALL_CPUS; 576 577 if (likely(cpu_mask)) { 578 *apicid = (unsigned int)cpu_mask; 579 return 0; 580 } else { 581 return -EINVAL; 582 } 583 } 584 585 extern int 586 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 587 const struct cpumask *andmask, 588 unsigned int *apicid); 589 590 static inline void 591 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 592 const struct cpumask *mask) 593 { 594 /* Careful. Some cpus do not strictly honor the set of cpus 595 * specified in the interrupt destination when using lowest 596 * priority interrupt delivery mode. 597 * 598 * In particular there was a hyperthreading cpu observed to 599 * deliver interrupts to the wrong hyperthread when only one 600 * hyperthread was specified in the interrupt desitination. 601 */ 602 cpumask_clear(retmask); 603 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 604 } 605 606 static inline void 607 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 608 const struct cpumask *mask) 609 { 610 cpumask_copy(retmask, cpumask_of(cpu)); 611 } 612 613 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 614 { 615 return physid_isset(apicid, *map); 616 } 617 618 static inline unsigned long default_check_apicid_present(int bit) 619 { 620 return physid_isset(bit, phys_cpu_present_map); 621 } 622 623 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 624 { 625 *retmap = *phys_map; 626 } 627 628 static inline int __default_cpu_present_to_apicid(int mps_cpu) 629 { 630 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 631 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 632 else 633 return BAD_APICID; 634 } 635 636 static inline int 637 __default_check_phys_apicid_present(int phys_apicid) 638 { 639 return physid_isset(phys_apicid, phys_cpu_present_map); 640 } 641 642 #ifdef CONFIG_X86_32 643 static inline int default_cpu_present_to_apicid(int mps_cpu) 644 { 645 return __default_cpu_present_to_apicid(mps_cpu); 646 } 647 648 static inline int 649 default_check_phys_apicid_present(int phys_apicid) 650 { 651 return __default_check_phys_apicid_present(phys_apicid); 652 } 653 #else 654 extern int default_cpu_present_to_apicid(int mps_cpu); 655 extern int default_check_phys_apicid_present(int phys_apicid); 656 #endif 657 658 #endif /* CONFIG_X86_LOCAL_APIC */ 659 extern void irq_enter(void); 660 extern void irq_exit(void); 661 662 static inline void entering_irq(void) 663 { 664 irq_enter(); 665 exit_idle(); 666 } 667 668 static inline void entering_ack_irq(void) 669 { 670 ack_APIC_irq(); 671 entering_irq(); 672 } 673 674 static inline void exiting_irq(void) 675 { 676 irq_exit(); 677 } 678 679 static inline void exiting_ack_irq(void) 680 { 681 irq_exit(); 682 /* Ack only at the end to avoid potential reentry */ 683 ack_APIC_irq(); 684 } 685 686 extern void ioapic_zap_locks(void); 687 688 #endif /* _ASM_X86_APIC_H */ 689