1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 #include <linux/static_call.h> 7 8 #include <asm/alternative.h> 9 #include <asm/cpufeature.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/hardirq.h> 16 #include <asm/io.h> 17 18 #define ARCH_APICTIMER_STOPS_ON_C3 1 19 20 /* 21 * Debugging macros 22 */ 23 #define APIC_QUIET 0 24 #define APIC_VERBOSE 1 25 #define APIC_DEBUG 2 26 27 /* Macros for apic_extnmi which controls external NMI masking */ 28 #define APIC_EXTNMI_BSP 0 /* Default */ 29 #define APIC_EXTNMI_ALL 1 30 #define APIC_EXTNMI_NONE 2 31 32 /* 33 * Define the default level of output to be very little 34 * This can be turned up by using apic=verbose for more 35 * information and apic=debug for _lots_ of information. 36 * apic_verbosity is defined in apic.c 37 */ 38 #define apic_printk(v, s, a...) do { \ 39 if ((v) <= apic_verbosity) \ 40 printk(s, ##a); \ 41 } while (0) 42 43 44 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 45 extern void x86_32_probe_apic(void); 46 #else 47 static inline void x86_32_probe_apic(void) { } 48 #endif 49 50 #ifdef CONFIG_X86_LOCAL_APIC 51 52 extern int apic_verbosity; 53 extern int local_apic_timer_c2_ok; 54 55 extern bool apic_is_disabled; 56 extern unsigned int lapic_timer_period; 57 58 extern int cpuid_to_apicid[]; 59 60 extern enum apic_intr_mode_id apic_intr_mode; 61 enum apic_intr_mode_id { 62 APIC_PIC, 63 APIC_VIRTUAL_WIRE, 64 APIC_VIRTUAL_WIRE_NO_CONFIG, 65 APIC_SYMMETRIC_IO, 66 APIC_SYMMETRIC_IO_NO_ROUTING 67 }; 68 69 /* 70 * With 82489DX we can't rely on apic feature bit 71 * retrieved via cpuid but still have to deal with 72 * such an apic chip so we assume that SMP configuration 73 * is found from MP table (64bit case uses ACPI mostly 74 * which set smp presence flag as well so we are safe 75 * to use this helper too). 76 */ 77 static inline bool apic_from_smp_config(void) 78 { 79 return smp_found_config && !apic_is_disabled; 80 } 81 82 /* 83 * Basic functions accessing APICs. 84 */ 85 #ifdef CONFIG_PARAVIRT 86 #include <asm/paravirt.h> 87 #endif 88 89 static inline void native_apic_mem_write(u32 reg, u32 v) 90 { 91 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 92 93 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 94 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 95 ASM_OUTPUT2("0" (v), "m" (*addr))); 96 } 97 98 static inline u32 native_apic_mem_read(u32 reg) 99 { 100 return readl((void __iomem *)(APIC_BASE + reg)); 101 } 102 103 static inline void native_apic_mem_eoi(void) 104 { 105 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK); 106 } 107 108 extern void native_apic_icr_write(u32 low, u32 id); 109 extern u64 native_apic_icr_read(void); 110 111 static inline bool apic_is_x2apic_enabled(void) 112 { 113 u64 msr; 114 115 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 116 return false; 117 return msr & X2APIC_ENABLE; 118 } 119 120 extern void enable_IR_x2apic(void); 121 122 extern int get_physical_broadcast(void); 123 124 extern int lapic_get_maxlvt(void); 125 extern void clear_local_APIC(void); 126 extern void disconnect_bsp_APIC(int virt_wire_setup); 127 extern void disable_local_APIC(void); 128 extern void apic_soft_disable(void); 129 extern void lapic_shutdown(void); 130 extern void sync_Arb_IDs(void); 131 extern void init_bsp_APIC(void); 132 extern void apic_intr_mode_select(void); 133 extern void apic_intr_mode_init(void); 134 extern void init_apic_mappings(void); 135 void register_lapic_address(unsigned long address); 136 extern void setup_boot_APIC_clock(void); 137 extern void setup_secondary_APIC_clock(void); 138 extern void lapic_update_tsc_freq(void); 139 140 #ifdef CONFIG_X86_64 141 static inline bool apic_force_enable(unsigned long addr) 142 { 143 return false; 144 } 145 #else 146 extern bool apic_force_enable(unsigned long addr); 147 #endif 148 149 extern void apic_ap_setup(void); 150 151 /* 152 * On 32bit this is mach-xxx local 153 */ 154 #ifdef CONFIG_X86_64 155 extern int apic_is_clustered_box(void); 156 #else 157 static inline int apic_is_clustered_box(void) 158 { 159 return 0; 160 } 161 #endif 162 163 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 164 extern void lapic_assign_system_vectors(void); 165 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 166 extern void lapic_update_legacy_vectors(void); 167 extern void lapic_online(void); 168 extern void lapic_offline(void); 169 extern bool apic_needs_pit(void); 170 171 extern void apic_send_IPI_allbutself(unsigned int vector); 172 173 #else /* !CONFIG_X86_LOCAL_APIC */ 174 static inline void lapic_shutdown(void) { } 175 #define local_apic_timer_c2_ok 1 176 static inline void init_apic_mappings(void) { } 177 static inline void disable_local_APIC(void) { } 178 # define setup_boot_APIC_clock x86_init_noop 179 # define setup_secondary_APIC_clock x86_init_noop 180 static inline void lapic_update_tsc_freq(void) { } 181 static inline void init_bsp_APIC(void) { } 182 static inline void apic_intr_mode_select(void) { } 183 static inline void apic_intr_mode_init(void) { } 184 static inline void lapic_assign_system_vectors(void) { } 185 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 186 static inline bool apic_needs_pit(void) { return true; } 187 #endif /* !CONFIG_X86_LOCAL_APIC */ 188 189 #ifdef CONFIG_X86_X2APIC 190 static inline void native_apic_msr_write(u32 reg, u32 v) 191 { 192 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 193 reg == APIC_LVR) 194 return; 195 196 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 197 } 198 199 static inline void native_apic_msr_eoi(void) 200 { 201 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 202 } 203 204 static inline u32 native_apic_msr_read(u32 reg) 205 { 206 u64 msr; 207 208 if (reg == APIC_DFR) 209 return -1; 210 211 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 212 return (u32)msr; 213 } 214 215 static inline void native_x2apic_icr_write(u32 low, u32 id) 216 { 217 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 218 } 219 220 static inline u64 native_x2apic_icr_read(void) 221 { 222 unsigned long val; 223 224 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 225 return val; 226 } 227 228 extern int x2apic_mode; 229 extern int x2apic_phys; 230 extern void __init x2apic_set_max_apicid(u32 apicid); 231 extern void x2apic_setup(void); 232 static inline int x2apic_enabled(void) 233 { 234 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 235 } 236 237 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 238 #else /* !CONFIG_X86_X2APIC */ 239 static inline void x2apic_setup(void) { } 240 static inline int x2apic_enabled(void) { return 0; } 241 static inline u32 native_apic_msr_read(u32 reg) { BUG(); } 242 #define x2apic_mode (0) 243 #define x2apic_supported() (0) 244 #endif /* !CONFIG_X86_X2APIC */ 245 extern void __init check_x2apic(void); 246 247 struct irq_data; 248 249 /* 250 * Copyright 2004 James Cleverdon, IBM. 251 * 252 * Generic APIC sub-arch data struct. 253 * 254 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 255 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 256 * James Cleverdon. 257 */ 258 struct apic { 259 /* Hotpath functions first */ 260 void (*eoi)(void); 261 void (*native_eoi)(void); 262 void (*write)(u32 reg, u32 v); 263 u32 (*read)(u32 reg); 264 265 /* IPI related functions */ 266 void (*wait_icr_idle)(void); 267 u32 (*safe_wait_icr_idle)(void); 268 269 void (*send_IPI)(int cpu, int vector); 270 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 271 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 272 void (*send_IPI_allbutself)(int vector); 273 void (*send_IPI_all)(int vector); 274 void (*send_IPI_self)(int vector); 275 276 enum apic_delivery_modes delivery_mode; 277 278 u32 disable_esr : 1, 279 dest_mode_logical : 1, 280 x2apic_set_max_apicid : 1; 281 282 u32 (*calc_dest_apicid)(unsigned int cpu); 283 284 /* ICR related functions */ 285 u64 (*icr_read)(void); 286 void (*icr_write)(u32 low, u32 high); 287 288 /* The limit of the APIC ID space. */ 289 u32 max_apic_id; 290 291 /* Probe, setup and smpboot functions */ 292 int (*probe)(void); 293 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 294 bool (*apic_id_registered)(void); 295 296 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 297 void (*init_apic_ldr)(void); 298 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 299 int (*cpu_present_to_apicid)(int mps_cpu); 300 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 301 302 u32 (*get_apic_id)(unsigned long x); 303 u32 (*set_apic_id)(unsigned int id); 304 305 /* wakeup_secondary_cpu */ 306 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 307 /* wakeup secondary CPU using 64-bit wakeup point */ 308 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); 309 310 char *name; 311 }; 312 313 struct apic_override { 314 void (*eoi)(void); 315 void (*native_eoi)(void); 316 void (*write)(u32 reg, u32 v); 317 u32 (*read)(u32 reg); 318 void (*send_IPI)(int cpu, int vector); 319 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 320 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 321 void (*send_IPI_allbutself)(int vector); 322 void (*send_IPI_all)(int vector); 323 void (*send_IPI_self)(int vector); 324 u64 (*icr_read)(void); 325 void (*icr_write)(u32 low, u32 high); 326 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 327 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); 328 }; 329 330 /* 331 * Pointer to the local APIC driver in use on this system (there's 332 * always just one such driver in use - the kernel decides via an 333 * early probing process which one it picks - and then sticks to it): 334 */ 335 extern struct apic *apic; 336 337 /* 338 * APIC drivers are probed based on how they are listed in the .apicdrivers 339 * section. So the order is important and enforced by the ordering 340 * of different apic driver files in the Makefile. 341 * 342 * For the files having two apic drivers, we use apic_drivers() 343 * to enforce the order with in them. 344 */ 345 #define apic_driver(sym) \ 346 static const struct apic *__apicdrivers_##sym __used \ 347 __aligned(sizeof(struct apic *)) \ 348 __section(".apicdrivers") = { &sym } 349 350 #define apic_drivers(sym1, sym2) \ 351 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 352 __aligned(sizeof(struct apic *)) \ 353 __section(".apicdrivers") = { &sym1, &sym2 } 354 355 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 356 357 /* 358 * APIC functionality to boot other CPUs - only used on SMP: 359 */ 360 #ifdef CONFIG_SMP 361 extern int lapic_can_unplug_cpu(void); 362 #endif 363 364 #ifdef CONFIG_X86_LOCAL_APIC 365 extern struct apic_override __x86_apic_override; 366 367 void __init apic_setup_apic_calls(void); 368 void __init apic_install_driver(struct apic *driver); 369 370 #define apic_update_callback(_callback, _fn) { \ 371 __x86_apic_override._callback = _fn; \ 372 apic->_callback = _fn; \ 373 static_call_update(apic_call_##_callback, _fn); \ 374 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \ 375 } 376 377 #define DECLARE_APIC_CALL(__cb) \ 378 DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb) 379 380 DECLARE_APIC_CALL(eoi); 381 DECLARE_APIC_CALL(native_eoi); 382 DECLARE_APIC_CALL(icr_read); 383 DECLARE_APIC_CALL(icr_write); 384 DECLARE_APIC_CALL(read); 385 DECLARE_APIC_CALL(send_IPI); 386 DECLARE_APIC_CALL(send_IPI_mask); 387 DECLARE_APIC_CALL(send_IPI_mask_allbutself); 388 DECLARE_APIC_CALL(send_IPI_allbutself); 389 DECLARE_APIC_CALL(send_IPI_all); 390 DECLARE_APIC_CALL(send_IPI_self); 391 DECLARE_APIC_CALL(wait_icr_idle); 392 DECLARE_APIC_CALL(wakeup_secondary_cpu); 393 DECLARE_APIC_CALL(wakeup_secondary_cpu_64); 394 DECLARE_APIC_CALL(write); 395 396 static __always_inline u32 apic_read(u32 reg) 397 { 398 return static_call(apic_call_read)(reg); 399 } 400 401 static __always_inline void apic_write(u32 reg, u32 val) 402 { 403 static_call(apic_call_write)(reg, val); 404 } 405 406 static __always_inline void apic_eoi(void) 407 { 408 static_call(apic_call_eoi)(); 409 } 410 411 static __always_inline void apic_native_eoi(void) 412 { 413 static_call(apic_call_native_eoi)(); 414 } 415 416 static __always_inline u64 apic_icr_read(void) 417 { 418 return static_call(apic_call_icr_read)(); 419 } 420 421 static __always_inline void apic_icr_write(u32 low, u32 high) 422 { 423 static_call(apic_call_icr_write)(low, high); 424 } 425 426 static __always_inline void __apic_send_IPI(int cpu, int vector) 427 { 428 static_call(apic_call_send_IPI)(cpu, vector); 429 } 430 431 static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector) 432 { 433 static_call_mod(apic_call_send_IPI_mask)(mask, vector); 434 } 435 436 static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 437 { 438 static_call(apic_call_send_IPI_mask_allbutself)(mask, vector); 439 } 440 441 static __always_inline void __apic_send_IPI_allbutself(int vector) 442 { 443 static_call(apic_call_send_IPI_allbutself)(vector); 444 } 445 446 static __always_inline void __apic_send_IPI_all(int vector) 447 { 448 static_call(apic_call_send_IPI_all)(vector); 449 } 450 451 static __always_inline void __apic_send_IPI_self(int vector) 452 { 453 static_call_mod(apic_call_send_IPI_self)(vector); 454 } 455 456 static __always_inline void apic_wait_icr_idle(void) 457 { 458 static_call_cond(apic_call_wait_icr_idle)(); 459 } 460 461 static __always_inline u32 safe_apic_wait_icr_idle(void) 462 { 463 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; 464 } 465 466 static __always_inline bool apic_id_valid(u32 apic_id) 467 { 468 return apic_id <= apic->max_apic_id; 469 } 470 471 #else /* CONFIG_X86_LOCAL_APIC */ 472 473 static inline u32 apic_read(u32 reg) { return 0; } 474 static inline void apic_write(u32 reg, u32 val) { } 475 static inline void apic_eoi(void) { } 476 static inline u64 apic_icr_read(void) { return 0; } 477 static inline void apic_icr_write(u32 low, u32 high) { } 478 static inline void apic_wait_icr_idle(void) { } 479 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 480 static inline void apic_set_eoi_cb(void (*eoi)(void)) {} 481 static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } 482 static inline void apic_setup_apic_calls(void) { } 483 484 #define apic_update_callback(_callback, _fn) do { } while (0) 485 486 #endif /* CONFIG_X86_LOCAL_APIC */ 487 488 extern void apic_ack_irq(struct irq_data *data); 489 490 static inline bool lapic_vector_set_in_irr(unsigned int vector) 491 { 492 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 493 494 return !!(irr & (1U << (vector % 32))); 495 } 496 497 static inline unsigned default_get_apic_id(unsigned long x) 498 { 499 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 500 501 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 502 return (x >> 24) & 0xFF; 503 else 504 return (x >> 24) & 0x0F; 505 } 506 507 /* 508 * Warm reset vector position: 509 */ 510 #define TRAMPOLINE_PHYS_LOW 0x467 511 #define TRAMPOLINE_PHYS_HIGH 0x469 512 513 extern void generic_bigsmp_probe(void); 514 515 #ifdef CONFIG_X86_LOCAL_APIC 516 517 #include <asm/smp.h> 518 519 extern struct apic apic_noop; 520 521 static inline unsigned int read_apic_id(void) 522 { 523 unsigned int reg = apic_read(APIC_ID); 524 525 return apic->get_apic_id(reg); 526 } 527 528 #ifdef CONFIG_X86_64 529 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 530 extern int default_acpi_madt_oem_check(char *, char *); 531 extern void x86_64_probe_apic(void); 532 #else 533 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } 534 static inline void x86_64_probe_apic(void) { } 535 #endif 536 537 extern int default_apic_id_valid(u32 apicid); 538 539 extern u32 apic_default_calc_apicid(unsigned int cpu); 540 extern u32 apic_flat_calc_apicid(unsigned int cpu); 541 542 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 543 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 544 extern int default_cpu_present_to_apicid(int mps_cpu); 545 546 #else /* CONFIG_X86_LOCAL_APIC */ 547 548 static inline unsigned int read_apic_id(void) { return 0; } 549 550 #endif /* !CONFIG_X86_LOCAL_APIC */ 551 552 #ifdef CONFIG_SMP 553 void apic_smt_update(void); 554 #else 555 static inline void apic_smt_update(void) { } 556 #endif 557 558 struct msi_msg; 559 struct irq_cfg; 560 561 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 562 bool dmar); 563 564 extern void ioapic_zap_locks(void); 565 566 #endif /* _ASM_X86_APIC_H */ 567