1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/idle.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* 27 * Define the default level of output to be very little 28 * This can be turned up by using apic=verbose for more 29 * information and apic=debug for _lots_ of information. 30 * apic_verbosity is defined in apic.c 31 */ 32 #define apic_printk(v, s, a...) do { \ 33 if ((v) <= apic_verbosity) \ 34 printk(s, ##a); \ 35 } while (0) 36 37 38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39 extern void generic_apic_probe(void); 40 #else 41 static inline void generic_apic_probe(void) 42 { 43 } 44 #endif 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 48 extern unsigned int apic_verbosity; 49 extern int local_apic_timer_c2_ok; 50 51 extern int disable_apic; 52 extern unsigned int lapic_timer_frequency; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 #ifdef CONFIG_X86_64 89 extern int is_vsmp_box(void); 90 #else 91 static inline int is_vsmp_box(void) 92 { 93 return 0; 94 } 95 #endif 96 extern void xapic_wait_icr_idle(void); 97 extern u32 safe_xapic_wait_icr_idle(void); 98 extern void xapic_icr_write(u32, u32); 99 extern int setup_profiling_timer(unsigned int); 100 101 static inline void native_apic_mem_write(u32 reg, u32 v) 102 { 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108 } 109 110 static inline u32 native_apic_mem_read(u32 reg) 111 { 112 return *((volatile u32 *)(APIC_BASE + reg)); 113 } 114 115 extern void native_apic_wait_icr_idle(void); 116 extern u32 native_safe_apic_wait_icr_idle(void); 117 extern void native_apic_icr_write(u32 low, u32 id); 118 extern u64 native_apic_icr_read(void); 119 120 extern int x2apic_mode; 121 122 #ifdef CONFIG_X86_X2APIC 123 /* 124 * Make previous memory operations globally visible before 125 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 126 * mfence for this. 127 */ 128 static inline void x2apic_wrmsr_fence(void) 129 { 130 asm volatile("mfence" : : : "memory"); 131 } 132 133 static inline void native_apic_msr_write(u32 reg, u32 v) 134 { 135 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 136 reg == APIC_LVR) 137 return; 138 139 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 140 } 141 142 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 143 { 144 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 145 } 146 147 static inline u32 native_apic_msr_read(u32 reg) 148 { 149 u64 msr; 150 151 if (reg == APIC_DFR) 152 return -1; 153 154 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 155 return (u32)msr; 156 } 157 158 static inline void native_x2apic_wait_icr_idle(void) 159 { 160 /* no need to wait for icr idle in x2apic */ 161 return; 162 } 163 164 static inline u32 native_safe_x2apic_wait_icr_idle(void) 165 { 166 /* no need to wait for icr idle in x2apic */ 167 return 0; 168 } 169 170 static inline void native_x2apic_icr_write(u32 low, u32 id) 171 { 172 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 173 } 174 175 static inline u64 native_x2apic_icr_read(void) 176 { 177 unsigned long val; 178 179 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 180 return val; 181 } 182 183 extern int x2apic_phys; 184 extern int x2apic_preenabled; 185 extern void check_x2apic(void); 186 extern void enable_x2apic(void); 187 extern void x2apic_icr_write(u32 low, u32 id); 188 static inline int x2apic_enabled(void) 189 { 190 u64 msr; 191 192 if (!cpu_has_x2apic) 193 return 0; 194 195 rdmsrl(MSR_IA32_APICBASE, msr); 196 if (msr & X2APIC_ENABLE) 197 return 1; 198 return 0; 199 } 200 201 #define x2apic_supported() (cpu_has_x2apic) 202 static inline void x2apic_force_phys(void) 203 { 204 x2apic_phys = 1; 205 } 206 #else 207 static inline void disable_x2apic(void) 208 { 209 } 210 static inline void check_x2apic(void) 211 { 212 } 213 static inline void enable_x2apic(void) 214 { 215 } 216 static inline int x2apic_enabled(void) 217 { 218 return 0; 219 } 220 static inline void x2apic_force_phys(void) 221 { 222 } 223 224 #define nox2apic 0 225 #define x2apic_preenabled 0 226 #define x2apic_supported() 0 227 #endif 228 229 extern void enable_IR_x2apic(void); 230 231 extern int get_physical_broadcast(void); 232 233 extern int lapic_get_maxlvt(void); 234 extern void clear_local_APIC(void); 235 extern void connect_bsp_APIC(void); 236 extern void disconnect_bsp_APIC(int virt_wire_setup); 237 extern void disable_local_APIC(void); 238 extern void lapic_shutdown(void); 239 extern int verify_local_APIC(void); 240 extern void sync_Arb_IDs(void); 241 extern void init_bsp_APIC(void); 242 extern void setup_local_APIC(void); 243 extern void end_local_APIC_setup(void); 244 extern void bsp_end_local_APIC_setup(void); 245 extern void init_apic_mappings(void); 246 void register_lapic_address(unsigned long address); 247 extern void setup_boot_APIC_clock(void); 248 extern void setup_secondary_APIC_clock(void); 249 extern int APIC_init_uniprocessor(void); 250 extern int apic_force_enable(unsigned long addr); 251 252 /* 253 * On 32bit this is mach-xxx local 254 */ 255 #ifdef CONFIG_X86_64 256 extern int apic_is_clustered_box(void); 257 #else 258 static inline int apic_is_clustered_box(void) 259 { 260 return 0; 261 } 262 #endif 263 264 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 265 266 #else /* !CONFIG_X86_LOCAL_APIC */ 267 static inline void lapic_shutdown(void) { } 268 #define local_apic_timer_c2_ok 1 269 static inline void init_apic_mappings(void) { } 270 static inline void disable_local_APIC(void) { } 271 # define setup_boot_APIC_clock x86_init_noop 272 # define setup_secondary_APIC_clock x86_init_noop 273 #endif /* !CONFIG_X86_LOCAL_APIC */ 274 275 #ifdef CONFIG_X86_64 276 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 277 #else 278 279 #endif 280 281 /* 282 * Copyright 2004 James Cleverdon, IBM. 283 * Subject to the GNU Public License, v.2 284 * 285 * Generic APIC sub-arch data struct. 286 * 287 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 288 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 289 * James Cleverdon. 290 */ 291 struct apic { 292 char *name; 293 294 int (*probe)(void); 295 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 296 int (*apic_id_valid)(int apicid); 297 int (*apic_id_registered)(void); 298 299 u32 irq_delivery_mode; 300 u32 irq_dest_mode; 301 302 const struct cpumask *(*target_cpus)(void); 303 304 int disable_esr; 305 306 int dest_logical; 307 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 308 unsigned long (*check_apicid_present)(int apicid); 309 310 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 311 const struct cpumask *mask); 312 void (*init_apic_ldr)(void); 313 314 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 315 316 void (*setup_apic_routing)(void); 317 int (*multi_timer_check)(int apic, int irq); 318 int (*cpu_present_to_apicid)(int mps_cpu); 319 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 320 void (*setup_portio_remap)(void); 321 int (*check_phys_apicid_present)(int phys_apicid); 322 void (*enable_apic_mode)(void); 323 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 324 325 /* 326 * When one of the next two hooks returns 1 the apic 327 * is switched to this. Essentially they are additional 328 * probe functions: 329 */ 330 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 331 332 unsigned int (*get_apic_id)(unsigned long x); 333 unsigned long (*set_apic_id)(unsigned int id); 334 unsigned long apic_id_mask; 335 336 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 337 const struct cpumask *andmask, 338 unsigned int *apicid); 339 340 /* ipi */ 341 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 342 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 343 int vector); 344 void (*send_IPI_allbutself)(int vector); 345 void (*send_IPI_all)(int vector); 346 void (*send_IPI_self)(int vector); 347 348 /* wakeup_secondary_cpu */ 349 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 350 351 int trampoline_phys_low; 352 int trampoline_phys_high; 353 354 void (*wait_for_init_deassert)(atomic_t *deassert); 355 void (*smp_callin_clear_local_apic)(void); 356 void (*inquire_remote_apic)(int apicid); 357 358 /* apic ops */ 359 u32 (*read)(u32 reg); 360 void (*write)(u32 reg, u32 v); 361 /* 362 * ->eoi_write() has the same signature as ->write(). 363 * 364 * Drivers can support both ->eoi_write() and ->write() by passing the same 365 * callback value. Kernel can override ->eoi_write() and fall back 366 * on write for EOI. 367 */ 368 void (*eoi_write)(u32 reg, u32 v); 369 u64 (*icr_read)(void); 370 void (*icr_write)(u32 low, u32 high); 371 void (*wait_icr_idle)(void); 372 u32 (*safe_wait_icr_idle)(void); 373 374 #ifdef CONFIG_X86_32 375 /* 376 * Called very early during boot from get_smp_config(). It should 377 * return the logical apicid. x86_[bios]_cpu_to_apicid is 378 * initialized before this function is called. 379 * 380 * If logical apicid can't be determined that early, the function 381 * may return BAD_APICID. Logical apicid will be configured after 382 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 383 * won't be applied properly during early boot in this case. 384 */ 385 int (*x86_32_early_logical_apicid)(int cpu); 386 387 /* 388 * Optional method called from setup_local_APIC() after logical 389 * apicid is guaranteed to be known to initialize apicid -> node 390 * mapping if NUMA initialization hasn't done so already. Don't 391 * add new users. 392 */ 393 int (*x86_32_numa_cpu_node)(int cpu); 394 #endif 395 }; 396 397 /* 398 * Pointer to the local APIC driver in use on this system (there's 399 * always just one such driver in use - the kernel decides via an 400 * early probing process which one it picks - and then sticks to it): 401 */ 402 extern struct apic *apic; 403 404 /* 405 * APIC drivers are probed based on how they are listed in the .apicdrivers 406 * section. So the order is important and enforced by the ordering 407 * of different apic driver files in the Makefile. 408 * 409 * For the files having two apic drivers, we use apic_drivers() 410 * to enforce the order with in them. 411 */ 412 #define apic_driver(sym) \ 413 static const struct apic *__apicdrivers_##sym __used \ 414 __aligned(sizeof(struct apic *)) \ 415 __section(.apicdrivers) = { &sym } 416 417 #define apic_drivers(sym1, sym2) \ 418 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 419 __aligned(sizeof(struct apic *)) \ 420 __section(.apicdrivers) = { &sym1, &sym2 } 421 422 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 423 424 /* 425 * APIC functionality to boot other CPUs - only used on SMP: 426 */ 427 #ifdef CONFIG_SMP 428 extern atomic_t init_deasserted; 429 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 430 #endif 431 432 #ifdef CONFIG_X86_LOCAL_APIC 433 434 static inline u32 apic_read(u32 reg) 435 { 436 return apic->read(reg); 437 } 438 439 static inline void apic_write(u32 reg, u32 val) 440 { 441 apic->write(reg, val); 442 } 443 444 static inline void apic_eoi(void) 445 { 446 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 447 } 448 449 static inline u64 apic_icr_read(void) 450 { 451 return apic->icr_read(); 452 } 453 454 static inline void apic_icr_write(u32 low, u32 high) 455 { 456 apic->icr_write(low, high); 457 } 458 459 static inline void apic_wait_icr_idle(void) 460 { 461 apic->wait_icr_idle(); 462 } 463 464 static inline u32 safe_apic_wait_icr_idle(void) 465 { 466 return apic->safe_wait_icr_idle(); 467 } 468 469 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 470 471 #else /* CONFIG_X86_LOCAL_APIC */ 472 473 static inline u32 apic_read(u32 reg) { return 0; } 474 static inline void apic_write(u32 reg, u32 val) { } 475 static inline void apic_eoi(void) { } 476 static inline u64 apic_icr_read(void) { return 0; } 477 static inline void apic_icr_write(u32 low, u32 high) { } 478 static inline void apic_wait_icr_idle(void) { } 479 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 480 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 481 482 #endif /* CONFIG_X86_LOCAL_APIC */ 483 484 static inline void ack_APIC_irq(void) 485 { 486 /* 487 * ack_APIC_irq() actually gets compiled as a single instruction 488 * ... yummie. 489 */ 490 apic_eoi(); 491 } 492 493 static inline unsigned default_get_apic_id(unsigned long x) 494 { 495 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 496 497 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 498 return (x >> 24) & 0xFF; 499 else 500 return (x >> 24) & 0x0F; 501 } 502 503 /* 504 * Warm reset vector default position: 505 */ 506 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 507 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 508 509 #ifdef CONFIG_X86_64 510 extern int default_acpi_madt_oem_check(char *, char *); 511 512 extern void apic_send_IPI_self(int vector); 513 514 DECLARE_PER_CPU(int, x2apic_extra_bits); 515 516 extern int default_cpu_present_to_apicid(int mps_cpu); 517 extern int default_check_phys_apicid_present(int phys_apicid); 518 #endif 519 520 static inline void default_wait_for_init_deassert(atomic_t *deassert) 521 { 522 while (!atomic_read(deassert)) 523 cpu_relax(); 524 return; 525 } 526 527 extern void generic_bigsmp_probe(void); 528 529 530 #ifdef CONFIG_X86_LOCAL_APIC 531 532 #include <asm/smp.h> 533 534 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 535 536 static inline const struct cpumask *default_target_cpus(void) 537 { 538 #ifdef CONFIG_SMP 539 return cpu_online_mask; 540 #else 541 return cpumask_of(0); 542 #endif 543 } 544 545 static inline const struct cpumask *online_target_cpus(void) 546 { 547 return cpu_online_mask; 548 } 549 550 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 551 552 553 static inline unsigned int read_apic_id(void) 554 { 555 unsigned int reg; 556 557 reg = apic_read(APIC_ID); 558 559 return apic->get_apic_id(reg); 560 } 561 562 static inline int default_apic_id_valid(int apicid) 563 { 564 return (apicid < 255); 565 } 566 567 extern void default_setup_apic_routing(void); 568 569 extern struct apic apic_noop; 570 571 #ifdef CONFIG_X86_32 572 573 static inline int noop_x86_32_early_logical_apicid(int cpu) 574 { 575 return BAD_APICID; 576 } 577 578 /* 579 * Set up the logical destination ID. 580 * 581 * Intel recommends to set DFR, LDR and TPR before enabling 582 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 583 * document number 292116). So here it goes... 584 */ 585 extern void default_init_apic_ldr(void); 586 587 static inline int default_apic_id_registered(void) 588 { 589 return physid_isset(read_apic_id(), phys_cpu_present_map); 590 } 591 592 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 593 { 594 return cpuid_apic >> index_msb; 595 } 596 597 #endif 598 599 static inline int 600 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 601 const struct cpumask *andmask, 602 unsigned int *apicid) 603 { 604 unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 605 cpumask_bits(andmask)[0] & 606 cpumask_bits(cpu_online_mask)[0] & 607 APIC_ALL_CPUS; 608 609 if (likely(cpu_mask)) { 610 *apicid = (unsigned int)cpu_mask; 611 return 0; 612 } else { 613 return -EINVAL; 614 } 615 } 616 617 extern int 618 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 619 const struct cpumask *andmask, 620 unsigned int *apicid); 621 622 static inline void 623 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 624 const struct cpumask *mask) 625 { 626 /* Careful. Some cpus do not strictly honor the set of cpus 627 * specified in the interrupt destination when using lowest 628 * priority interrupt delivery mode. 629 * 630 * In particular there was a hyperthreading cpu observed to 631 * deliver interrupts to the wrong hyperthread when only one 632 * hyperthread was specified in the interrupt desitination. 633 */ 634 cpumask_clear(retmask); 635 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 636 } 637 638 static inline void 639 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 640 const struct cpumask *mask) 641 { 642 cpumask_copy(retmask, cpumask_of(cpu)); 643 } 644 645 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 646 { 647 return physid_isset(apicid, *map); 648 } 649 650 static inline unsigned long default_check_apicid_present(int bit) 651 { 652 return physid_isset(bit, phys_cpu_present_map); 653 } 654 655 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 656 { 657 *retmap = *phys_map; 658 } 659 660 static inline int __default_cpu_present_to_apicid(int mps_cpu) 661 { 662 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 663 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 664 else 665 return BAD_APICID; 666 } 667 668 static inline int 669 __default_check_phys_apicid_present(int phys_apicid) 670 { 671 return physid_isset(phys_apicid, phys_cpu_present_map); 672 } 673 674 #ifdef CONFIG_X86_32 675 static inline int default_cpu_present_to_apicid(int mps_cpu) 676 { 677 return __default_cpu_present_to_apicid(mps_cpu); 678 } 679 680 static inline int 681 default_check_phys_apicid_present(int phys_apicid) 682 { 683 return __default_check_phys_apicid_present(phys_apicid); 684 } 685 #else 686 extern int default_cpu_present_to_apicid(int mps_cpu); 687 extern int default_check_phys_apicid_present(int phys_apicid); 688 #endif 689 690 #endif /* CONFIG_X86_LOCAL_APIC */ 691 extern void irq_enter(void); 692 extern void irq_exit(void); 693 694 static inline void entering_irq(void) 695 { 696 irq_enter(); 697 exit_idle(); 698 } 699 700 static inline void entering_ack_irq(void) 701 { 702 ack_APIC_irq(); 703 entering_irq(); 704 } 705 706 static inline void exiting_irq(void) 707 { 708 irq_exit(); 709 } 710 711 static inline void exiting_ack_irq(void) 712 { 713 irq_exit(); 714 /* Ack only at the end to avoid potential reentry */ 715 ack_APIC_irq(); 716 } 717 718 extern void ioapic_zap_locks(void); 719 720 #endif /* _ASM_X86_APIC_H */ 721