1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/apicdef.h> 10 #include <linux/atomic.h> 11 #include <asm/fixmap.h> 12 #include <asm/mpspec.h> 13 #include <asm/msr.h> 14 #include <asm/hardirq.h> 15 16 #define ARCH_APICTIMER_STOPS_ON_C3 1 17 18 /* 19 * Debugging macros 20 */ 21 #define APIC_QUIET 0 22 #define APIC_VERBOSE 1 23 #define APIC_DEBUG 2 24 25 /* Macros for apic_extnmi which controls external NMI masking */ 26 #define APIC_EXTNMI_BSP 0 /* Default */ 27 #define APIC_EXTNMI_ALL 1 28 #define APIC_EXTNMI_NONE 2 29 30 /* 31 * Define the default level of output to be very little 32 * This can be turned up by using apic=verbose for more 33 * information and apic=debug for _lots_ of information. 34 * apic_verbosity is defined in apic.c 35 */ 36 #define apic_printk(v, s, a...) do { \ 37 if ((v) <= apic_verbosity) \ 38 printk(s, ##a); \ 39 } while (0) 40 41 42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 43 extern void x86_32_probe_apic(void); 44 #else 45 static inline void x86_32_probe_apic(void) { } 46 #endif 47 48 #ifdef CONFIG_X86_LOCAL_APIC 49 50 extern int apic_verbosity; 51 extern int local_apic_timer_c2_ok; 52 53 extern bool apic_is_disabled; 54 extern unsigned int lapic_timer_period; 55 56 extern int cpuid_to_apicid[]; 57 58 extern enum apic_intr_mode_id apic_intr_mode; 59 enum apic_intr_mode_id { 60 APIC_PIC, 61 APIC_VIRTUAL_WIRE, 62 APIC_VIRTUAL_WIRE_NO_CONFIG, 63 APIC_SYMMETRIC_IO, 64 APIC_SYMMETRIC_IO_NO_ROUTING 65 }; 66 67 /* 68 * With 82489DX we can't rely on apic feature bit 69 * retrieved via cpuid but still have to deal with 70 * such an apic chip so we assume that SMP configuration 71 * is found from MP table (64bit case uses ACPI mostly 72 * which set smp presence flag as well so we are safe 73 * to use this helper too). 74 */ 75 static inline bool apic_from_smp_config(void) 76 { 77 return smp_found_config && !apic_is_disabled; 78 } 79 80 /* 81 * Basic functions accessing APICs. 82 */ 83 #ifdef CONFIG_PARAVIRT 84 #include <asm/paravirt.h> 85 #endif 86 87 static inline void native_apic_mem_write(u32 reg, u32 v) 88 { 89 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 90 91 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 92 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 93 ASM_OUTPUT2("0" (v), "m" (*addr))); 94 } 95 96 static inline u32 native_apic_mem_read(u32 reg) 97 { 98 return *((volatile u32 *)(APIC_BASE + reg)); 99 } 100 101 static inline void native_apic_mem_eoi(void) 102 { 103 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK); 104 } 105 106 extern void native_apic_icr_write(u32 low, u32 id); 107 extern u64 native_apic_icr_read(void); 108 109 static inline bool apic_is_x2apic_enabled(void) 110 { 111 u64 msr; 112 113 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 114 return false; 115 return msr & X2APIC_ENABLE; 116 } 117 118 extern void enable_IR_x2apic(void); 119 120 extern int get_physical_broadcast(void); 121 122 extern int lapic_get_maxlvt(void); 123 extern void clear_local_APIC(void); 124 extern void disconnect_bsp_APIC(int virt_wire_setup); 125 extern void disable_local_APIC(void); 126 extern void apic_soft_disable(void); 127 extern void lapic_shutdown(void); 128 extern void sync_Arb_IDs(void); 129 extern void init_bsp_APIC(void); 130 extern void apic_intr_mode_select(void); 131 extern void apic_intr_mode_init(void); 132 extern void init_apic_mappings(void); 133 void register_lapic_address(unsigned long address); 134 extern void setup_boot_APIC_clock(void); 135 extern void setup_secondary_APIC_clock(void); 136 extern void lapic_update_tsc_freq(void); 137 138 #ifdef CONFIG_X86_64 139 static inline bool apic_force_enable(unsigned long addr) 140 { 141 return false; 142 } 143 #else 144 extern bool apic_force_enable(unsigned long addr); 145 #endif 146 147 extern void apic_ap_setup(void); 148 149 /* 150 * On 32bit this is mach-xxx local 151 */ 152 #ifdef CONFIG_X86_64 153 extern int apic_is_clustered_box(void); 154 #else 155 static inline int apic_is_clustered_box(void) 156 { 157 return 0; 158 } 159 #endif 160 161 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 162 extern void lapic_assign_system_vectors(void); 163 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 164 extern void lapic_update_legacy_vectors(void); 165 extern void lapic_online(void); 166 extern void lapic_offline(void); 167 extern bool apic_needs_pit(void); 168 169 extern void apic_send_IPI_allbutself(unsigned int vector); 170 171 #else /* !CONFIG_X86_LOCAL_APIC */ 172 static inline void lapic_shutdown(void) { } 173 #define local_apic_timer_c2_ok 1 174 static inline void init_apic_mappings(void) { } 175 static inline void disable_local_APIC(void) { } 176 # define setup_boot_APIC_clock x86_init_noop 177 # define setup_secondary_APIC_clock x86_init_noop 178 static inline void lapic_update_tsc_freq(void) { } 179 static inline void init_bsp_APIC(void) { } 180 static inline void apic_intr_mode_select(void) { } 181 static inline void apic_intr_mode_init(void) { } 182 static inline void lapic_assign_system_vectors(void) { } 183 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 184 static inline bool apic_needs_pit(void) { return true; } 185 #endif /* !CONFIG_X86_LOCAL_APIC */ 186 187 #ifdef CONFIG_X86_X2APIC 188 static inline void native_apic_msr_write(u32 reg, u32 v) 189 { 190 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 191 reg == APIC_LVR) 192 return; 193 194 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 195 } 196 197 static inline void native_apic_msr_eoi(void) 198 { 199 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 200 } 201 202 static inline u32 native_apic_msr_read(u32 reg) 203 { 204 u64 msr; 205 206 if (reg == APIC_DFR) 207 return -1; 208 209 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 210 return (u32)msr; 211 } 212 213 static inline void native_x2apic_icr_write(u32 low, u32 id) 214 { 215 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 216 } 217 218 static inline u64 native_x2apic_icr_read(void) 219 { 220 unsigned long val; 221 222 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 223 return val; 224 } 225 226 extern int x2apic_mode; 227 extern int x2apic_phys; 228 extern void __init x2apic_set_max_apicid(u32 apicid); 229 extern void x2apic_setup(void); 230 static inline int x2apic_enabled(void) 231 { 232 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 233 } 234 235 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 236 #else /* !CONFIG_X86_X2APIC */ 237 static inline void x2apic_setup(void) { } 238 static inline int x2apic_enabled(void) { return 0; } 239 static inline u32 native_apic_msr_read(u32 reg) { BUG(); } 240 #define x2apic_mode (0) 241 #define x2apic_supported() (0) 242 #endif /* !CONFIG_X86_X2APIC */ 243 extern void __init check_x2apic(void); 244 245 struct irq_data; 246 247 /* 248 * Copyright 2004 James Cleverdon, IBM. 249 * 250 * Generic APIC sub-arch data struct. 251 * 252 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 253 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 254 * James Cleverdon. 255 */ 256 struct apic { 257 /* Hotpath functions first */ 258 void (*eoi)(void); 259 void (*native_eoi)(void); 260 void (*write)(u32 reg, u32 v); 261 u32 (*read)(u32 reg); 262 263 /* IPI related functions */ 264 void (*wait_icr_idle)(void); 265 u32 (*safe_wait_icr_idle)(void); 266 267 void (*send_IPI)(int cpu, int vector); 268 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 269 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 270 void (*send_IPI_allbutself)(int vector); 271 void (*send_IPI_all)(int vector); 272 void (*send_IPI_self)(int vector); 273 274 enum apic_delivery_modes delivery_mode; 275 276 u32 disable_esr : 1, 277 dest_mode_logical : 1, 278 x2apic_set_max_apicid : 1; 279 280 u32 (*calc_dest_apicid)(unsigned int cpu); 281 282 /* ICR related functions */ 283 u64 (*icr_read)(void); 284 void (*icr_write)(u32 low, u32 high); 285 286 /* The limit of the APIC ID space. */ 287 u32 max_apic_id; 288 289 /* Probe, setup and smpboot functions */ 290 int (*probe)(void); 291 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 292 bool (*apic_id_registered)(void); 293 294 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 295 void (*init_apic_ldr)(void); 296 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 297 int (*cpu_present_to_apicid)(int mps_cpu); 298 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 299 300 u32 (*get_apic_id)(unsigned long x); 301 u32 (*set_apic_id)(unsigned int id); 302 303 /* wakeup_secondary_cpu */ 304 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 305 /* wakeup secondary CPU using 64-bit wakeup point */ 306 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); 307 308 char *name; 309 }; 310 311 /* 312 * Pointer to the local APIC driver in use on this system (there's 313 * always just one such driver in use - the kernel decides via an 314 * early probing process which one it picks - and then sticks to it): 315 */ 316 extern struct apic *apic; 317 318 /* 319 * APIC drivers are probed based on how they are listed in the .apicdrivers 320 * section. So the order is important and enforced by the ordering 321 * of different apic driver files in the Makefile. 322 * 323 * For the files having two apic drivers, we use apic_drivers() 324 * to enforce the order with in them. 325 */ 326 #define apic_driver(sym) \ 327 static const struct apic *__apicdrivers_##sym __used \ 328 __aligned(sizeof(struct apic *)) \ 329 __section(".apicdrivers") = { &sym } 330 331 #define apic_drivers(sym1, sym2) \ 332 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 333 __aligned(sizeof(struct apic *)) \ 334 __section(".apicdrivers") = { &sym1, &sym2 } 335 336 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 337 338 /* 339 * APIC functionality to boot other CPUs - only used on SMP: 340 */ 341 #ifdef CONFIG_SMP 342 extern int lapic_can_unplug_cpu(void); 343 #endif 344 345 #ifdef CONFIG_X86_LOCAL_APIC 346 347 static inline u32 apic_read(u32 reg) 348 { 349 return apic->read(reg); 350 } 351 352 static inline void apic_write(u32 reg, u32 val) 353 { 354 apic->write(reg, val); 355 } 356 357 static inline void apic_eoi(void) 358 { 359 apic->eoi(); 360 } 361 362 static inline void apic_native_eoi(void) 363 { 364 apic->native_eoi(); 365 } 366 367 static inline u64 apic_icr_read(void) 368 { 369 return apic->icr_read(); 370 } 371 372 static inline void apic_icr_write(u32 low, u32 high) 373 { 374 apic->icr_write(low, high); 375 } 376 377 static inline void apic_wait_icr_idle(void) 378 { 379 if (apic->wait_icr_idle) 380 apic->wait_icr_idle(); 381 } 382 383 static inline u32 safe_apic_wait_icr_idle(void) 384 { 385 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; 386 } 387 388 static inline bool apic_id_valid(u32 apic_id) 389 { 390 return apic_id <= apic->max_apic_id; 391 } 392 393 extern void __init apic_set_eoi_cb(void (*eoi)(void)); 394 395 #else /* CONFIG_X86_LOCAL_APIC */ 396 397 static inline u32 apic_read(u32 reg) { return 0; } 398 static inline void apic_write(u32 reg, u32 val) { } 399 static inline void apic_eoi(void) { } 400 static inline u64 apic_icr_read(void) { return 0; } 401 static inline void apic_icr_write(u32 low, u32 high) { } 402 static inline void apic_wait_icr_idle(void) { } 403 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 404 static inline void apic_set_eoi_cb(void (*eoi)(void)) {} 405 static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } 406 407 #endif /* CONFIG_X86_LOCAL_APIC */ 408 409 extern void apic_ack_irq(struct irq_data *data); 410 411 static inline bool lapic_vector_set_in_irr(unsigned int vector) 412 { 413 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 414 415 return !!(irr & (1U << (vector % 32))); 416 } 417 418 static inline unsigned default_get_apic_id(unsigned long x) 419 { 420 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 421 422 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 423 return (x >> 24) & 0xFF; 424 else 425 return (x >> 24) & 0x0F; 426 } 427 428 /* 429 * Warm reset vector position: 430 */ 431 #define TRAMPOLINE_PHYS_LOW 0x467 432 #define TRAMPOLINE_PHYS_HIGH 0x469 433 434 extern void generic_bigsmp_probe(void); 435 436 #ifdef CONFIG_X86_LOCAL_APIC 437 438 #include <asm/smp.h> 439 440 extern struct apic apic_noop; 441 442 static inline unsigned int read_apic_id(void) 443 { 444 unsigned int reg = apic_read(APIC_ID); 445 446 return apic->get_apic_id(reg); 447 } 448 449 #ifdef CONFIG_X86_64 450 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 451 extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); 452 extern int default_acpi_madt_oem_check(char *, char *); 453 extern void x86_64_probe_apic(void); 454 #else 455 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } 456 static inline void x86_64_probe_apic(void) { } 457 #endif 458 459 extern int default_apic_id_valid(u32 apicid); 460 461 extern u32 apic_default_calc_apicid(unsigned int cpu); 462 extern u32 apic_flat_calc_apicid(unsigned int cpu); 463 464 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 465 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 466 extern int default_cpu_present_to_apicid(int mps_cpu); 467 468 #else /* CONFIG_X86_LOCAL_APIC */ 469 470 static inline unsigned int read_apic_id(void) { return 0; } 471 472 #endif /* !CONFIG_X86_LOCAL_APIC */ 473 474 #ifdef CONFIG_SMP 475 void apic_smt_update(void); 476 #else 477 static inline void apic_smt_update(void) { } 478 #endif 479 480 struct msi_msg; 481 struct irq_cfg; 482 483 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 484 bool dmar); 485 486 extern void ioapic_zap_locks(void); 487 488 #endif /* _ASM_X86_APIC_H */ 489