1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 6 #include <asm/alternative.h> 7 #include <asm/cpufeature.h> 8 #include <asm/apicdef.h> 9 #include <linux/atomic.h> 10 #include <asm/fixmap.h> 11 #include <asm/mpspec.h> 12 #include <asm/msr.h> 13 14 #define ARCH_APICTIMER_STOPS_ON_C3 1 15 16 /* 17 * Debugging macros 18 */ 19 #define APIC_QUIET 0 20 #define APIC_VERBOSE 1 21 #define APIC_DEBUG 2 22 23 /* Macros for apic_extnmi which controls external NMI masking */ 24 #define APIC_EXTNMI_BSP 0 /* Default */ 25 #define APIC_EXTNMI_ALL 1 26 #define APIC_EXTNMI_NONE 2 27 28 /* 29 * Define the default level of output to be very little 30 * This can be turned up by using apic=verbose for more 31 * information and apic=debug for _lots_ of information. 32 * apic_verbosity is defined in apic.c 33 */ 34 #define apic_printk(v, s, a...) do { \ 35 if ((v) <= apic_verbosity) \ 36 printk(s, ##a); \ 37 } while (0) 38 39 40 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 41 extern void generic_apic_probe(void); 42 #else 43 static inline void generic_apic_probe(void) 44 { 45 } 46 #endif 47 48 #ifdef CONFIG_X86_LOCAL_APIC 49 50 extern unsigned int apic_verbosity; 51 extern int local_apic_timer_c2_ok; 52 53 extern int disable_apic; 54 extern unsigned int lapic_timer_frequency; 55 56 extern enum apic_intr_mode_id apic_intr_mode; 57 enum apic_intr_mode_id { 58 APIC_PIC, 59 APIC_VIRTUAL_WIRE, 60 APIC_VIRTUAL_WIRE_NO_CONFIG, 61 APIC_SYMMETRIC_IO, 62 APIC_SYMMETRIC_IO_NO_ROUTING 63 }; 64 65 #ifdef CONFIG_SMP 66 extern void __inquire_remote_apic(int apicid); 67 #else /* CONFIG_SMP */ 68 static inline void __inquire_remote_apic(int apicid) 69 { 70 } 71 #endif /* CONFIG_SMP */ 72 73 static inline void default_inquire_remote_apic(int apicid) 74 { 75 if (apic_verbosity >= APIC_DEBUG) 76 __inquire_remote_apic(apicid); 77 } 78 79 /* 80 * With 82489DX we can't rely on apic feature bit 81 * retrieved via cpuid but still have to deal with 82 * such an apic chip so we assume that SMP configuration 83 * is found from MP table (64bit case uses ACPI mostly 84 * which set smp presence flag as well so we are safe 85 * to use this helper too). 86 */ 87 static inline bool apic_from_smp_config(void) 88 { 89 return smp_found_config && !disable_apic; 90 } 91 92 /* 93 * Basic functions accessing APICs. 94 */ 95 #ifdef CONFIG_PARAVIRT 96 #include <asm/paravirt.h> 97 #endif 98 99 extern int setup_profiling_timer(unsigned int); 100 101 static inline void native_apic_mem_write(u32 reg, u32 v) 102 { 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108 } 109 110 static inline u32 native_apic_mem_read(u32 reg) 111 { 112 return *((volatile u32 *)(APIC_BASE + reg)); 113 } 114 115 extern void native_apic_wait_icr_idle(void); 116 extern u32 native_safe_apic_wait_icr_idle(void); 117 extern void native_apic_icr_write(u32 low, u32 id); 118 extern u64 native_apic_icr_read(void); 119 120 static inline bool apic_is_x2apic_enabled(void) 121 { 122 u64 msr; 123 124 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 125 return false; 126 return msr & X2APIC_ENABLE; 127 } 128 129 extern void enable_IR_x2apic(void); 130 131 extern int get_physical_broadcast(void); 132 133 extern int lapic_get_maxlvt(void); 134 extern void clear_local_APIC(void); 135 extern void disconnect_bsp_APIC(int virt_wire_setup); 136 extern void disable_local_APIC(void); 137 extern void lapic_shutdown(void); 138 extern void sync_Arb_IDs(void); 139 extern void init_bsp_APIC(void); 140 extern void apic_intr_mode_init(void); 141 extern void setup_local_APIC(void); 142 extern void init_apic_mappings(void); 143 void register_lapic_address(unsigned long address); 144 extern void setup_boot_APIC_clock(void); 145 extern void setup_secondary_APIC_clock(void); 146 extern void lapic_update_tsc_freq(void); 147 148 #ifdef CONFIG_X86_64 149 static inline int apic_force_enable(unsigned long addr) 150 { 151 return -1; 152 } 153 #else 154 extern int apic_force_enable(unsigned long addr); 155 #endif 156 157 extern void apic_bsp_setup(bool upmode); 158 extern void apic_ap_setup(void); 159 160 /* 161 * On 32bit this is mach-xxx local 162 */ 163 #ifdef CONFIG_X86_64 164 extern int apic_is_clustered_box(void); 165 #else 166 static inline int apic_is_clustered_box(void) 167 { 168 return 0; 169 } 170 #endif 171 172 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 173 174 #else /* !CONFIG_X86_LOCAL_APIC */ 175 static inline void lapic_shutdown(void) { } 176 #define local_apic_timer_c2_ok 1 177 static inline void init_apic_mappings(void) { } 178 static inline void disable_local_APIC(void) { } 179 # define setup_boot_APIC_clock x86_init_noop 180 # define setup_secondary_APIC_clock x86_init_noop 181 static inline void lapic_update_tsc_freq(void) { } 182 static inline void apic_intr_mode_init(void) { } 183 #endif /* !CONFIG_X86_LOCAL_APIC */ 184 185 #ifdef CONFIG_X86_X2APIC 186 /* 187 * Make previous memory operations globally visible before 188 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 189 * mfence for this. 190 */ 191 static inline void x2apic_wrmsr_fence(void) 192 { 193 asm volatile("mfence" : : : "memory"); 194 } 195 196 static inline void native_apic_msr_write(u32 reg, u32 v) 197 { 198 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 199 reg == APIC_LVR) 200 return; 201 202 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 203 } 204 205 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 206 { 207 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 208 } 209 210 static inline u32 native_apic_msr_read(u32 reg) 211 { 212 u64 msr; 213 214 if (reg == APIC_DFR) 215 return -1; 216 217 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 218 return (u32)msr; 219 } 220 221 static inline void native_x2apic_wait_icr_idle(void) 222 { 223 /* no need to wait for icr idle in x2apic */ 224 return; 225 } 226 227 static inline u32 native_safe_x2apic_wait_icr_idle(void) 228 { 229 /* no need to wait for icr idle in x2apic */ 230 return 0; 231 } 232 233 static inline void native_x2apic_icr_write(u32 low, u32 id) 234 { 235 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 236 } 237 238 static inline u64 native_x2apic_icr_read(void) 239 { 240 unsigned long val; 241 242 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 243 return val; 244 } 245 246 extern int x2apic_mode; 247 extern int x2apic_phys; 248 extern void __init check_x2apic(void); 249 extern void x2apic_setup(void); 250 static inline int x2apic_enabled(void) 251 { 252 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 253 } 254 255 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 256 #else /* !CONFIG_X86_X2APIC */ 257 static inline void check_x2apic(void) { } 258 static inline void x2apic_setup(void) { } 259 static inline int x2apic_enabled(void) { return 0; } 260 261 #define x2apic_mode (0) 262 #define x2apic_supported() (0) 263 #endif /* !CONFIG_X86_X2APIC */ 264 265 struct irq_data; 266 267 /* 268 * Copyright 2004 James Cleverdon, IBM. 269 * Subject to the GNU Public License, v.2 270 * 271 * Generic APIC sub-arch data struct. 272 * 273 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 274 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 275 * James Cleverdon. 276 */ 277 struct apic { 278 char *name; 279 280 int (*probe)(void); 281 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 282 int (*apic_id_valid)(int apicid); 283 int (*apic_id_registered)(void); 284 285 u32 irq_delivery_mode; 286 u32 irq_dest_mode; 287 288 const struct cpumask *(*target_cpus)(void); 289 290 int disable_esr; 291 292 int dest_logical; 293 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 294 295 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 296 const struct cpumask *mask); 297 void (*init_apic_ldr)(void); 298 299 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 300 301 void (*setup_apic_routing)(void); 302 int (*cpu_present_to_apicid)(int mps_cpu); 303 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 304 int (*check_phys_apicid_present)(int phys_apicid); 305 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 306 307 unsigned int (*get_apic_id)(unsigned long x); 308 /* Can't be NULL on 64-bit */ 309 unsigned long (*set_apic_id)(unsigned int id); 310 311 int (*cpu_mask_to_apicid)(const struct cpumask *cpumask, 312 struct irq_data *irqdata, 313 unsigned int *apicid); 314 315 /* ipi */ 316 void (*send_IPI)(int cpu, int vector); 317 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 318 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 319 int vector); 320 void (*send_IPI_allbutself)(int vector); 321 void (*send_IPI_all)(int vector); 322 void (*send_IPI_self)(int vector); 323 324 /* wakeup_secondary_cpu */ 325 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 326 327 void (*inquire_remote_apic)(int apicid); 328 329 /* apic ops */ 330 u32 (*read)(u32 reg); 331 void (*write)(u32 reg, u32 v); 332 /* 333 * ->eoi_write() has the same signature as ->write(). 334 * 335 * Drivers can support both ->eoi_write() and ->write() by passing the same 336 * callback value. Kernel can override ->eoi_write() and fall back 337 * on write for EOI. 338 */ 339 void (*eoi_write)(u32 reg, u32 v); 340 void (*native_eoi_write)(u32 reg, u32 v); 341 u64 (*icr_read)(void); 342 void (*icr_write)(u32 low, u32 high); 343 void (*wait_icr_idle)(void); 344 u32 (*safe_wait_icr_idle)(void); 345 346 #ifdef CONFIG_X86_32 347 /* 348 * Called very early during boot from get_smp_config(). It should 349 * return the logical apicid. x86_[bios]_cpu_to_apicid is 350 * initialized before this function is called. 351 * 352 * If logical apicid can't be determined that early, the function 353 * may return BAD_APICID. Logical apicid will be configured after 354 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 355 * won't be applied properly during early boot in this case. 356 */ 357 int (*x86_32_early_logical_apicid)(int cpu); 358 #endif 359 }; 360 361 /* 362 * Pointer to the local APIC driver in use on this system (there's 363 * always just one such driver in use - the kernel decides via an 364 * early probing process which one it picks - and then sticks to it): 365 */ 366 extern struct apic *apic; 367 368 /* 369 * APIC drivers are probed based on how they are listed in the .apicdrivers 370 * section. So the order is important and enforced by the ordering 371 * of different apic driver files in the Makefile. 372 * 373 * For the files having two apic drivers, we use apic_drivers() 374 * to enforce the order with in them. 375 */ 376 #define apic_driver(sym) \ 377 static const struct apic *__apicdrivers_##sym __used \ 378 __aligned(sizeof(struct apic *)) \ 379 __section(.apicdrivers) = { &sym } 380 381 #define apic_drivers(sym1, sym2) \ 382 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 383 __aligned(sizeof(struct apic *)) \ 384 __section(.apicdrivers) = { &sym1, &sym2 } 385 386 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 387 388 /* 389 * APIC functionality to boot other CPUs - only used on SMP: 390 */ 391 #ifdef CONFIG_SMP 392 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 393 #endif 394 395 #ifdef CONFIG_X86_LOCAL_APIC 396 397 static inline u32 apic_read(u32 reg) 398 { 399 return apic->read(reg); 400 } 401 402 static inline void apic_write(u32 reg, u32 val) 403 { 404 apic->write(reg, val); 405 } 406 407 static inline void apic_eoi(void) 408 { 409 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 410 } 411 412 static inline u64 apic_icr_read(void) 413 { 414 return apic->icr_read(); 415 } 416 417 static inline void apic_icr_write(u32 low, u32 high) 418 { 419 apic->icr_write(low, high); 420 } 421 422 static inline void apic_wait_icr_idle(void) 423 { 424 apic->wait_icr_idle(); 425 } 426 427 static inline u32 safe_apic_wait_icr_idle(void) 428 { 429 return apic->safe_wait_icr_idle(); 430 } 431 432 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 433 434 #else /* CONFIG_X86_LOCAL_APIC */ 435 436 static inline u32 apic_read(u32 reg) { return 0; } 437 static inline void apic_write(u32 reg, u32 val) { } 438 static inline void apic_eoi(void) { } 439 static inline u64 apic_icr_read(void) { return 0; } 440 static inline void apic_icr_write(u32 low, u32 high) { } 441 static inline void apic_wait_icr_idle(void) { } 442 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 443 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 444 445 #endif /* CONFIG_X86_LOCAL_APIC */ 446 447 static inline void ack_APIC_irq(void) 448 { 449 /* 450 * ack_APIC_irq() actually gets compiled as a single instruction 451 * ... yummie. 452 */ 453 apic_eoi(); 454 } 455 456 static inline unsigned default_get_apic_id(unsigned long x) 457 { 458 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 459 460 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 461 return (x >> 24) & 0xFF; 462 else 463 return (x >> 24) & 0x0F; 464 } 465 466 /* 467 * Warm reset vector position: 468 */ 469 #define TRAMPOLINE_PHYS_LOW 0x467 470 #define TRAMPOLINE_PHYS_HIGH 0x469 471 472 #ifdef CONFIG_X86_64 473 extern void apic_send_IPI_self(int vector); 474 475 DECLARE_PER_CPU(int, x2apic_extra_bits); 476 477 extern int default_cpu_present_to_apicid(int mps_cpu); 478 extern int default_check_phys_apicid_present(int phys_apicid); 479 #endif 480 481 extern void generic_bigsmp_probe(void); 482 483 484 #ifdef CONFIG_X86_LOCAL_APIC 485 486 #include <asm/smp.h> 487 488 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 489 490 static inline const struct cpumask *default_target_cpus(void) 491 { 492 #ifdef CONFIG_SMP 493 return cpu_online_mask; 494 #else 495 return cpumask_of(0); 496 #endif 497 } 498 499 static inline const struct cpumask *online_target_cpus(void) 500 { 501 return cpu_online_mask; 502 } 503 504 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 505 506 507 static inline unsigned int read_apic_id(void) 508 { 509 unsigned int reg; 510 511 reg = apic_read(APIC_ID); 512 513 return apic->get_apic_id(reg); 514 } 515 516 static inline int default_apic_id_valid(int apicid) 517 { 518 return (apicid < 255); 519 } 520 521 extern int default_acpi_madt_oem_check(char *, char *); 522 523 extern void default_setup_apic_routing(void); 524 525 extern struct apic apic_noop; 526 527 #ifdef CONFIG_X86_32 528 529 static inline int noop_x86_32_early_logical_apicid(int cpu) 530 { 531 return BAD_APICID; 532 } 533 534 /* 535 * Set up the logical destination ID. 536 * 537 * Intel recommends to set DFR, LDR and TPR before enabling 538 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 539 * document number 292116). So here it goes... 540 */ 541 extern void default_init_apic_ldr(void); 542 543 static inline int default_apic_id_registered(void) 544 { 545 return physid_isset(read_apic_id(), phys_cpu_present_map); 546 } 547 548 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 549 { 550 return cpuid_apic >> index_msb; 551 } 552 553 #endif 554 555 extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask, 556 struct irq_data *irqdata, 557 unsigned int *apicid); 558 extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask, 559 struct irq_data *irqdata, 560 unsigned int *apicid); 561 562 static inline void 563 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 564 const struct cpumask *mask) 565 { 566 /* Careful. Some cpus do not strictly honor the set of cpus 567 * specified in the interrupt destination when using lowest 568 * priority interrupt delivery mode. 569 * 570 * In particular there was a hyperthreading cpu observed to 571 * deliver interrupts to the wrong hyperthread when only one 572 * hyperthread was specified in the interrupt desitination. 573 */ 574 cpumask_clear(retmask); 575 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 576 } 577 578 static inline void 579 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 580 const struct cpumask *mask) 581 { 582 cpumask_copy(retmask, cpumask_of(cpu)); 583 } 584 585 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 586 { 587 return physid_isset(apicid, *map); 588 } 589 590 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 591 { 592 *retmap = *phys_map; 593 } 594 595 static inline int __default_cpu_present_to_apicid(int mps_cpu) 596 { 597 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 598 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 599 else 600 return BAD_APICID; 601 } 602 603 static inline int 604 __default_check_phys_apicid_present(int phys_apicid) 605 { 606 return physid_isset(phys_apicid, phys_cpu_present_map); 607 } 608 609 #ifdef CONFIG_X86_32 610 static inline int default_cpu_present_to_apicid(int mps_cpu) 611 { 612 return __default_cpu_present_to_apicid(mps_cpu); 613 } 614 615 static inline int 616 default_check_phys_apicid_present(int phys_apicid) 617 { 618 return __default_check_phys_apicid_present(phys_apicid); 619 } 620 #else 621 extern int default_cpu_present_to_apicid(int mps_cpu); 622 extern int default_check_phys_apicid_present(int phys_apicid); 623 #endif 624 625 #endif /* CONFIG_X86_LOCAL_APIC */ 626 extern void irq_enter(void); 627 extern void irq_exit(void); 628 629 static inline void entering_irq(void) 630 { 631 irq_enter(); 632 } 633 634 static inline void entering_ack_irq(void) 635 { 636 entering_irq(); 637 ack_APIC_irq(); 638 } 639 640 static inline void ipi_entering_ack_irq(void) 641 { 642 irq_enter(); 643 ack_APIC_irq(); 644 } 645 646 static inline void exiting_irq(void) 647 { 648 irq_exit(); 649 } 650 651 static inline void exiting_ack_irq(void) 652 { 653 ack_APIC_irq(); 654 irq_exit(); 655 } 656 657 extern void ioapic_zap_locks(void); 658 659 #endif /* _ASM_X86_APIC_H */ 660