11965aae3SH. Peter Anvin #ifndef _ASM_X86_APIC_H 21965aae3SH. Peter Anvin #define _ASM_X86_APIC_H 3bb898558SAl Viro 4e2780a68SIngo Molnar #include <linux/cpumask.h> 5bb898558SAl Viro #include <linux/delay.h> 6e2780a68SIngo Molnar #include <linux/pm.h> 7bb898558SAl Viro 8bb898558SAl Viro #include <asm/alternative.h> 9bb898558SAl Viro #include <asm/cpufeature.h> 10e2780a68SIngo Molnar #include <asm/processor.h> 11e2780a68SIngo Molnar #include <asm/apicdef.h> 12e2780a68SIngo Molnar #include <asm/atomic.h> 13e2780a68SIngo Molnar #include <asm/fixmap.h> 14e2780a68SIngo Molnar #include <asm/mpspec.h> 15e2780a68SIngo Molnar #include <asm/system.h> 16bb898558SAl Viro #include <asm/msr.h> 17bb898558SAl Viro 18bb898558SAl Viro #define ARCH_APICTIMER_STOPS_ON_C3 1 19bb898558SAl Viro 20bb898558SAl Viro /* 21bb898558SAl Viro * Debugging macros 22bb898558SAl Viro */ 23bb898558SAl Viro #define APIC_QUIET 0 24bb898558SAl Viro #define APIC_VERBOSE 1 25bb898558SAl Viro #define APIC_DEBUG 2 26bb898558SAl Viro 27bb898558SAl Viro /* 28bb898558SAl Viro * Define the default level of output to be very little 29bb898558SAl Viro * This can be turned up by using apic=verbose for more 30bb898558SAl Viro * information and apic=debug for _lots_ of information. 31bb898558SAl Viro * apic_verbosity is defined in apic.c 32bb898558SAl Viro */ 33bb898558SAl Viro #define apic_printk(v, s, a...) do { \ 34bb898558SAl Viro if ((v) <= apic_verbosity) \ 35bb898558SAl Viro printk(s, ##a); \ 36bb898558SAl Viro } while (0) 37bb898558SAl Viro 38bb898558SAl Viro 39160d8dacSIngo Molnar #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 40bb898558SAl Viro extern void generic_apic_probe(void); 41160d8dacSIngo Molnar #else 42160d8dacSIngo Molnar static inline void generic_apic_probe(void) 43160d8dacSIngo Molnar { 44160d8dacSIngo Molnar } 45160d8dacSIngo Molnar #endif 46bb898558SAl Viro 47bb898558SAl Viro #ifdef CONFIG_X86_LOCAL_APIC 48bb898558SAl Viro 49bb898558SAl Viro extern unsigned int apic_verbosity; 50bb898558SAl Viro extern int local_apic_timer_c2_ok; 51bb898558SAl Viro 52bb898558SAl Viro extern int disable_apic; 530939e4fdSIngo Molnar 540939e4fdSIngo Molnar #ifdef CONFIG_SMP 550939e4fdSIngo Molnar extern void __inquire_remote_apic(int apicid); 560939e4fdSIngo Molnar #else /* CONFIG_SMP */ 570939e4fdSIngo Molnar static inline void __inquire_remote_apic(int apicid) 580939e4fdSIngo Molnar { 590939e4fdSIngo Molnar } 600939e4fdSIngo Molnar #endif /* CONFIG_SMP */ 610939e4fdSIngo Molnar 620939e4fdSIngo Molnar static inline void default_inquire_remote_apic(int apicid) 630939e4fdSIngo Molnar { 640939e4fdSIngo Molnar if (apic_verbosity >= APIC_DEBUG) 650939e4fdSIngo Molnar __inquire_remote_apic(apicid); 660939e4fdSIngo Molnar } 670939e4fdSIngo Molnar 68bb898558SAl Viro /* 69bb898558SAl Viro * Basic functions accessing APICs. 70bb898558SAl Viro */ 71bb898558SAl Viro #ifdef CONFIG_PARAVIRT 72bb898558SAl Viro #include <asm/paravirt.h> 73bb898558SAl Viro #else 74bb898558SAl Viro #define setup_boot_clock setup_boot_APIC_clock 75bb898558SAl Viro #define setup_secondary_clock setup_secondary_APIC_clock 76bb898558SAl Viro #endif 77bb898558SAl Viro 78129d8bc8SYinghai Lu #ifdef CONFIG_X86_VSMP 79bb898558SAl Viro extern int is_vsmp_box(void); 80129d8bc8SYinghai Lu #else 81129d8bc8SYinghai Lu static inline int is_vsmp_box(void) 82129d8bc8SYinghai Lu { 83129d8bc8SYinghai Lu return 0; 84129d8bc8SYinghai Lu } 85129d8bc8SYinghai Lu #endif 86bb898558SAl Viro extern void xapic_wait_icr_idle(void); 87bb898558SAl Viro extern u32 safe_xapic_wait_icr_idle(void); 88bb898558SAl Viro extern void xapic_icr_write(u32, u32); 89bb898558SAl Viro extern int setup_profiling_timer(unsigned int); 90bb898558SAl Viro 91bb898558SAl Viro static inline void native_apic_mem_write(u32 reg, u32 v) 92bb898558SAl Viro { 93bb898558SAl Viro volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 94bb898558SAl Viro 95bb898558SAl Viro alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 96bb898558SAl Viro ASM_OUTPUT2("=r" (v), "=m" (*addr)), 97bb898558SAl Viro ASM_OUTPUT2("0" (v), "m" (*addr))); 98bb898558SAl Viro } 99bb898558SAl Viro 100bb898558SAl Viro static inline u32 native_apic_mem_read(u32 reg) 101bb898558SAl Viro { 102bb898558SAl Viro return *((volatile u32 *)(APIC_BASE + reg)); 103bb898558SAl Viro } 104bb898558SAl Viro 105c1eeb2deSYinghai Lu extern void native_apic_wait_icr_idle(void); 106c1eeb2deSYinghai Lu extern u32 native_safe_apic_wait_icr_idle(void); 107c1eeb2deSYinghai Lu extern void native_apic_icr_write(u32 low, u32 id); 108c1eeb2deSYinghai Lu extern u64 native_apic_icr_read(void); 109c1eeb2deSYinghai Lu 110c1eeb2deSYinghai Lu #ifdef CONFIG_X86_X2APIC 111ce4e240cSSuresh Siddha /* 112ce4e240cSSuresh Siddha * Make previous memory operations globally visible before 113ce4e240cSSuresh Siddha * sending the IPI through x2apic wrmsr. We need a serializing instruction or 114ce4e240cSSuresh Siddha * mfence for this. 115ce4e240cSSuresh Siddha */ 116ce4e240cSSuresh Siddha static inline void x2apic_wrmsr_fence(void) 117ce4e240cSSuresh Siddha { 118ce4e240cSSuresh Siddha asm volatile("mfence" : : : "memory"); 119ce4e240cSSuresh Siddha } 120ce4e240cSSuresh Siddha 121bb898558SAl Viro static inline void native_apic_msr_write(u32 reg, u32 v) 122bb898558SAl Viro { 123bb898558SAl Viro if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 124bb898558SAl Viro reg == APIC_LVR) 125bb898558SAl Viro return; 126bb898558SAl Viro 127bb898558SAl Viro wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 128bb898558SAl Viro } 129bb898558SAl Viro 130bb898558SAl Viro static inline u32 native_apic_msr_read(u32 reg) 131bb898558SAl Viro { 132bb898558SAl Viro u32 low, high; 133bb898558SAl Viro 134bb898558SAl Viro if (reg == APIC_DFR) 135bb898558SAl Viro return -1; 136bb898558SAl Viro 137bb898558SAl Viro rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); 138bb898558SAl Viro return low; 139bb898558SAl Viro } 140bb898558SAl Viro 141c1eeb2deSYinghai Lu static inline void native_x2apic_wait_icr_idle(void) 142c1eeb2deSYinghai Lu { 143c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 144c1eeb2deSYinghai Lu return; 145c1eeb2deSYinghai Lu } 146c1eeb2deSYinghai Lu 147c1eeb2deSYinghai Lu static inline u32 native_safe_x2apic_wait_icr_idle(void) 148c1eeb2deSYinghai Lu { 149c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 150c1eeb2deSYinghai Lu return 0; 151c1eeb2deSYinghai Lu } 152c1eeb2deSYinghai Lu 153c1eeb2deSYinghai Lu static inline void native_x2apic_icr_write(u32 low, u32 id) 154c1eeb2deSYinghai Lu { 155c1eeb2deSYinghai Lu wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 156c1eeb2deSYinghai Lu } 157c1eeb2deSYinghai Lu 158c1eeb2deSYinghai Lu static inline u64 native_x2apic_icr_read(void) 159c1eeb2deSYinghai Lu { 160c1eeb2deSYinghai Lu unsigned long val; 161c1eeb2deSYinghai Lu 162c1eeb2deSYinghai Lu rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 163c1eeb2deSYinghai Lu return val; 164c1eeb2deSYinghai Lu } 165c1eeb2deSYinghai Lu 166ef1f87aaSSuresh Siddha extern int x2apic, x2apic_phys; 167bb898558SAl Viro extern void check_x2apic(void); 168bb898558SAl Viro extern void enable_x2apic(void); 169bb898558SAl Viro extern void enable_IR_x2apic(void); 170bb898558SAl Viro extern void x2apic_icr_write(u32 low, u32 id); 171bb898558SAl Viro static inline int x2apic_enabled(void) 172bb898558SAl Viro { 173bb898558SAl Viro int msr, msr2; 174bb898558SAl Viro 175bb898558SAl Viro if (!cpu_has_x2apic) 176bb898558SAl Viro return 0; 177bb898558SAl Viro 178bb898558SAl Viro rdmsr(MSR_IA32_APICBASE, msr, msr2); 179bb898558SAl Viro if (msr & X2APIC_ENABLE) 180bb898558SAl Viro return 1; 181bb898558SAl Viro return 0; 182bb898558SAl Viro } 183bb898558SAl Viro #else 18406cd9a7dSYinghai Lu static inline void check_x2apic(void) 18506cd9a7dSYinghai Lu { 18606cd9a7dSYinghai Lu } 18706cd9a7dSYinghai Lu static inline void enable_x2apic(void) 18806cd9a7dSYinghai Lu { 18906cd9a7dSYinghai Lu } 19006cd9a7dSYinghai Lu static inline void enable_IR_x2apic(void) 19106cd9a7dSYinghai Lu { 19206cd9a7dSYinghai Lu } 19306cd9a7dSYinghai Lu static inline int x2apic_enabled(void) 19406cd9a7dSYinghai Lu { 19506cd9a7dSYinghai Lu return 0; 19606cd9a7dSYinghai Lu } 197cf6567feSSuresh Siddha 198cf6567feSSuresh Siddha #define x2apic 0 199cf6567feSSuresh Siddha 200bb898558SAl Viro #endif 201bb898558SAl Viro 202bb898558SAl Viro extern int get_physical_broadcast(void); 203bb898558SAl Viro 20406cd9a7dSYinghai Lu #ifdef CONFIG_X86_X2APIC 205bb898558SAl Viro static inline void ack_x2APIC_irq(void) 206bb898558SAl Viro { 207bb898558SAl Viro /* Docs say use 0 for future compatibility */ 208bb898558SAl Viro native_apic_msr_write(APIC_EOI, 0); 209bb898558SAl Viro } 210bb898558SAl Viro #endif 211bb898558SAl Viro 212bb898558SAl Viro extern int lapic_get_maxlvt(void); 213bb898558SAl Viro extern void clear_local_APIC(void); 214bb898558SAl Viro extern void connect_bsp_APIC(void); 215bb898558SAl Viro extern void disconnect_bsp_APIC(int virt_wire_setup); 216bb898558SAl Viro extern void disable_local_APIC(void); 217bb898558SAl Viro extern void lapic_shutdown(void); 218bb898558SAl Viro extern int verify_local_APIC(void); 219bb898558SAl Viro extern void cache_APIC_registers(void); 220bb898558SAl Viro extern void sync_Arb_IDs(void); 221bb898558SAl Viro extern void init_bsp_APIC(void); 222bb898558SAl Viro extern void setup_local_APIC(void); 223bb898558SAl Viro extern void end_local_APIC_setup(void); 224bb898558SAl Viro extern void init_apic_mappings(void); 225bb898558SAl Viro extern void setup_boot_APIC_clock(void); 226bb898558SAl Viro extern void setup_secondary_APIC_clock(void); 227bb898558SAl Viro extern int APIC_init_uniprocessor(void); 228bb898558SAl Viro extern void enable_NMI_through_LVT0(void); 229bb898558SAl Viro 230bb898558SAl Viro /* 231bb898558SAl Viro * On 32bit this is mach-xxx local 232bb898558SAl Viro */ 233bb898558SAl Viro #ifdef CONFIG_X86_64 234bb898558SAl Viro extern void early_init_lapic_mapping(void); 235bb898558SAl Viro extern int apic_is_clustered_box(void); 236bb898558SAl Viro #else 237bb898558SAl Viro static inline int apic_is_clustered_box(void) 238bb898558SAl Viro { 239bb898558SAl Viro return 0; 240bb898558SAl Viro } 241bb898558SAl Viro #endif 242bb898558SAl Viro 243bb898558SAl Viro extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 244bb898558SAl Viro extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 245bb898558SAl Viro 246bb898558SAl Viro 247bb898558SAl Viro #else /* !CONFIG_X86_LOCAL_APIC */ 248bb898558SAl Viro static inline void lapic_shutdown(void) { } 249bb898558SAl Viro #define local_apic_timer_c2_ok 1 250bb898558SAl Viro static inline void init_apic_mappings(void) { } 251d3ec5caeSIvan Vecera static inline void disable_local_APIC(void) { } 252bb898558SAl Viro 253bb898558SAl Viro #endif /* !CONFIG_X86_LOCAL_APIC */ 254bb898558SAl Viro 2551f75ed0cSIngo Molnar #ifdef CONFIG_X86_64 2561f75ed0cSIngo Molnar #define SET_APIC_ID(x) (apic->set_apic_id(x)) 2571f75ed0cSIngo Molnar #else 2581f75ed0cSIngo Molnar 2591f75ed0cSIngo Molnar #endif 2601f75ed0cSIngo Molnar 261e2780a68SIngo Molnar /* 262e2780a68SIngo Molnar * Copyright 2004 James Cleverdon, IBM. 263e2780a68SIngo Molnar * Subject to the GNU Public License, v.2 264e2780a68SIngo Molnar * 265e2780a68SIngo Molnar * Generic APIC sub-arch data struct. 266e2780a68SIngo Molnar * 267e2780a68SIngo Molnar * Hacked for x86-64 by James Cleverdon from i386 architecture code by 268e2780a68SIngo Molnar * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 269e2780a68SIngo Molnar * James Cleverdon. 270e2780a68SIngo Molnar */ 271be163a15SIngo Molnar struct apic { 272e2780a68SIngo Molnar char *name; 273e2780a68SIngo Molnar 274e2780a68SIngo Molnar int (*probe)(void); 275e2780a68SIngo Molnar int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 276e2780a68SIngo Molnar int (*apic_id_registered)(void); 277e2780a68SIngo Molnar 278e2780a68SIngo Molnar u32 irq_delivery_mode; 279e2780a68SIngo Molnar u32 irq_dest_mode; 280e2780a68SIngo Molnar 281e2780a68SIngo Molnar const struct cpumask *(*target_cpus)(void); 282e2780a68SIngo Molnar 283e2780a68SIngo Molnar int disable_esr; 284e2780a68SIngo Molnar 285e2780a68SIngo Molnar int dest_logical; 286e2780a68SIngo Molnar unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid); 287e2780a68SIngo Molnar unsigned long (*check_apicid_present)(int apicid); 288e2780a68SIngo Molnar 289e2780a68SIngo Molnar void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 290e2780a68SIngo Molnar void (*init_apic_ldr)(void); 291e2780a68SIngo Molnar 292e2780a68SIngo Molnar physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map); 293e2780a68SIngo Molnar 294e2780a68SIngo Molnar void (*setup_apic_routing)(void); 295e2780a68SIngo Molnar int (*multi_timer_check)(int apic, int irq); 296e2780a68SIngo Molnar int (*apicid_to_node)(int logical_apicid); 297e2780a68SIngo Molnar int (*cpu_to_logical_apicid)(int cpu); 298e2780a68SIngo Molnar int (*cpu_present_to_apicid)(int mps_cpu); 299e2780a68SIngo Molnar physid_mask_t (*apicid_to_cpu_present)(int phys_apicid); 300e2780a68SIngo Molnar void (*setup_portio_remap)(void); 301e2780a68SIngo Molnar int (*check_phys_apicid_present)(int boot_cpu_physical_apicid); 302e2780a68SIngo Molnar void (*enable_apic_mode)(void); 303e2780a68SIngo Molnar int (*phys_pkg_id)(int cpuid_apic, int index_msb); 304e2780a68SIngo Molnar 305e2780a68SIngo Molnar /* 306be163a15SIngo Molnar * When one of the next two hooks returns 1 the apic 307e2780a68SIngo Molnar * is switched to this. Essentially they are additional 308e2780a68SIngo Molnar * probe functions: 309e2780a68SIngo Molnar */ 310e2780a68SIngo Molnar int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 311e2780a68SIngo Molnar 312e2780a68SIngo Molnar unsigned int (*get_apic_id)(unsigned long x); 313e2780a68SIngo Molnar unsigned long (*set_apic_id)(unsigned int id); 314e2780a68SIngo Molnar unsigned long apic_id_mask; 315e2780a68SIngo Molnar 316e2780a68SIngo Molnar unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 317e2780a68SIngo Molnar unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 318e2780a68SIngo Molnar const struct cpumask *andmask); 319e2780a68SIngo Molnar 320e2780a68SIngo Molnar /* ipi */ 321e2780a68SIngo Molnar void (*send_IPI_mask)(const struct cpumask *mask, int vector); 322e2780a68SIngo Molnar void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 323e2780a68SIngo Molnar int vector); 324e2780a68SIngo Molnar void (*send_IPI_allbutself)(int vector); 325e2780a68SIngo Molnar void (*send_IPI_all)(int vector); 326e2780a68SIngo Molnar void (*send_IPI_self)(int vector); 327e2780a68SIngo Molnar 328e2780a68SIngo Molnar /* wakeup_secondary_cpu */ 3291f5bcabfSIngo Molnar int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 330e2780a68SIngo Molnar 331e2780a68SIngo Molnar int trampoline_phys_low; 332e2780a68SIngo Molnar int trampoline_phys_high; 333e2780a68SIngo Molnar 334e2780a68SIngo Molnar void (*wait_for_init_deassert)(atomic_t *deassert); 335e2780a68SIngo Molnar void (*smp_callin_clear_local_apic)(void); 336e2780a68SIngo Molnar void (*inquire_remote_apic)(int apicid); 337e2780a68SIngo Molnar 338e2780a68SIngo Molnar /* apic ops */ 339e2780a68SIngo Molnar u32 (*read)(u32 reg); 340e2780a68SIngo Molnar void (*write)(u32 reg, u32 v); 341e2780a68SIngo Molnar u64 (*icr_read)(void); 342e2780a68SIngo Molnar void (*icr_write)(u32 low, u32 high); 343e2780a68SIngo Molnar void (*wait_icr_idle)(void); 344e2780a68SIngo Molnar u32 (*safe_wait_icr_idle)(void); 345e2780a68SIngo Molnar }; 346e2780a68SIngo Molnar 3470917c01fSIngo Molnar /* 3480917c01fSIngo Molnar * Pointer to the local APIC driver in use on this system (there's 3490917c01fSIngo Molnar * always just one such driver in use - the kernel decides via an 3500917c01fSIngo Molnar * early probing process which one it picks - and then sticks to it): 3510917c01fSIngo Molnar */ 352be163a15SIngo Molnar extern struct apic *apic; 3530917c01fSIngo Molnar 3540917c01fSIngo Molnar /* 3550917c01fSIngo Molnar * APIC functionality to boot other CPUs - only used on SMP: 3560917c01fSIngo Molnar */ 3570917c01fSIngo Molnar #ifdef CONFIG_SMP 3582b6163bfSYinghai Lu extern atomic_t init_deasserted; 3592b6163bfSYinghai Lu extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 3600917c01fSIngo Molnar #endif 361e2780a68SIngo Molnar 362e2780a68SIngo Molnar static inline u32 apic_read(u32 reg) 363e2780a68SIngo Molnar { 364e2780a68SIngo Molnar return apic->read(reg); 365e2780a68SIngo Molnar } 366e2780a68SIngo Molnar 367e2780a68SIngo Molnar static inline void apic_write(u32 reg, u32 val) 368e2780a68SIngo Molnar { 369e2780a68SIngo Molnar apic->write(reg, val); 370e2780a68SIngo Molnar } 371e2780a68SIngo Molnar 372e2780a68SIngo Molnar static inline u64 apic_icr_read(void) 373e2780a68SIngo Molnar { 374e2780a68SIngo Molnar return apic->icr_read(); 375e2780a68SIngo Molnar } 376e2780a68SIngo Molnar 377e2780a68SIngo Molnar static inline void apic_icr_write(u32 low, u32 high) 378e2780a68SIngo Molnar { 379e2780a68SIngo Molnar apic->icr_write(low, high); 380e2780a68SIngo Molnar } 381e2780a68SIngo Molnar 382e2780a68SIngo Molnar static inline void apic_wait_icr_idle(void) 383e2780a68SIngo Molnar { 384e2780a68SIngo Molnar apic->wait_icr_idle(); 385e2780a68SIngo Molnar } 386e2780a68SIngo Molnar 387e2780a68SIngo Molnar static inline u32 safe_apic_wait_icr_idle(void) 388e2780a68SIngo Molnar { 389e2780a68SIngo Molnar return apic->safe_wait_icr_idle(); 390e2780a68SIngo Molnar } 391e2780a68SIngo Molnar 392e2780a68SIngo Molnar 393e2780a68SIngo Molnar static inline void ack_APIC_irq(void) 394e2780a68SIngo Molnar { 395b2b35259SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 396e2780a68SIngo Molnar /* 397e2780a68SIngo Molnar * ack_APIC_irq() actually gets compiled as a single instruction 398e2780a68SIngo Molnar * ... yummie. 399e2780a68SIngo Molnar */ 400e2780a68SIngo Molnar 401e2780a68SIngo Molnar /* Docs say use 0 for future compatibility */ 402e2780a68SIngo Molnar apic_write(APIC_EOI, 0); 403b2b35259SIngo Molnar #endif 404e2780a68SIngo Molnar } 405e2780a68SIngo Molnar 406e2780a68SIngo Molnar static inline unsigned default_get_apic_id(unsigned long x) 407e2780a68SIngo Molnar { 408e2780a68SIngo Molnar unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 409e2780a68SIngo Molnar 410e2780a68SIngo Molnar if (APIC_XAPIC(ver)) 411e2780a68SIngo Molnar return (x >> 24) & 0xFF; 412e2780a68SIngo Molnar else 413e2780a68SIngo Molnar return (x >> 24) & 0x0F; 414e2780a68SIngo Molnar } 415e2780a68SIngo Molnar 416e2780a68SIngo Molnar /* 417e2780a68SIngo Molnar * Warm reset vector default position: 418e2780a68SIngo Molnar */ 419e2780a68SIngo Molnar #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 420e2780a68SIngo Molnar #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 421e2780a68SIngo Molnar 4222b6163bfSYinghai Lu #ifdef CONFIG_X86_64 423be163a15SIngo Molnar extern struct apic apic_flat; 424be163a15SIngo Molnar extern struct apic apic_physflat; 425be163a15SIngo Molnar extern struct apic apic_x2apic_cluster; 426be163a15SIngo Molnar extern struct apic apic_x2apic_phys; 427e2780a68SIngo Molnar extern int default_acpi_madt_oem_check(char *, char *); 428e2780a68SIngo Molnar 429e2780a68SIngo Molnar extern void apic_send_IPI_self(int vector); 430e2780a68SIngo Molnar 431be163a15SIngo Molnar extern struct apic apic_x2apic_uv_x; 432e2780a68SIngo Molnar DECLARE_PER_CPU(int, x2apic_extra_bits); 433e2780a68SIngo Molnar 434e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 435e2780a68SIngo Molnar extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); 436e2780a68SIngo Molnar #endif 437e2780a68SIngo Molnar 438e2780a68SIngo Molnar static inline void default_wait_for_init_deassert(atomic_t *deassert) 439e2780a68SIngo Molnar { 440e2780a68SIngo Molnar while (!atomic_read(deassert)) 441e2780a68SIngo Molnar cpu_relax(); 442e2780a68SIngo Molnar return; 443e2780a68SIngo Molnar } 444e2780a68SIngo Molnar 445e2780a68SIngo Molnar extern void generic_bigsmp_probe(void); 446e2780a68SIngo Molnar 447e2780a68SIngo Molnar 448e2780a68SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 449e2780a68SIngo Molnar 450e2780a68SIngo Molnar #include <asm/smp.h> 451e2780a68SIngo Molnar 452e2780a68SIngo Molnar #define APIC_DFR_VALUE (APIC_DFR_FLAT) 453e2780a68SIngo Molnar 454e2780a68SIngo Molnar static inline const struct cpumask *default_target_cpus(void) 455e2780a68SIngo Molnar { 456e2780a68SIngo Molnar #ifdef CONFIG_SMP 457e2780a68SIngo Molnar return cpu_online_mask; 458e2780a68SIngo Molnar #else 459e2780a68SIngo Molnar return cpumask_of(0); 460e2780a68SIngo Molnar #endif 461e2780a68SIngo Molnar } 462e2780a68SIngo Molnar 463e2780a68SIngo Molnar DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 464e2780a68SIngo Molnar 465e2780a68SIngo Molnar 466e2780a68SIngo Molnar static inline unsigned int read_apic_id(void) 467e2780a68SIngo Molnar { 468e2780a68SIngo Molnar unsigned int reg; 469e2780a68SIngo Molnar 470e2780a68SIngo Molnar reg = apic_read(APIC_ID); 471e2780a68SIngo Molnar 472e2780a68SIngo Molnar return apic->get_apic_id(reg); 473e2780a68SIngo Molnar } 474e2780a68SIngo Molnar 475e2780a68SIngo Molnar extern void default_setup_apic_routing(void); 476e2780a68SIngo Molnar 477e2780a68SIngo Molnar #ifdef CONFIG_X86_32 478e2780a68SIngo Molnar /* 479e2780a68SIngo Molnar * Set up the logical destination ID. 480e2780a68SIngo Molnar * 481e2780a68SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 482e2780a68SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 483e2780a68SIngo Molnar * document number 292116). So here it goes... 484e2780a68SIngo Molnar */ 485e2780a68SIngo Molnar extern void default_init_apic_ldr(void); 486e2780a68SIngo Molnar 487e2780a68SIngo Molnar static inline int default_apic_id_registered(void) 488e2780a68SIngo Molnar { 489e2780a68SIngo Molnar return physid_isset(read_apic_id(), phys_cpu_present_map); 490e2780a68SIngo Molnar } 491e2780a68SIngo Molnar 492f56e5034SYinghai Lu static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 493f56e5034SYinghai Lu { 494f56e5034SYinghai Lu return cpuid_apic >> index_msb; 495f56e5034SYinghai Lu } 496f56e5034SYinghai Lu 497f56e5034SYinghai Lu extern int default_apicid_to_node(int logical_apicid); 498f56e5034SYinghai Lu 499f56e5034SYinghai Lu #endif 500f56e5034SYinghai Lu 501e2780a68SIngo Molnar static inline unsigned int 502e2780a68SIngo Molnar default_cpu_mask_to_apicid(const struct cpumask *cpumask) 503e2780a68SIngo Molnar { 504f56e5034SYinghai Lu return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 505e2780a68SIngo Molnar } 506e2780a68SIngo Molnar 507e2780a68SIngo Molnar static inline unsigned int 508e2780a68SIngo Molnar default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 509e2780a68SIngo Molnar const struct cpumask *andmask) 510e2780a68SIngo Molnar { 511e2780a68SIngo Molnar unsigned long mask1 = cpumask_bits(cpumask)[0]; 512e2780a68SIngo Molnar unsigned long mask2 = cpumask_bits(andmask)[0]; 513e2780a68SIngo Molnar unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 514e2780a68SIngo Molnar 515e2780a68SIngo Molnar return (unsigned int)(mask1 & mask2 & mask3); 516e2780a68SIngo Molnar } 517e2780a68SIngo Molnar 518e2780a68SIngo Molnar static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) 519e2780a68SIngo Molnar { 520e2780a68SIngo Molnar return physid_isset(apicid, bitmap); 521e2780a68SIngo Molnar } 522e2780a68SIngo Molnar 523e2780a68SIngo Molnar static inline unsigned long default_check_apicid_present(int bit) 524e2780a68SIngo Molnar { 525e2780a68SIngo Molnar return physid_isset(bit, phys_cpu_present_map); 526e2780a68SIngo Molnar } 527e2780a68SIngo Molnar 528e2780a68SIngo Molnar static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) 529e2780a68SIngo Molnar { 530e2780a68SIngo Molnar return phys_map; 531e2780a68SIngo Molnar } 532e2780a68SIngo Molnar 533e2780a68SIngo Molnar /* Mapping from cpu number to logical apicid */ 534e2780a68SIngo Molnar static inline int default_cpu_to_logical_apicid(int cpu) 535e2780a68SIngo Molnar { 536e2780a68SIngo Molnar return 1 << cpu; 537e2780a68SIngo Molnar } 538e2780a68SIngo Molnar 539e2780a68SIngo Molnar static inline int __default_cpu_present_to_apicid(int mps_cpu) 540e2780a68SIngo Molnar { 541e2780a68SIngo Molnar if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 542e2780a68SIngo Molnar return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 543e2780a68SIngo Molnar else 544e2780a68SIngo Molnar return BAD_APICID; 545e2780a68SIngo Molnar } 546e2780a68SIngo Molnar 547e2780a68SIngo Molnar static inline int 548e2780a68SIngo Molnar __default_check_phys_apicid_present(int boot_cpu_physical_apicid) 549e2780a68SIngo Molnar { 550e2780a68SIngo Molnar return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); 551e2780a68SIngo Molnar } 552e2780a68SIngo Molnar 553e2780a68SIngo Molnar #ifdef CONFIG_X86_32 554e2780a68SIngo Molnar static inline int default_cpu_present_to_apicid(int mps_cpu) 555e2780a68SIngo Molnar { 556e2780a68SIngo Molnar return __default_cpu_present_to_apicid(mps_cpu); 557e2780a68SIngo Molnar } 558e2780a68SIngo Molnar 559e2780a68SIngo Molnar static inline int 560e2780a68SIngo Molnar default_check_phys_apicid_present(int boot_cpu_physical_apicid) 561e2780a68SIngo Molnar { 562e2780a68SIngo Molnar return __default_check_phys_apicid_present(boot_cpu_physical_apicid); 563e2780a68SIngo Molnar } 564e2780a68SIngo Molnar #else 565e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 566e2780a68SIngo Molnar extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); 567e2780a68SIngo Molnar #endif 568e2780a68SIngo Molnar 569e2780a68SIngo Molnar static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) 570e2780a68SIngo Molnar { 571e2780a68SIngo Molnar return physid_mask_of_physid(phys_apicid); 572e2780a68SIngo Molnar } 573e2780a68SIngo Molnar 574e2780a68SIngo Molnar #endif /* CONFIG_X86_LOCAL_APIC */ 575e2780a68SIngo Molnar 5762f205bc4SIngo Molnar #ifdef CONFIG_X86_32 5772f205bc4SIngo Molnar extern u8 cpu_2_logical_apicid[NR_CPUS]; 5782f205bc4SIngo Molnar #endif 5792f205bc4SIngo Molnar 5801965aae3SH. Peter Anvin #endif /* _ASM_X86_APIC_H */ 581