11965aae3SH. Peter Anvin #ifndef _ASM_X86_APIC_H 21965aae3SH. Peter Anvin #define _ASM_X86_APIC_H 3bb898558SAl Viro 4e2780a68SIngo Molnar #include <linux/cpumask.h> 5e2780a68SIngo Molnar #include <linux/pm.h> 6bb898558SAl Viro 7bb898558SAl Viro #include <asm/alternative.h> 8bb898558SAl Viro #include <asm/cpufeature.h> 9e2780a68SIngo Molnar #include <asm/processor.h> 10e2780a68SIngo Molnar #include <asm/apicdef.h> 1160063497SArun Sharma #include <linux/atomic.h> 12e2780a68SIngo Molnar #include <asm/fixmap.h> 13e2780a68SIngo Molnar #include <asm/mpspec.h> 14bb898558SAl Viro #include <asm/msr.h> 15eddc0e92SSeiji Aguchi #include <asm/idle.h> 16bb898558SAl Viro 17bb898558SAl Viro #define ARCH_APICTIMER_STOPS_ON_C3 1 18bb898558SAl Viro 19bb898558SAl Viro /* 20bb898558SAl Viro * Debugging macros 21bb898558SAl Viro */ 22bb898558SAl Viro #define APIC_QUIET 0 23bb898558SAl Viro #define APIC_VERBOSE 1 24bb898558SAl Viro #define APIC_DEBUG 2 25bb898558SAl Viro 26bb898558SAl Viro /* 27bb898558SAl Viro * Define the default level of output to be very little 28bb898558SAl Viro * This can be turned up by using apic=verbose for more 29bb898558SAl Viro * information and apic=debug for _lots_ of information. 30bb898558SAl Viro * apic_verbosity is defined in apic.c 31bb898558SAl Viro */ 32bb898558SAl Viro #define apic_printk(v, s, a...) do { \ 33bb898558SAl Viro if ((v) <= apic_verbosity) \ 34bb898558SAl Viro printk(s, ##a); \ 35bb898558SAl Viro } while (0) 36bb898558SAl Viro 37bb898558SAl Viro 38160d8dacSIngo Molnar #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39bb898558SAl Viro extern void generic_apic_probe(void); 40160d8dacSIngo Molnar #else 41160d8dacSIngo Molnar static inline void generic_apic_probe(void) 42160d8dacSIngo Molnar { 43160d8dacSIngo Molnar } 44160d8dacSIngo Molnar #endif 45bb898558SAl Viro 46bb898558SAl Viro #ifdef CONFIG_X86_LOCAL_APIC 47bb898558SAl Viro 48bb898558SAl Viro extern unsigned int apic_verbosity; 49bb898558SAl Viro extern int local_apic_timer_c2_ok; 50bb898558SAl Viro 51bb898558SAl Viro extern int disable_apic; 521ade93efSJacob Pan extern unsigned int lapic_timer_frequency; 530939e4fdSIngo Molnar 540939e4fdSIngo Molnar #ifdef CONFIG_SMP 550939e4fdSIngo Molnar extern void __inquire_remote_apic(int apicid); 560939e4fdSIngo Molnar #else /* CONFIG_SMP */ 570939e4fdSIngo Molnar static inline void __inquire_remote_apic(int apicid) 580939e4fdSIngo Molnar { 590939e4fdSIngo Molnar } 600939e4fdSIngo Molnar #endif /* CONFIG_SMP */ 610939e4fdSIngo Molnar 620939e4fdSIngo Molnar static inline void default_inquire_remote_apic(int apicid) 630939e4fdSIngo Molnar { 640939e4fdSIngo Molnar if (apic_verbosity >= APIC_DEBUG) 650939e4fdSIngo Molnar __inquire_remote_apic(apicid); 660939e4fdSIngo Molnar } 670939e4fdSIngo Molnar 68bb898558SAl Viro /* 698312136fSCyrill Gorcunov * With 82489DX we can't rely on apic feature bit 708312136fSCyrill Gorcunov * retrieved via cpuid but still have to deal with 718312136fSCyrill Gorcunov * such an apic chip so we assume that SMP configuration 728312136fSCyrill Gorcunov * is found from MP table (64bit case uses ACPI mostly 738312136fSCyrill Gorcunov * which set smp presence flag as well so we are safe 748312136fSCyrill Gorcunov * to use this helper too). 758312136fSCyrill Gorcunov */ 768312136fSCyrill Gorcunov static inline bool apic_from_smp_config(void) 778312136fSCyrill Gorcunov { 788312136fSCyrill Gorcunov return smp_found_config && !disable_apic; 798312136fSCyrill Gorcunov } 808312136fSCyrill Gorcunov 818312136fSCyrill Gorcunov /* 82bb898558SAl Viro * Basic functions accessing APICs. 83bb898558SAl Viro */ 84bb898558SAl Viro #ifdef CONFIG_PARAVIRT 85bb898558SAl Viro #include <asm/paravirt.h> 86bb898558SAl Viro #endif 87bb898558SAl Viro 88bb898558SAl Viro extern int setup_profiling_timer(unsigned int); 89bb898558SAl Viro 90bb898558SAl Viro static inline void native_apic_mem_write(u32 reg, u32 v) 91bb898558SAl Viro { 92bb898558SAl Viro volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 93bb898558SAl Viro 94a930dc45SBorislav Petkov alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 95bb898558SAl Viro ASM_OUTPUT2("=r" (v), "=m" (*addr)), 96bb898558SAl Viro ASM_OUTPUT2("0" (v), "m" (*addr))); 97bb898558SAl Viro } 98bb898558SAl Viro 99bb898558SAl Viro static inline u32 native_apic_mem_read(u32 reg) 100bb898558SAl Viro { 101bb898558SAl Viro return *((volatile u32 *)(APIC_BASE + reg)); 102bb898558SAl Viro } 103bb898558SAl Viro 104c1eeb2deSYinghai Lu extern void native_apic_wait_icr_idle(void); 105c1eeb2deSYinghai Lu extern u32 native_safe_apic_wait_icr_idle(void); 106c1eeb2deSYinghai Lu extern void native_apic_icr_write(u32 low, u32 id); 107c1eeb2deSYinghai Lu extern u64 native_apic_icr_read(void); 108c1eeb2deSYinghai Lu 1098d806960SThomas Gleixner static inline bool apic_is_x2apic_enabled(void) 1108d806960SThomas Gleixner { 1118d806960SThomas Gleixner u64 msr; 1128d806960SThomas Gleixner 1138d806960SThomas Gleixner if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 1148d806960SThomas Gleixner return false; 1158d806960SThomas Gleixner return msr & X2APIC_ENABLE; 1168d806960SThomas Gleixner } 1178d806960SThomas Gleixner 118e02ae387SPaolo Bonzini extern void enable_IR_x2apic(void); 119e02ae387SPaolo Bonzini 120e02ae387SPaolo Bonzini extern int get_physical_broadcast(void); 121e02ae387SPaolo Bonzini 122e02ae387SPaolo Bonzini extern int lapic_get_maxlvt(void); 123e02ae387SPaolo Bonzini extern void clear_local_APIC(void); 124e02ae387SPaolo Bonzini extern void disconnect_bsp_APIC(int virt_wire_setup); 125e02ae387SPaolo Bonzini extern void disable_local_APIC(void); 126e02ae387SPaolo Bonzini extern void lapic_shutdown(void); 127e02ae387SPaolo Bonzini extern void sync_Arb_IDs(void); 128e02ae387SPaolo Bonzini extern void init_bsp_APIC(void); 129e02ae387SPaolo Bonzini extern void setup_local_APIC(void); 130e02ae387SPaolo Bonzini extern void init_apic_mappings(void); 131e02ae387SPaolo Bonzini void register_lapic_address(unsigned long address); 132e02ae387SPaolo Bonzini extern void setup_boot_APIC_clock(void); 133e02ae387SPaolo Bonzini extern void setup_secondary_APIC_clock(void); 134e02ae387SPaolo Bonzini extern int APIC_init_uniprocessor(void); 135e02ae387SPaolo Bonzini 136e02ae387SPaolo Bonzini #ifdef CONFIG_X86_64 137e02ae387SPaolo Bonzini static inline int apic_force_enable(unsigned long addr) 138e02ae387SPaolo Bonzini { 139e02ae387SPaolo Bonzini return -1; 140e02ae387SPaolo Bonzini } 141e02ae387SPaolo Bonzini #else 142e02ae387SPaolo Bonzini extern int apic_force_enable(unsigned long addr); 143e02ae387SPaolo Bonzini #endif 144e02ae387SPaolo Bonzini 145e02ae387SPaolo Bonzini extern int apic_bsp_setup(bool upmode); 146e02ae387SPaolo Bonzini extern void apic_ap_setup(void); 147e02ae387SPaolo Bonzini 148e02ae387SPaolo Bonzini /* 149e02ae387SPaolo Bonzini * On 32bit this is mach-xxx local 150e02ae387SPaolo Bonzini */ 151e02ae387SPaolo Bonzini #ifdef CONFIG_X86_64 152e02ae387SPaolo Bonzini extern int apic_is_clustered_box(void); 153e02ae387SPaolo Bonzini #else 154e02ae387SPaolo Bonzini static inline int apic_is_clustered_box(void) 155e02ae387SPaolo Bonzini { 156e02ae387SPaolo Bonzini return 0; 157e02ae387SPaolo Bonzini } 158e02ae387SPaolo Bonzini #endif 159e02ae387SPaolo Bonzini 160e02ae387SPaolo Bonzini extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 161e02ae387SPaolo Bonzini 162e02ae387SPaolo Bonzini #else /* !CONFIG_X86_LOCAL_APIC */ 163e02ae387SPaolo Bonzini static inline void lapic_shutdown(void) { } 164e02ae387SPaolo Bonzini #define local_apic_timer_c2_ok 1 165e02ae387SPaolo Bonzini static inline void init_apic_mappings(void) { } 166e02ae387SPaolo Bonzini static inline void disable_local_APIC(void) { } 167e02ae387SPaolo Bonzini # define setup_boot_APIC_clock x86_init_noop 168e02ae387SPaolo Bonzini # define setup_secondary_APIC_clock x86_init_noop 169e02ae387SPaolo Bonzini #endif /* !CONFIG_X86_LOCAL_APIC */ 170e02ae387SPaolo Bonzini 171d0b03bd1SHan, Weidong #ifdef CONFIG_X86_X2APIC 172ce4e240cSSuresh Siddha /* 173ce4e240cSSuresh Siddha * Make previous memory operations globally visible before 174ce4e240cSSuresh Siddha * sending the IPI through x2apic wrmsr. We need a serializing instruction or 175ce4e240cSSuresh Siddha * mfence for this. 176ce4e240cSSuresh Siddha */ 177ce4e240cSSuresh Siddha static inline void x2apic_wrmsr_fence(void) 178ce4e240cSSuresh Siddha { 179ce4e240cSSuresh Siddha asm volatile("mfence" : : : "memory"); 180ce4e240cSSuresh Siddha } 181ce4e240cSSuresh Siddha 182bb898558SAl Viro static inline void native_apic_msr_write(u32 reg, u32 v) 183bb898558SAl Viro { 184bb898558SAl Viro if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 185bb898558SAl Viro reg == APIC_LVR) 186bb898558SAl Viro return; 187bb898558SAl Viro 188bb898558SAl Viro wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 189bb898558SAl Viro } 190bb898558SAl Viro 1910ab711aeSMichael S. Tsirkin static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 1920ab711aeSMichael S. Tsirkin { 1930ab711aeSMichael S. Tsirkin wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 1940ab711aeSMichael S. Tsirkin } 1950ab711aeSMichael S. Tsirkin 196bb898558SAl Viro static inline u32 native_apic_msr_read(u32 reg) 197bb898558SAl Viro { 1980059b243SAndi Kleen u64 msr; 199bb898558SAl Viro 200bb898558SAl Viro if (reg == APIC_DFR) 201bb898558SAl Viro return -1; 202bb898558SAl Viro 2030059b243SAndi Kleen rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 2040059b243SAndi Kleen return (u32)msr; 205bb898558SAl Viro } 206bb898558SAl Viro 207c1eeb2deSYinghai Lu static inline void native_x2apic_wait_icr_idle(void) 208c1eeb2deSYinghai Lu { 209c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 210c1eeb2deSYinghai Lu return; 211c1eeb2deSYinghai Lu } 212c1eeb2deSYinghai Lu 213c1eeb2deSYinghai Lu static inline u32 native_safe_x2apic_wait_icr_idle(void) 214c1eeb2deSYinghai Lu { 215c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 216c1eeb2deSYinghai Lu return 0; 217c1eeb2deSYinghai Lu } 218c1eeb2deSYinghai Lu 219c1eeb2deSYinghai Lu static inline void native_x2apic_icr_write(u32 low, u32 id) 220c1eeb2deSYinghai Lu { 221c1eeb2deSYinghai Lu wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 222c1eeb2deSYinghai Lu } 223c1eeb2deSYinghai Lu 224c1eeb2deSYinghai Lu static inline u64 native_x2apic_icr_read(void) 225c1eeb2deSYinghai Lu { 226c1eeb2deSYinghai Lu unsigned long val; 227c1eeb2deSYinghai Lu 228c1eeb2deSYinghai Lu rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 229c1eeb2deSYinghai Lu return val; 230c1eeb2deSYinghai Lu } 231c1eeb2deSYinghai Lu 23281a46dd8SThomas Gleixner extern int x2apic_mode; 233fc1edaf9SSuresh Siddha extern int x2apic_phys; 234d524165cSThomas Gleixner extern void __init check_x2apic(void); 235659006bfSThomas Gleixner extern void x2apic_setup(void); 236bb898558SAl Viro static inline int x2apic_enabled(void) 237bb898558SAl Viro { 2388d806960SThomas Gleixner return cpu_has_x2apic && apic_is_x2apic_enabled(); 239bb898558SAl Viro } 240fc1edaf9SSuresh Siddha 241fc1edaf9SSuresh Siddha #define x2apic_supported() (cpu_has_x2apic) 242e02ae387SPaolo Bonzini #else /* !CONFIG_X86_X2APIC */ 24355eae7deSThomas Gleixner static inline void check_x2apic(void) { } 244659006bfSThomas Gleixner static inline void x2apic_setup(void) { } 24555eae7deSThomas Gleixner static inline int x2apic_enabled(void) { return 0; } 246cf6567feSSuresh Siddha 24781a46dd8SThomas Gleixner #define x2apic_mode (0) 24881a46dd8SThomas Gleixner #define x2apic_supported() (0) 249e02ae387SPaolo Bonzini #endif /* !CONFIG_X86_X2APIC */ 250bb898558SAl Viro 2511f75ed0cSIngo Molnar #ifdef CONFIG_X86_64 2521f75ed0cSIngo Molnar #define SET_APIC_ID(x) (apic->set_apic_id(x)) 2531f75ed0cSIngo Molnar #else 2541f75ed0cSIngo Molnar 2551f75ed0cSIngo Molnar #endif 2561f75ed0cSIngo Molnar 257e2780a68SIngo Molnar /* 258e2780a68SIngo Molnar * Copyright 2004 James Cleverdon, IBM. 259e2780a68SIngo Molnar * Subject to the GNU Public License, v.2 260e2780a68SIngo Molnar * 261e2780a68SIngo Molnar * Generic APIC sub-arch data struct. 262e2780a68SIngo Molnar * 263e2780a68SIngo Molnar * Hacked for x86-64 by James Cleverdon from i386 architecture code by 264e2780a68SIngo Molnar * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 265e2780a68SIngo Molnar * James Cleverdon. 266e2780a68SIngo Molnar */ 267be163a15SIngo Molnar struct apic { 268e2780a68SIngo Molnar char *name; 269e2780a68SIngo Molnar 270e2780a68SIngo Molnar int (*probe)(void); 271e2780a68SIngo Molnar int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 272fa63030eSDaniel J Blueman int (*apic_id_valid)(int apicid); 273e2780a68SIngo Molnar int (*apic_id_registered)(void); 274e2780a68SIngo Molnar 275e2780a68SIngo Molnar u32 irq_delivery_mode; 276e2780a68SIngo Molnar u32 irq_dest_mode; 277e2780a68SIngo Molnar 278e2780a68SIngo Molnar const struct cpumask *(*target_cpus)(void); 279e2780a68SIngo Molnar 280e2780a68SIngo Molnar int disable_esr; 281e2780a68SIngo Molnar 282e2780a68SIngo Molnar int dest_logical; 2837abc0753SCyrill Gorcunov unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 284e2780a68SIngo Molnar 2851ac322d0SSuresh Siddha void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 2861ac322d0SSuresh Siddha const struct cpumask *mask); 287e2780a68SIngo Molnar void (*init_apic_ldr)(void); 288e2780a68SIngo Molnar 2897abc0753SCyrill Gorcunov void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 290e2780a68SIngo Molnar 291e2780a68SIngo Molnar void (*setup_apic_routing)(void); 292e2780a68SIngo Molnar int (*cpu_present_to_apicid)(int mps_cpu); 2937abc0753SCyrill Gorcunov void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 294e11dadabSThomas Gleixner int (*check_phys_apicid_present)(int phys_apicid); 295e2780a68SIngo Molnar int (*phys_pkg_id)(int cpuid_apic, int index_msb); 296e2780a68SIngo Molnar 297e2780a68SIngo Molnar unsigned int (*get_apic_id)(unsigned long x); 298e2780a68SIngo Molnar unsigned long (*set_apic_id)(unsigned int id); 299e2780a68SIngo Molnar unsigned long apic_id_mask; 300e2780a68SIngo Molnar 301ff164324SAlexander Gordeev int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 302ff164324SAlexander Gordeev const struct cpumask *andmask, 303ff164324SAlexander Gordeev unsigned int *apicid); 304e2780a68SIngo Molnar 305e2780a68SIngo Molnar /* ipi */ 306e2780a68SIngo Molnar void (*send_IPI_mask)(const struct cpumask *mask, int vector); 307e2780a68SIngo Molnar void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 308e2780a68SIngo Molnar int vector); 309e2780a68SIngo Molnar void (*send_IPI_allbutself)(int vector); 310e2780a68SIngo Molnar void (*send_IPI_all)(int vector); 311e2780a68SIngo Molnar void (*send_IPI_self)(int vector); 312e2780a68SIngo Molnar 313e2780a68SIngo Molnar /* wakeup_secondary_cpu */ 3141f5bcabfSIngo Molnar int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 315e2780a68SIngo Molnar 316e2780a68SIngo Molnar void (*inquire_remote_apic)(int apicid); 317e2780a68SIngo Molnar 318e2780a68SIngo Molnar /* apic ops */ 319e2780a68SIngo Molnar u32 (*read)(u32 reg); 320e2780a68SIngo Molnar void (*write)(u32 reg, u32 v); 3212a43195dSMichael S. Tsirkin /* 3222a43195dSMichael S. Tsirkin * ->eoi_write() has the same signature as ->write(). 3232a43195dSMichael S. Tsirkin * 3242a43195dSMichael S. Tsirkin * Drivers can support both ->eoi_write() and ->write() by passing the same 3252a43195dSMichael S. Tsirkin * callback value. Kernel can override ->eoi_write() and fall back 3262a43195dSMichael S. Tsirkin * on write for EOI. 3272a43195dSMichael S. Tsirkin */ 3282a43195dSMichael S. Tsirkin void (*eoi_write)(u32 reg, u32 v); 329e2780a68SIngo Molnar u64 (*icr_read)(void); 330e2780a68SIngo Molnar void (*icr_write)(u32 low, u32 high); 331e2780a68SIngo Molnar void (*wait_icr_idle)(void); 332e2780a68SIngo Molnar u32 (*safe_wait_icr_idle)(void); 333acb8bc09STejun Heo 334acb8bc09STejun Heo #ifdef CONFIG_X86_32 335acb8bc09STejun Heo /* 336acb8bc09STejun Heo * Called very early during boot from get_smp_config(). It should 337acb8bc09STejun Heo * return the logical apicid. x86_[bios]_cpu_to_apicid is 338acb8bc09STejun Heo * initialized before this function is called. 339acb8bc09STejun Heo * 340acb8bc09STejun Heo * If logical apicid can't be determined that early, the function 341acb8bc09STejun Heo * may return BAD_APICID. Logical apicid will be configured after 342acb8bc09STejun Heo * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 343acb8bc09STejun Heo * won't be applied properly during early boot in this case. 344acb8bc09STejun Heo */ 345acb8bc09STejun Heo int (*x86_32_early_logical_apicid)(int cpu); 346acb8bc09STejun Heo #endif 347e2780a68SIngo Molnar }; 348e2780a68SIngo Molnar 3490917c01fSIngo Molnar /* 3500917c01fSIngo Molnar * Pointer to the local APIC driver in use on this system (there's 3510917c01fSIngo Molnar * always just one such driver in use - the kernel decides via an 3520917c01fSIngo Molnar * early probing process which one it picks - and then sticks to it): 3530917c01fSIngo Molnar */ 354be163a15SIngo Molnar extern struct apic *apic; 3550917c01fSIngo Molnar 3560917c01fSIngo Molnar /* 357107e0e0cSSuresh Siddha * APIC drivers are probed based on how they are listed in the .apicdrivers 358107e0e0cSSuresh Siddha * section. So the order is important and enforced by the ordering 359107e0e0cSSuresh Siddha * of different apic driver files in the Makefile. 360107e0e0cSSuresh Siddha * 361107e0e0cSSuresh Siddha * For the files having two apic drivers, we use apic_drivers() 362107e0e0cSSuresh Siddha * to enforce the order with in them. 363107e0e0cSSuresh Siddha */ 364107e0e0cSSuresh Siddha #define apic_driver(sym) \ 36575fdd155SAndi Kleen static const struct apic *__apicdrivers_##sym __used \ 366107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 367107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym } 368107e0e0cSSuresh Siddha 369107e0e0cSSuresh Siddha #define apic_drivers(sym1, sym2) \ 370107e0e0cSSuresh Siddha static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 371107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 372107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym1, &sym2 } 373107e0e0cSSuresh Siddha 374107e0e0cSSuresh Siddha extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 375107e0e0cSSuresh Siddha 376107e0e0cSSuresh Siddha /* 3770917c01fSIngo Molnar * APIC functionality to boot other CPUs - only used on SMP: 3780917c01fSIngo Molnar */ 3790917c01fSIngo Molnar #ifdef CONFIG_SMP 3802b6163bfSYinghai Lu extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 3810917c01fSIngo Molnar #endif 382e2780a68SIngo Molnar 383d674cd19SCyrill Gorcunov #ifdef CONFIG_X86_LOCAL_APIC 384346b46beSFernando Luis Vázquez Cao 385e2780a68SIngo Molnar static inline u32 apic_read(u32 reg) 386e2780a68SIngo Molnar { 387e2780a68SIngo Molnar return apic->read(reg); 388e2780a68SIngo Molnar } 389e2780a68SIngo Molnar 390e2780a68SIngo Molnar static inline void apic_write(u32 reg, u32 val) 391e2780a68SIngo Molnar { 392e2780a68SIngo Molnar apic->write(reg, val); 393e2780a68SIngo Molnar } 394e2780a68SIngo Molnar 3952a43195dSMichael S. Tsirkin static inline void apic_eoi(void) 3962a43195dSMichael S. Tsirkin { 3972a43195dSMichael S. Tsirkin apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 3982a43195dSMichael S. Tsirkin } 3992a43195dSMichael S. Tsirkin 400e2780a68SIngo Molnar static inline u64 apic_icr_read(void) 401e2780a68SIngo Molnar { 402e2780a68SIngo Molnar return apic->icr_read(); 403e2780a68SIngo Molnar } 404e2780a68SIngo Molnar 405e2780a68SIngo Molnar static inline void apic_icr_write(u32 low, u32 high) 406e2780a68SIngo Molnar { 407e2780a68SIngo Molnar apic->icr_write(low, high); 408e2780a68SIngo Molnar } 409e2780a68SIngo Molnar 410e2780a68SIngo Molnar static inline void apic_wait_icr_idle(void) 411e2780a68SIngo Molnar { 412e2780a68SIngo Molnar apic->wait_icr_idle(); 413e2780a68SIngo Molnar } 414e2780a68SIngo Molnar 415e2780a68SIngo Molnar static inline u32 safe_apic_wait_icr_idle(void) 416e2780a68SIngo Molnar { 417e2780a68SIngo Molnar return apic->safe_wait_icr_idle(); 418e2780a68SIngo Molnar } 419e2780a68SIngo Molnar 4201551df64SMichael S. Tsirkin extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 4211551df64SMichael S. Tsirkin 422d674cd19SCyrill Gorcunov #else /* CONFIG_X86_LOCAL_APIC */ 423d674cd19SCyrill Gorcunov 424d674cd19SCyrill Gorcunov static inline u32 apic_read(u32 reg) { return 0; } 425d674cd19SCyrill Gorcunov static inline void apic_write(u32 reg, u32 val) { } 4262a43195dSMichael S. Tsirkin static inline void apic_eoi(void) { } 427d674cd19SCyrill Gorcunov static inline u64 apic_icr_read(void) { return 0; } 428d674cd19SCyrill Gorcunov static inline void apic_icr_write(u32 low, u32 high) { } 429d674cd19SCyrill Gorcunov static inline void apic_wait_icr_idle(void) { } 430d674cd19SCyrill Gorcunov static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 4311551df64SMichael S. Tsirkin static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 432d674cd19SCyrill Gorcunov 433d674cd19SCyrill Gorcunov #endif /* CONFIG_X86_LOCAL_APIC */ 434e2780a68SIngo Molnar 435e2780a68SIngo Molnar static inline void ack_APIC_irq(void) 436e2780a68SIngo Molnar { 437e2780a68SIngo Molnar /* 438e2780a68SIngo Molnar * ack_APIC_irq() actually gets compiled as a single instruction 439e2780a68SIngo Molnar * ... yummie. 440e2780a68SIngo Molnar */ 4412a43195dSMichael S. Tsirkin apic_eoi(); 442e2780a68SIngo Molnar } 443e2780a68SIngo Molnar 444e2780a68SIngo Molnar static inline unsigned default_get_apic_id(unsigned long x) 445e2780a68SIngo Molnar { 446e2780a68SIngo Molnar unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 447e2780a68SIngo Molnar 44842937e81SAndreas Herrmann if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 449e2780a68SIngo Molnar return (x >> 24) & 0xFF; 450e2780a68SIngo Molnar else 451e2780a68SIngo Molnar return (x >> 24) & 0x0F; 452e2780a68SIngo Molnar } 453e2780a68SIngo Molnar 454e2780a68SIngo Molnar /* 4556ab1b27cSDavid Rientjes * Warm reset vector position: 456e2780a68SIngo Molnar */ 4576ab1b27cSDavid Rientjes #define TRAMPOLINE_PHYS_LOW 0x467 4586ab1b27cSDavid Rientjes #define TRAMPOLINE_PHYS_HIGH 0x469 459e2780a68SIngo Molnar 4602b6163bfSYinghai Lu #ifdef CONFIG_X86_64 461e2780a68SIngo Molnar extern void apic_send_IPI_self(int vector); 462e2780a68SIngo Molnar 463e2780a68SIngo Molnar DECLARE_PER_CPU(int, x2apic_extra_bits); 464e2780a68SIngo Molnar 465e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 466e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 467e2780a68SIngo Molnar #endif 468e2780a68SIngo Molnar 469838312beSJan Beulich extern void generic_bigsmp_probe(void); 470e2780a68SIngo Molnar 471e2780a68SIngo Molnar 472e2780a68SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 473e2780a68SIngo Molnar 474e2780a68SIngo Molnar #include <asm/smp.h> 475e2780a68SIngo Molnar 476e2780a68SIngo Molnar #define APIC_DFR_VALUE (APIC_DFR_FLAT) 477e2780a68SIngo Molnar 478e2780a68SIngo Molnar static inline const struct cpumask *default_target_cpus(void) 479e2780a68SIngo Molnar { 480e2780a68SIngo Molnar #ifdef CONFIG_SMP 481e2780a68SIngo Molnar return cpu_online_mask; 482e2780a68SIngo Molnar #else 483e2780a68SIngo Molnar return cpumask_of(0); 484e2780a68SIngo Molnar #endif 485e2780a68SIngo Molnar } 486e2780a68SIngo Molnar 487bf721d3aSAlexander Gordeev static inline const struct cpumask *online_target_cpus(void) 488bf721d3aSAlexander Gordeev { 489bf721d3aSAlexander Gordeev return cpu_online_mask; 490bf721d3aSAlexander Gordeev } 491bf721d3aSAlexander Gordeev 4920816b0f0SVlad Zolotarov DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 493e2780a68SIngo Molnar 494e2780a68SIngo Molnar 495e2780a68SIngo Molnar static inline unsigned int read_apic_id(void) 496e2780a68SIngo Molnar { 497e2780a68SIngo Molnar unsigned int reg; 498e2780a68SIngo Molnar 499e2780a68SIngo Molnar reg = apic_read(APIC_ID); 500e2780a68SIngo Molnar 501e2780a68SIngo Molnar return apic->get_apic_id(reg); 502e2780a68SIngo Molnar } 503e2780a68SIngo Molnar 504fa63030eSDaniel J Blueman static inline int default_apic_id_valid(int apicid) 505fa63030eSDaniel J Blueman { 506b7157acfSSteffen Persvold return (apicid < 255); 507fa63030eSDaniel J Blueman } 508fa63030eSDaniel J Blueman 509a491cc90SJiang Liu extern int default_acpi_madt_oem_check(char *, char *); 510a491cc90SJiang Liu 511e2780a68SIngo Molnar extern void default_setup_apic_routing(void); 512e2780a68SIngo Molnar 5139844ab11SCyrill Gorcunov extern struct apic apic_noop; 5149844ab11SCyrill Gorcunov 515e2780a68SIngo Molnar #ifdef CONFIG_X86_32 5162c1b284eSJaswinder Singh Rajput 517acb8bc09STejun Heo static inline int noop_x86_32_early_logical_apicid(int cpu) 518acb8bc09STejun Heo { 519acb8bc09STejun Heo return BAD_APICID; 520acb8bc09STejun Heo } 521acb8bc09STejun Heo 522e2780a68SIngo Molnar /* 523e2780a68SIngo Molnar * Set up the logical destination ID. 524e2780a68SIngo Molnar * 525e2780a68SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 526e2780a68SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 527e2780a68SIngo Molnar * document number 292116). So here it goes... 528e2780a68SIngo Molnar */ 529e2780a68SIngo Molnar extern void default_init_apic_ldr(void); 530e2780a68SIngo Molnar 531e2780a68SIngo Molnar static inline int default_apic_id_registered(void) 532e2780a68SIngo Molnar { 533e2780a68SIngo Molnar return physid_isset(read_apic_id(), phys_cpu_present_map); 534e2780a68SIngo Molnar } 535e2780a68SIngo Molnar 536f56e5034SYinghai Lu static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 537f56e5034SYinghai Lu { 538f56e5034SYinghai Lu return cpuid_apic >> index_msb; 539f56e5034SYinghai Lu } 540f56e5034SYinghai Lu 541f56e5034SYinghai Lu #endif 542f56e5034SYinghai Lu 543ff164324SAlexander Gordeev static inline int 544a5a39156SAlexander Gordeev flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 545a5a39156SAlexander Gordeev const struct cpumask *andmask, 546a5a39156SAlexander Gordeev unsigned int *apicid) 547e2780a68SIngo Molnar { 548a5a39156SAlexander Gordeev unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 549a5a39156SAlexander Gordeev cpumask_bits(andmask)[0] & 550a5a39156SAlexander Gordeev cpumask_bits(cpu_online_mask)[0] & 551a5a39156SAlexander Gordeev APIC_ALL_CPUS; 552a5a39156SAlexander Gordeev 553ff164324SAlexander Gordeev if (likely(cpu_mask)) { 554ff164324SAlexander Gordeev *apicid = (unsigned int)cpu_mask; 555ff164324SAlexander Gordeev return 0; 556ff164324SAlexander Gordeev } else { 557ff164324SAlexander Gordeev return -EINVAL; 558ff164324SAlexander Gordeev } 559e2780a68SIngo Molnar } 560e2780a68SIngo Molnar 561ff164324SAlexander Gordeev extern int 5626398268dSAlexander Gordeev default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 563ff164324SAlexander Gordeev const struct cpumask *andmask, 564ff164324SAlexander Gordeev unsigned int *apicid); 5656398268dSAlexander Gordeev 566b39f25a8SSuresh Siddha static inline void 5671ac322d0SSuresh Siddha flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 5681ac322d0SSuresh Siddha const struct cpumask *mask) 5699d8e1066SAlexander Gordeev { 5709d8e1066SAlexander Gordeev /* Careful. Some cpus do not strictly honor the set of cpus 5719d8e1066SAlexander Gordeev * specified in the interrupt destination when using lowest 5729d8e1066SAlexander Gordeev * priority interrupt delivery mode. 5739d8e1066SAlexander Gordeev * 5749d8e1066SAlexander Gordeev * In particular there was a hyperthreading cpu observed to 5759d8e1066SAlexander Gordeev * deliver interrupts to the wrong hyperthread when only one 5769d8e1066SAlexander Gordeev * hyperthread was specified in the interrupt desitination. 5779d8e1066SAlexander Gordeev */ 5789d8e1066SAlexander Gordeev cpumask_clear(retmask); 5799d8e1066SAlexander Gordeev cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 5809d8e1066SAlexander Gordeev } 5819d8e1066SAlexander Gordeev 582b39f25a8SSuresh Siddha static inline void 5831ac322d0SSuresh Siddha default_vector_allocation_domain(int cpu, struct cpumask *retmask, 5841ac322d0SSuresh Siddha const struct cpumask *mask) 5859d8e1066SAlexander Gordeev { 5869d8e1066SAlexander Gordeev cpumask_copy(retmask, cpumask_of(cpu)); 5879d8e1066SAlexander Gordeev } 5889d8e1066SAlexander Gordeev 5897abc0753SCyrill Gorcunov static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 590e2780a68SIngo Molnar { 5917abc0753SCyrill Gorcunov return physid_isset(apicid, *map); 592e2780a68SIngo Molnar } 593e2780a68SIngo Molnar 5947abc0753SCyrill Gorcunov static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 595e2780a68SIngo Molnar { 5967abc0753SCyrill Gorcunov *retmap = *phys_map; 597e2780a68SIngo Molnar } 598e2780a68SIngo Molnar 599e2780a68SIngo Molnar static inline int __default_cpu_present_to_apicid(int mps_cpu) 600e2780a68SIngo Molnar { 601e2780a68SIngo Molnar if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 602e2780a68SIngo Molnar return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 603e2780a68SIngo Molnar else 604e2780a68SIngo Molnar return BAD_APICID; 605e2780a68SIngo Molnar } 606e2780a68SIngo Molnar 607e2780a68SIngo Molnar static inline int 608e11dadabSThomas Gleixner __default_check_phys_apicid_present(int phys_apicid) 609e2780a68SIngo Molnar { 610e11dadabSThomas Gleixner return physid_isset(phys_apicid, phys_cpu_present_map); 611e2780a68SIngo Molnar } 612e2780a68SIngo Molnar 613e2780a68SIngo Molnar #ifdef CONFIG_X86_32 614e2780a68SIngo Molnar static inline int default_cpu_present_to_apicid(int mps_cpu) 615e2780a68SIngo Molnar { 616e2780a68SIngo Molnar return __default_cpu_present_to_apicid(mps_cpu); 617e2780a68SIngo Molnar } 618e2780a68SIngo Molnar 619e2780a68SIngo Molnar static inline int 620e11dadabSThomas Gleixner default_check_phys_apicid_present(int phys_apicid) 621e2780a68SIngo Molnar { 622e11dadabSThomas Gleixner return __default_check_phys_apicid_present(phys_apicid); 623e2780a68SIngo Molnar } 624e2780a68SIngo Molnar #else 625e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 626e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 627e2780a68SIngo Molnar #endif 628e2780a68SIngo Molnar 629e2780a68SIngo Molnar #endif /* CONFIG_X86_LOCAL_APIC */ 630eddc0e92SSeiji Aguchi extern void irq_enter(void); 631eddc0e92SSeiji Aguchi extern void irq_exit(void); 632eddc0e92SSeiji Aguchi 633eddc0e92SSeiji Aguchi static inline void entering_irq(void) 634eddc0e92SSeiji Aguchi { 635eddc0e92SSeiji Aguchi irq_enter(); 636eddc0e92SSeiji Aguchi exit_idle(); 637eddc0e92SSeiji Aguchi } 638eddc0e92SSeiji Aguchi 639eddc0e92SSeiji Aguchi static inline void entering_ack_irq(void) 640eddc0e92SSeiji Aguchi { 641eddc0e92SSeiji Aguchi ack_APIC_irq(); 642eddc0e92SSeiji Aguchi entering_irq(); 643eddc0e92SSeiji Aguchi } 644eddc0e92SSeiji Aguchi 6456dc17876SThomas Gleixner static inline void ipi_entering_ack_irq(void) 6466dc17876SThomas Gleixner { 6476dc17876SThomas Gleixner ack_APIC_irq(); 6486dc17876SThomas Gleixner irq_enter(); 6496dc17876SThomas Gleixner } 6506dc17876SThomas Gleixner 651eddc0e92SSeiji Aguchi static inline void exiting_irq(void) 652eddc0e92SSeiji Aguchi { 653eddc0e92SSeiji Aguchi irq_exit(); 654eddc0e92SSeiji Aguchi } 655eddc0e92SSeiji Aguchi 656eddc0e92SSeiji Aguchi static inline void exiting_ack_irq(void) 657eddc0e92SSeiji Aguchi { 658eddc0e92SSeiji Aguchi irq_exit(); 659eddc0e92SSeiji Aguchi /* Ack only at the end to avoid potential reentry */ 660eddc0e92SSeiji Aguchi ack_APIC_irq(); 661eddc0e92SSeiji Aguchi } 662e2780a68SIngo Molnar 66317405453SYoshihiro YUNOMAE extern void ioapic_zap_locks(void); 66417405453SYoshihiro YUNOMAE 6651965aae3SH. Peter Anvin #endif /* _ASM_X86_APIC_H */ 666