11965aae3SH. Peter Anvin #ifndef _ASM_X86_APIC_H 21965aae3SH. Peter Anvin #define _ASM_X86_APIC_H 3bb898558SAl Viro 4e2780a68SIngo Molnar #include <linux/cpumask.h> 5e2780a68SIngo Molnar #include <linux/pm.h> 6bb898558SAl Viro 7bb898558SAl Viro #include <asm/alternative.h> 8bb898558SAl Viro #include <asm/cpufeature.h> 9e2780a68SIngo Molnar #include <asm/processor.h> 10e2780a68SIngo Molnar #include <asm/apicdef.h> 1160063497SArun Sharma #include <linux/atomic.h> 12e2780a68SIngo Molnar #include <asm/fixmap.h> 13e2780a68SIngo Molnar #include <asm/mpspec.h> 14bb898558SAl Viro #include <asm/msr.h> 15eddc0e92SSeiji Aguchi #include <asm/idle.h> 16bb898558SAl Viro 17bb898558SAl Viro #define ARCH_APICTIMER_STOPS_ON_C3 1 18bb898558SAl Viro 19bb898558SAl Viro /* 20bb898558SAl Viro * Debugging macros 21bb898558SAl Viro */ 22bb898558SAl Viro #define APIC_QUIET 0 23bb898558SAl Viro #define APIC_VERBOSE 1 24bb898558SAl Viro #define APIC_DEBUG 2 25bb898558SAl Viro 26bb898558SAl Viro /* 27bb898558SAl Viro * Define the default level of output to be very little 28bb898558SAl Viro * This can be turned up by using apic=verbose for more 29bb898558SAl Viro * information and apic=debug for _lots_ of information. 30bb898558SAl Viro * apic_verbosity is defined in apic.c 31bb898558SAl Viro */ 32bb898558SAl Viro #define apic_printk(v, s, a...) do { \ 33bb898558SAl Viro if ((v) <= apic_verbosity) \ 34bb898558SAl Viro printk(s, ##a); \ 35bb898558SAl Viro } while (0) 36bb898558SAl Viro 37bb898558SAl Viro 38160d8dacSIngo Molnar #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39bb898558SAl Viro extern void generic_apic_probe(void); 40160d8dacSIngo Molnar #else 41160d8dacSIngo Molnar static inline void generic_apic_probe(void) 42160d8dacSIngo Molnar { 43160d8dacSIngo Molnar } 44160d8dacSIngo Molnar #endif 45bb898558SAl Viro 46bb898558SAl Viro #ifdef CONFIG_X86_LOCAL_APIC 47bb898558SAl Viro 48bb898558SAl Viro extern unsigned int apic_verbosity; 49bb898558SAl Viro extern int local_apic_timer_c2_ok; 50bb898558SAl Viro 51bb898558SAl Viro extern int disable_apic; 521ade93efSJacob Pan extern unsigned int lapic_timer_frequency; 530939e4fdSIngo Molnar 540939e4fdSIngo Molnar #ifdef CONFIG_SMP 550939e4fdSIngo Molnar extern void __inquire_remote_apic(int apicid); 560939e4fdSIngo Molnar #else /* CONFIG_SMP */ 570939e4fdSIngo Molnar static inline void __inquire_remote_apic(int apicid) 580939e4fdSIngo Molnar { 590939e4fdSIngo Molnar } 600939e4fdSIngo Molnar #endif /* CONFIG_SMP */ 610939e4fdSIngo Molnar 620939e4fdSIngo Molnar static inline void default_inquire_remote_apic(int apicid) 630939e4fdSIngo Molnar { 640939e4fdSIngo Molnar if (apic_verbosity >= APIC_DEBUG) 650939e4fdSIngo Molnar __inquire_remote_apic(apicid); 660939e4fdSIngo Molnar } 670939e4fdSIngo Molnar 68bb898558SAl Viro /* 698312136fSCyrill Gorcunov * With 82489DX we can't rely on apic feature bit 708312136fSCyrill Gorcunov * retrieved via cpuid but still have to deal with 718312136fSCyrill Gorcunov * such an apic chip so we assume that SMP configuration 728312136fSCyrill Gorcunov * is found from MP table (64bit case uses ACPI mostly 738312136fSCyrill Gorcunov * which set smp presence flag as well so we are safe 748312136fSCyrill Gorcunov * to use this helper too). 758312136fSCyrill Gorcunov */ 768312136fSCyrill Gorcunov static inline bool apic_from_smp_config(void) 778312136fSCyrill Gorcunov { 788312136fSCyrill Gorcunov return smp_found_config && !disable_apic; 798312136fSCyrill Gorcunov } 808312136fSCyrill Gorcunov 818312136fSCyrill Gorcunov /* 82bb898558SAl Viro * Basic functions accessing APICs. 83bb898558SAl Viro */ 84bb898558SAl Viro #ifdef CONFIG_PARAVIRT 85bb898558SAl Viro #include <asm/paravirt.h> 86bb898558SAl Viro #endif 87bb898558SAl Viro 8870511134SRavikiran G Thirumalai #ifdef CONFIG_X86_64 89bb898558SAl Viro extern int is_vsmp_box(void); 90129d8bc8SYinghai Lu #else 91129d8bc8SYinghai Lu static inline int is_vsmp_box(void) 92129d8bc8SYinghai Lu { 93129d8bc8SYinghai Lu return 0; 94129d8bc8SYinghai Lu } 95129d8bc8SYinghai Lu #endif 96bb898558SAl Viro extern int setup_profiling_timer(unsigned int); 97bb898558SAl Viro 98bb898558SAl Viro static inline void native_apic_mem_write(u32 reg, u32 v) 99bb898558SAl Viro { 100bb898558SAl Viro volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 101bb898558SAl Viro 1029b13a93dSBorislav Petkov alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, 103bb898558SAl Viro ASM_OUTPUT2("=r" (v), "=m" (*addr)), 104bb898558SAl Viro ASM_OUTPUT2("0" (v), "m" (*addr))); 105bb898558SAl Viro } 106bb898558SAl Viro 107bb898558SAl Viro static inline u32 native_apic_mem_read(u32 reg) 108bb898558SAl Viro { 109bb898558SAl Viro return *((volatile u32 *)(APIC_BASE + reg)); 110bb898558SAl Viro } 111bb898558SAl Viro 112c1eeb2deSYinghai Lu extern void native_apic_wait_icr_idle(void); 113c1eeb2deSYinghai Lu extern u32 native_safe_apic_wait_icr_idle(void); 114c1eeb2deSYinghai Lu extern void native_apic_icr_write(u32 low, u32 id); 115c1eeb2deSYinghai Lu extern u64 native_apic_icr_read(void); 116c1eeb2deSYinghai Lu 117fc1edaf9SSuresh Siddha extern int x2apic_mode; 118b24696bcSFenghua Yu 119d0b03bd1SHan, Weidong #ifdef CONFIG_X86_X2APIC 120ce4e240cSSuresh Siddha /* 121ce4e240cSSuresh Siddha * Make previous memory operations globally visible before 122ce4e240cSSuresh Siddha * sending the IPI through x2apic wrmsr. We need a serializing instruction or 123ce4e240cSSuresh Siddha * mfence for this. 124ce4e240cSSuresh Siddha */ 125ce4e240cSSuresh Siddha static inline void x2apic_wrmsr_fence(void) 126ce4e240cSSuresh Siddha { 127ce4e240cSSuresh Siddha asm volatile("mfence" : : : "memory"); 128ce4e240cSSuresh Siddha } 129ce4e240cSSuresh Siddha 130bb898558SAl Viro static inline void native_apic_msr_write(u32 reg, u32 v) 131bb898558SAl Viro { 132bb898558SAl Viro if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 133bb898558SAl Viro reg == APIC_LVR) 134bb898558SAl Viro return; 135bb898558SAl Viro 136bb898558SAl Viro wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 137bb898558SAl Viro } 138bb898558SAl Viro 1390ab711aeSMichael S. Tsirkin static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 1400ab711aeSMichael S. Tsirkin { 1410ab711aeSMichael S. Tsirkin wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 1420ab711aeSMichael S. Tsirkin } 1430ab711aeSMichael S. Tsirkin 144bb898558SAl Viro static inline u32 native_apic_msr_read(u32 reg) 145bb898558SAl Viro { 1460059b243SAndi Kleen u64 msr; 147bb898558SAl Viro 148bb898558SAl Viro if (reg == APIC_DFR) 149bb898558SAl Viro return -1; 150bb898558SAl Viro 1510059b243SAndi Kleen rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 1520059b243SAndi Kleen return (u32)msr; 153bb898558SAl Viro } 154bb898558SAl Viro 155c1eeb2deSYinghai Lu static inline void native_x2apic_wait_icr_idle(void) 156c1eeb2deSYinghai Lu { 157c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 158c1eeb2deSYinghai Lu return; 159c1eeb2deSYinghai Lu } 160c1eeb2deSYinghai Lu 161c1eeb2deSYinghai Lu static inline u32 native_safe_x2apic_wait_icr_idle(void) 162c1eeb2deSYinghai Lu { 163c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 164c1eeb2deSYinghai Lu return 0; 165c1eeb2deSYinghai Lu } 166c1eeb2deSYinghai Lu 167c1eeb2deSYinghai Lu static inline void native_x2apic_icr_write(u32 low, u32 id) 168c1eeb2deSYinghai Lu { 169c1eeb2deSYinghai Lu wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 170c1eeb2deSYinghai Lu } 171c1eeb2deSYinghai Lu 172c1eeb2deSYinghai Lu static inline u64 native_x2apic_icr_read(void) 173c1eeb2deSYinghai Lu { 174c1eeb2deSYinghai Lu unsigned long val; 175c1eeb2deSYinghai Lu 176c1eeb2deSYinghai Lu rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 177c1eeb2deSYinghai Lu return val; 178c1eeb2deSYinghai Lu } 179c1eeb2deSYinghai Lu 180fc1edaf9SSuresh Siddha extern int x2apic_phys; 181fb209bd8SYinghai Lu extern int x2apic_preenabled; 182bb898558SAl Viro extern void check_x2apic(void); 183bb898558SAl Viro extern void enable_x2apic(void); 184bb898558SAl Viro static inline int x2apic_enabled(void) 185bb898558SAl Viro { 1860059b243SAndi Kleen u64 msr; 187bb898558SAl Viro 188bb898558SAl Viro if (!cpu_has_x2apic) 189bb898558SAl Viro return 0; 190bb898558SAl Viro 1910059b243SAndi Kleen rdmsrl(MSR_IA32_APICBASE, msr); 192bb898558SAl Viro if (msr & X2APIC_ENABLE) 193bb898558SAl Viro return 1; 194bb898558SAl Viro return 0; 195bb898558SAl Viro } 196fc1edaf9SSuresh Siddha 197fc1edaf9SSuresh Siddha #define x2apic_supported() (cpu_has_x2apic) 198ce69a784SGleb Natapov static inline void x2apic_force_phys(void) 199ce69a784SGleb Natapov { 200ce69a784SGleb Natapov x2apic_phys = 1; 201ce69a784SGleb Natapov } 202bb898558SAl Viro #else 203fb209bd8SYinghai Lu static inline void disable_x2apic(void) 204fb209bd8SYinghai Lu { 205fb209bd8SYinghai Lu } 20606cd9a7dSYinghai Lu static inline void check_x2apic(void) 20706cd9a7dSYinghai Lu { 20806cd9a7dSYinghai Lu } 20906cd9a7dSYinghai Lu static inline void enable_x2apic(void) 21006cd9a7dSYinghai Lu { 21106cd9a7dSYinghai Lu } 21206cd9a7dSYinghai Lu static inline int x2apic_enabled(void) 21306cd9a7dSYinghai Lu { 21406cd9a7dSYinghai Lu return 0; 21506cd9a7dSYinghai Lu } 216ce69a784SGleb Natapov static inline void x2apic_force_phys(void) 217ce69a784SGleb Natapov { 218ce69a784SGleb Natapov } 219cf6567feSSuresh Siddha 22093758238SWeidong Han #define x2apic_preenabled 0 221fc1edaf9SSuresh Siddha #define x2apic_supported() 0 222bb898558SAl Viro #endif 223bb898558SAl Viro 22493758238SWeidong Han extern void enable_IR_x2apic(void); 22593758238SWeidong Han 226bb898558SAl Viro extern int get_physical_broadcast(void); 227bb898558SAl Viro 228bb898558SAl Viro extern int lapic_get_maxlvt(void); 229bb898558SAl Viro extern void clear_local_APIC(void); 230bb898558SAl Viro extern void connect_bsp_APIC(void); 231bb898558SAl Viro extern void disconnect_bsp_APIC(int virt_wire_setup); 232bb898558SAl Viro extern void disable_local_APIC(void); 233bb898558SAl Viro extern void lapic_shutdown(void); 234bb898558SAl Viro extern int verify_local_APIC(void); 235bb898558SAl Viro extern void sync_Arb_IDs(void); 236bb898558SAl Viro extern void init_bsp_APIC(void); 237bb898558SAl Viro extern void setup_local_APIC(void); 238bb898558SAl Viro extern void end_local_APIC_setup(void); 2392fb270f3SJan Beulich extern void bsp_end_local_APIC_setup(void); 240bb898558SAl Viro extern void init_apic_mappings(void); 241c0104d38SYinghai Lu void register_lapic_address(unsigned long address); 242bb898558SAl Viro extern void setup_boot_APIC_clock(void); 243bb898558SAl Viro extern void setup_secondary_APIC_clock(void); 244bb898558SAl Viro extern int APIC_init_uniprocessor(void); 245a906fdaaSThomas Gleixner extern int apic_force_enable(unsigned long addr); 246bb898558SAl Viro 247bb898558SAl Viro /* 248bb898558SAl Viro * On 32bit this is mach-xxx local 249bb898558SAl Viro */ 250bb898558SAl Viro #ifdef CONFIG_X86_64 251bb898558SAl Viro extern int apic_is_clustered_box(void); 252bb898558SAl Viro #else 253bb898558SAl Viro static inline int apic_is_clustered_box(void) 254bb898558SAl Viro { 255bb898558SAl Viro return 0; 256bb898558SAl Viro } 257bb898558SAl Viro #endif 258bb898558SAl Viro 25927afdf20SRobert Richter extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 260bb898558SAl Viro 261bb898558SAl Viro #else /* !CONFIG_X86_LOCAL_APIC */ 262bb898558SAl Viro static inline void lapic_shutdown(void) { } 263bb898558SAl Viro #define local_apic_timer_c2_ok 1 264bb898558SAl Viro static inline void init_apic_mappings(void) { } 265d3ec5caeSIvan Vecera static inline void disable_local_APIC(void) { } 266736decacSThomas Gleixner # define setup_boot_APIC_clock x86_init_noop 267736decacSThomas Gleixner # define setup_secondary_APIC_clock x86_init_noop 268bb898558SAl Viro #endif /* !CONFIG_X86_LOCAL_APIC */ 269bb898558SAl Viro 2701f75ed0cSIngo Molnar #ifdef CONFIG_X86_64 2711f75ed0cSIngo Molnar #define SET_APIC_ID(x) (apic->set_apic_id(x)) 2721f75ed0cSIngo Molnar #else 2731f75ed0cSIngo Molnar 2741f75ed0cSIngo Molnar #endif 2751f75ed0cSIngo Molnar 276e2780a68SIngo Molnar /* 277e2780a68SIngo Molnar * Copyright 2004 James Cleverdon, IBM. 278e2780a68SIngo Molnar * Subject to the GNU Public License, v.2 279e2780a68SIngo Molnar * 280e2780a68SIngo Molnar * Generic APIC sub-arch data struct. 281e2780a68SIngo Molnar * 282e2780a68SIngo Molnar * Hacked for x86-64 by James Cleverdon from i386 architecture code by 283e2780a68SIngo Molnar * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 284e2780a68SIngo Molnar * James Cleverdon. 285e2780a68SIngo Molnar */ 286be163a15SIngo Molnar struct apic { 287e2780a68SIngo Molnar char *name; 288e2780a68SIngo Molnar 289e2780a68SIngo Molnar int (*probe)(void); 290e2780a68SIngo Molnar int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 291fa63030eSDaniel J Blueman int (*apic_id_valid)(int apicid); 292e2780a68SIngo Molnar int (*apic_id_registered)(void); 293e2780a68SIngo Molnar 294e2780a68SIngo Molnar u32 irq_delivery_mode; 295e2780a68SIngo Molnar u32 irq_dest_mode; 296e2780a68SIngo Molnar 297e2780a68SIngo Molnar const struct cpumask *(*target_cpus)(void); 298e2780a68SIngo Molnar 299e2780a68SIngo Molnar int disable_esr; 300e2780a68SIngo Molnar 301e2780a68SIngo Molnar int dest_logical; 3027abc0753SCyrill Gorcunov unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 303e2780a68SIngo Molnar unsigned long (*check_apicid_present)(int apicid); 304e2780a68SIngo Molnar 3051ac322d0SSuresh Siddha void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 3061ac322d0SSuresh Siddha const struct cpumask *mask); 307e2780a68SIngo Molnar void (*init_apic_ldr)(void); 308e2780a68SIngo Molnar 3097abc0753SCyrill Gorcunov void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 310e2780a68SIngo Molnar 311e2780a68SIngo Molnar void (*setup_apic_routing)(void); 312e2780a68SIngo Molnar int (*multi_timer_check)(int apic, int irq); 313e2780a68SIngo Molnar int (*cpu_present_to_apicid)(int mps_cpu); 3147abc0753SCyrill Gorcunov void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 315e2780a68SIngo Molnar void (*setup_portio_remap)(void); 316e11dadabSThomas Gleixner int (*check_phys_apicid_present)(int phys_apicid); 317e2780a68SIngo Molnar void (*enable_apic_mode)(void); 318e2780a68SIngo Molnar int (*phys_pkg_id)(int cpuid_apic, int index_msb); 319e2780a68SIngo Molnar 320e2780a68SIngo Molnar /* 321be163a15SIngo Molnar * When one of the next two hooks returns 1 the apic 322e2780a68SIngo Molnar * is switched to this. Essentially they are additional 323e2780a68SIngo Molnar * probe functions: 324e2780a68SIngo Molnar */ 325e2780a68SIngo Molnar int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 326e2780a68SIngo Molnar 327e2780a68SIngo Molnar unsigned int (*get_apic_id)(unsigned long x); 328e2780a68SIngo Molnar unsigned long (*set_apic_id)(unsigned int id); 329e2780a68SIngo Molnar unsigned long apic_id_mask; 330e2780a68SIngo Molnar 331ff164324SAlexander Gordeev int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 332ff164324SAlexander Gordeev const struct cpumask *andmask, 333ff164324SAlexander Gordeev unsigned int *apicid); 334e2780a68SIngo Molnar 335e2780a68SIngo Molnar /* ipi */ 336e2780a68SIngo Molnar void (*send_IPI_mask)(const struct cpumask *mask, int vector); 337e2780a68SIngo Molnar void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 338e2780a68SIngo Molnar int vector); 339e2780a68SIngo Molnar void (*send_IPI_allbutself)(int vector); 340e2780a68SIngo Molnar void (*send_IPI_all)(int vector); 341e2780a68SIngo Molnar void (*send_IPI_self)(int vector); 342e2780a68SIngo Molnar 343e2780a68SIngo Molnar /* wakeup_secondary_cpu */ 3441f5bcabfSIngo Molnar int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 345e2780a68SIngo Molnar 346e2780a68SIngo Molnar int trampoline_phys_low; 347e2780a68SIngo Molnar int trampoline_phys_high; 348e2780a68SIngo Molnar 349465822cfSDavid Rientjes bool wait_for_init_deassert; 350e2780a68SIngo Molnar void (*smp_callin_clear_local_apic)(void); 351e2780a68SIngo Molnar void (*inquire_remote_apic)(int apicid); 352e2780a68SIngo Molnar 353e2780a68SIngo Molnar /* apic ops */ 354e2780a68SIngo Molnar u32 (*read)(u32 reg); 355e2780a68SIngo Molnar void (*write)(u32 reg, u32 v); 3562a43195dSMichael S. Tsirkin /* 3572a43195dSMichael S. Tsirkin * ->eoi_write() has the same signature as ->write(). 3582a43195dSMichael S. Tsirkin * 3592a43195dSMichael S. Tsirkin * Drivers can support both ->eoi_write() and ->write() by passing the same 3602a43195dSMichael S. Tsirkin * callback value. Kernel can override ->eoi_write() and fall back 3612a43195dSMichael S. Tsirkin * on write for EOI. 3622a43195dSMichael S. Tsirkin */ 3632a43195dSMichael S. Tsirkin void (*eoi_write)(u32 reg, u32 v); 364e2780a68SIngo Molnar u64 (*icr_read)(void); 365e2780a68SIngo Molnar void (*icr_write)(u32 low, u32 high); 366e2780a68SIngo Molnar void (*wait_icr_idle)(void); 367e2780a68SIngo Molnar u32 (*safe_wait_icr_idle)(void); 368acb8bc09STejun Heo 369acb8bc09STejun Heo #ifdef CONFIG_X86_32 370acb8bc09STejun Heo /* 371acb8bc09STejun Heo * Called very early during boot from get_smp_config(). It should 372acb8bc09STejun Heo * return the logical apicid. x86_[bios]_cpu_to_apicid is 373acb8bc09STejun Heo * initialized before this function is called. 374acb8bc09STejun Heo * 375acb8bc09STejun Heo * If logical apicid can't be determined that early, the function 376acb8bc09STejun Heo * may return BAD_APICID. Logical apicid will be configured after 377acb8bc09STejun Heo * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 378acb8bc09STejun Heo * won't be applied properly during early boot in this case. 379acb8bc09STejun Heo */ 380acb8bc09STejun Heo int (*x86_32_early_logical_apicid)(int cpu); 38189e5dc21STejun Heo 38284914ed0STejun Heo /* 38384914ed0STejun Heo * Optional method called from setup_local_APIC() after logical 38484914ed0STejun Heo * apicid is guaranteed to be known to initialize apicid -> node 38584914ed0STejun Heo * mapping if NUMA initialization hasn't done so already. Don't 38684914ed0STejun Heo * add new users. 38784914ed0STejun Heo */ 38889e5dc21STejun Heo int (*x86_32_numa_cpu_node)(int cpu); 389acb8bc09STejun Heo #endif 390e2780a68SIngo Molnar }; 391e2780a68SIngo Molnar 3920917c01fSIngo Molnar /* 3930917c01fSIngo Molnar * Pointer to the local APIC driver in use on this system (there's 3940917c01fSIngo Molnar * always just one such driver in use - the kernel decides via an 3950917c01fSIngo Molnar * early probing process which one it picks - and then sticks to it): 3960917c01fSIngo Molnar */ 397be163a15SIngo Molnar extern struct apic *apic; 3980917c01fSIngo Molnar 3990917c01fSIngo Molnar /* 400107e0e0cSSuresh Siddha * APIC drivers are probed based on how they are listed in the .apicdrivers 401107e0e0cSSuresh Siddha * section. So the order is important and enforced by the ordering 402107e0e0cSSuresh Siddha * of different apic driver files in the Makefile. 403107e0e0cSSuresh Siddha * 404107e0e0cSSuresh Siddha * For the files having two apic drivers, we use apic_drivers() 405107e0e0cSSuresh Siddha * to enforce the order with in them. 406107e0e0cSSuresh Siddha */ 407107e0e0cSSuresh Siddha #define apic_driver(sym) \ 40875fdd155SAndi Kleen static const struct apic *__apicdrivers_##sym __used \ 409107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 410107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym } 411107e0e0cSSuresh Siddha 412107e0e0cSSuresh Siddha #define apic_drivers(sym1, sym2) \ 413107e0e0cSSuresh Siddha static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 414107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 415107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym1, &sym2 } 416107e0e0cSSuresh Siddha 417107e0e0cSSuresh Siddha extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 418107e0e0cSSuresh Siddha 419107e0e0cSSuresh Siddha /* 4200917c01fSIngo Molnar * APIC functionality to boot other CPUs - only used on SMP: 4210917c01fSIngo Molnar */ 4220917c01fSIngo Molnar #ifdef CONFIG_SMP 4232b6163bfSYinghai Lu extern atomic_t init_deasserted; 4242b6163bfSYinghai Lu extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 4250917c01fSIngo Molnar #endif 426e2780a68SIngo Molnar 427d674cd19SCyrill Gorcunov #ifdef CONFIG_X86_LOCAL_APIC 428346b46beSFernando Luis Vázquez Cao 429e2780a68SIngo Molnar static inline u32 apic_read(u32 reg) 430e2780a68SIngo Molnar { 431e2780a68SIngo Molnar return apic->read(reg); 432e2780a68SIngo Molnar } 433e2780a68SIngo Molnar 434e2780a68SIngo Molnar static inline void apic_write(u32 reg, u32 val) 435e2780a68SIngo Molnar { 436e2780a68SIngo Molnar apic->write(reg, val); 437e2780a68SIngo Molnar } 438e2780a68SIngo Molnar 4392a43195dSMichael S. Tsirkin static inline void apic_eoi(void) 4402a43195dSMichael S. Tsirkin { 4412a43195dSMichael S. Tsirkin apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 4422a43195dSMichael S. Tsirkin } 4432a43195dSMichael S. Tsirkin 444e2780a68SIngo Molnar static inline u64 apic_icr_read(void) 445e2780a68SIngo Molnar { 446e2780a68SIngo Molnar return apic->icr_read(); 447e2780a68SIngo Molnar } 448e2780a68SIngo Molnar 449e2780a68SIngo Molnar static inline void apic_icr_write(u32 low, u32 high) 450e2780a68SIngo Molnar { 451e2780a68SIngo Molnar apic->icr_write(low, high); 452e2780a68SIngo Molnar } 453e2780a68SIngo Molnar 454e2780a68SIngo Molnar static inline void apic_wait_icr_idle(void) 455e2780a68SIngo Molnar { 456e2780a68SIngo Molnar apic->wait_icr_idle(); 457e2780a68SIngo Molnar } 458e2780a68SIngo Molnar 459e2780a68SIngo Molnar static inline u32 safe_apic_wait_icr_idle(void) 460e2780a68SIngo Molnar { 461e2780a68SIngo Molnar return apic->safe_wait_icr_idle(); 462e2780a68SIngo Molnar } 463e2780a68SIngo Molnar 4641551df64SMichael S. Tsirkin extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 4651551df64SMichael S. Tsirkin 466d674cd19SCyrill Gorcunov #else /* CONFIG_X86_LOCAL_APIC */ 467d674cd19SCyrill Gorcunov 468d674cd19SCyrill Gorcunov static inline u32 apic_read(u32 reg) { return 0; } 469d674cd19SCyrill Gorcunov static inline void apic_write(u32 reg, u32 val) { } 4702a43195dSMichael S. Tsirkin static inline void apic_eoi(void) { } 471d674cd19SCyrill Gorcunov static inline u64 apic_icr_read(void) { return 0; } 472d674cd19SCyrill Gorcunov static inline void apic_icr_write(u32 low, u32 high) { } 473d674cd19SCyrill Gorcunov static inline void apic_wait_icr_idle(void) { } 474d674cd19SCyrill Gorcunov static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 4751551df64SMichael S. Tsirkin static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 476d674cd19SCyrill Gorcunov 477d674cd19SCyrill Gorcunov #endif /* CONFIG_X86_LOCAL_APIC */ 478e2780a68SIngo Molnar 479e2780a68SIngo Molnar static inline void ack_APIC_irq(void) 480e2780a68SIngo Molnar { 481e2780a68SIngo Molnar /* 482e2780a68SIngo Molnar * ack_APIC_irq() actually gets compiled as a single instruction 483e2780a68SIngo Molnar * ... yummie. 484e2780a68SIngo Molnar */ 4852a43195dSMichael S. Tsirkin apic_eoi(); 486e2780a68SIngo Molnar } 487e2780a68SIngo Molnar 488e2780a68SIngo Molnar static inline unsigned default_get_apic_id(unsigned long x) 489e2780a68SIngo Molnar { 490e2780a68SIngo Molnar unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 491e2780a68SIngo Molnar 49242937e81SAndreas Herrmann if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 493e2780a68SIngo Molnar return (x >> 24) & 0xFF; 494e2780a68SIngo Molnar else 495e2780a68SIngo Molnar return (x >> 24) & 0x0F; 496e2780a68SIngo Molnar } 497e2780a68SIngo Molnar 498e2780a68SIngo Molnar /* 499e2780a68SIngo Molnar * Warm reset vector default position: 500e2780a68SIngo Molnar */ 501e2780a68SIngo Molnar #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 502e2780a68SIngo Molnar #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 503e2780a68SIngo Molnar 5042b6163bfSYinghai Lu #ifdef CONFIG_X86_64 505e2780a68SIngo Molnar extern int default_acpi_madt_oem_check(char *, char *); 506e2780a68SIngo Molnar 507e2780a68SIngo Molnar extern void apic_send_IPI_self(int vector); 508e2780a68SIngo Molnar 509e2780a68SIngo Molnar DECLARE_PER_CPU(int, x2apic_extra_bits); 510e2780a68SIngo Molnar 511e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 512e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 513e2780a68SIngo Molnar #endif 514e2780a68SIngo Molnar 515838312beSJan Beulich extern void generic_bigsmp_probe(void); 516e2780a68SIngo Molnar 517e2780a68SIngo Molnar 518e2780a68SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 519e2780a68SIngo Molnar 520e2780a68SIngo Molnar #include <asm/smp.h> 521e2780a68SIngo Molnar 522e2780a68SIngo Molnar #define APIC_DFR_VALUE (APIC_DFR_FLAT) 523e2780a68SIngo Molnar 524e2780a68SIngo Molnar static inline const struct cpumask *default_target_cpus(void) 525e2780a68SIngo Molnar { 526e2780a68SIngo Molnar #ifdef CONFIG_SMP 527e2780a68SIngo Molnar return cpu_online_mask; 528e2780a68SIngo Molnar #else 529e2780a68SIngo Molnar return cpumask_of(0); 530e2780a68SIngo Molnar #endif 531e2780a68SIngo Molnar } 532e2780a68SIngo Molnar 533bf721d3aSAlexander Gordeev static inline const struct cpumask *online_target_cpus(void) 534bf721d3aSAlexander Gordeev { 535bf721d3aSAlexander Gordeev return cpu_online_mask; 536bf721d3aSAlexander Gordeev } 537bf721d3aSAlexander Gordeev 5380816b0f0SVlad Zolotarov DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 539e2780a68SIngo Molnar 540e2780a68SIngo Molnar 541e2780a68SIngo Molnar static inline unsigned int read_apic_id(void) 542e2780a68SIngo Molnar { 543e2780a68SIngo Molnar unsigned int reg; 544e2780a68SIngo Molnar 545e2780a68SIngo Molnar reg = apic_read(APIC_ID); 546e2780a68SIngo Molnar 547e2780a68SIngo Molnar return apic->get_apic_id(reg); 548e2780a68SIngo Molnar } 549e2780a68SIngo Molnar 550fa63030eSDaniel J Blueman static inline int default_apic_id_valid(int apicid) 551fa63030eSDaniel J Blueman { 552b7157acfSSteffen Persvold return (apicid < 255); 553fa63030eSDaniel J Blueman } 554fa63030eSDaniel J Blueman 555e2780a68SIngo Molnar extern void default_setup_apic_routing(void); 556e2780a68SIngo Molnar 5579844ab11SCyrill Gorcunov extern struct apic apic_noop; 5589844ab11SCyrill Gorcunov 559e2780a68SIngo Molnar #ifdef CONFIG_X86_32 5602c1b284eSJaswinder Singh Rajput 561acb8bc09STejun Heo static inline int noop_x86_32_early_logical_apicid(int cpu) 562acb8bc09STejun Heo { 563acb8bc09STejun Heo return BAD_APICID; 564acb8bc09STejun Heo } 565acb8bc09STejun Heo 566e2780a68SIngo Molnar /* 567e2780a68SIngo Molnar * Set up the logical destination ID. 568e2780a68SIngo Molnar * 569e2780a68SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 570e2780a68SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 571e2780a68SIngo Molnar * document number 292116). So here it goes... 572e2780a68SIngo Molnar */ 573e2780a68SIngo Molnar extern void default_init_apic_ldr(void); 574e2780a68SIngo Molnar 575e2780a68SIngo Molnar static inline int default_apic_id_registered(void) 576e2780a68SIngo Molnar { 577e2780a68SIngo Molnar return physid_isset(read_apic_id(), phys_cpu_present_map); 578e2780a68SIngo Molnar } 579e2780a68SIngo Molnar 580f56e5034SYinghai Lu static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 581f56e5034SYinghai Lu { 582f56e5034SYinghai Lu return cpuid_apic >> index_msb; 583f56e5034SYinghai Lu } 584f56e5034SYinghai Lu 585f56e5034SYinghai Lu #endif 586f56e5034SYinghai Lu 587ff164324SAlexander Gordeev static inline int 588a5a39156SAlexander Gordeev flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 589a5a39156SAlexander Gordeev const struct cpumask *andmask, 590a5a39156SAlexander Gordeev unsigned int *apicid) 591e2780a68SIngo Molnar { 592a5a39156SAlexander Gordeev unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 593a5a39156SAlexander Gordeev cpumask_bits(andmask)[0] & 594a5a39156SAlexander Gordeev cpumask_bits(cpu_online_mask)[0] & 595a5a39156SAlexander Gordeev APIC_ALL_CPUS; 596a5a39156SAlexander Gordeev 597ff164324SAlexander Gordeev if (likely(cpu_mask)) { 598ff164324SAlexander Gordeev *apicid = (unsigned int)cpu_mask; 599ff164324SAlexander Gordeev return 0; 600ff164324SAlexander Gordeev } else { 601ff164324SAlexander Gordeev return -EINVAL; 602ff164324SAlexander Gordeev } 603e2780a68SIngo Molnar } 604e2780a68SIngo Molnar 605ff164324SAlexander Gordeev extern int 6066398268dSAlexander Gordeev default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 607ff164324SAlexander Gordeev const struct cpumask *andmask, 608ff164324SAlexander Gordeev unsigned int *apicid); 6096398268dSAlexander Gordeev 610b39f25a8SSuresh Siddha static inline void 6111ac322d0SSuresh Siddha flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 6121ac322d0SSuresh Siddha const struct cpumask *mask) 6139d8e1066SAlexander Gordeev { 6149d8e1066SAlexander Gordeev /* Careful. Some cpus do not strictly honor the set of cpus 6159d8e1066SAlexander Gordeev * specified in the interrupt destination when using lowest 6169d8e1066SAlexander Gordeev * priority interrupt delivery mode. 6179d8e1066SAlexander Gordeev * 6189d8e1066SAlexander Gordeev * In particular there was a hyperthreading cpu observed to 6199d8e1066SAlexander Gordeev * deliver interrupts to the wrong hyperthread when only one 6209d8e1066SAlexander Gordeev * hyperthread was specified in the interrupt desitination. 6219d8e1066SAlexander Gordeev */ 6229d8e1066SAlexander Gordeev cpumask_clear(retmask); 6239d8e1066SAlexander Gordeev cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 6249d8e1066SAlexander Gordeev } 6259d8e1066SAlexander Gordeev 626b39f25a8SSuresh Siddha static inline void 6271ac322d0SSuresh Siddha default_vector_allocation_domain(int cpu, struct cpumask *retmask, 6281ac322d0SSuresh Siddha const struct cpumask *mask) 6299d8e1066SAlexander Gordeev { 6309d8e1066SAlexander Gordeev cpumask_copy(retmask, cpumask_of(cpu)); 6319d8e1066SAlexander Gordeev } 6329d8e1066SAlexander Gordeev 6337abc0753SCyrill Gorcunov static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 634e2780a68SIngo Molnar { 6357abc0753SCyrill Gorcunov return physid_isset(apicid, *map); 636e2780a68SIngo Molnar } 637e2780a68SIngo Molnar 638e2780a68SIngo Molnar static inline unsigned long default_check_apicid_present(int bit) 639e2780a68SIngo Molnar { 640e2780a68SIngo Molnar return physid_isset(bit, phys_cpu_present_map); 641e2780a68SIngo Molnar } 642e2780a68SIngo Molnar 6437abc0753SCyrill Gorcunov static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 644e2780a68SIngo Molnar { 6457abc0753SCyrill Gorcunov *retmap = *phys_map; 646e2780a68SIngo Molnar } 647e2780a68SIngo Molnar 648e2780a68SIngo Molnar static inline int __default_cpu_present_to_apicid(int mps_cpu) 649e2780a68SIngo Molnar { 650e2780a68SIngo Molnar if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 651e2780a68SIngo Molnar return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 652e2780a68SIngo Molnar else 653e2780a68SIngo Molnar return BAD_APICID; 654e2780a68SIngo Molnar } 655e2780a68SIngo Molnar 656e2780a68SIngo Molnar static inline int 657e11dadabSThomas Gleixner __default_check_phys_apicid_present(int phys_apicid) 658e2780a68SIngo Molnar { 659e11dadabSThomas Gleixner return physid_isset(phys_apicid, phys_cpu_present_map); 660e2780a68SIngo Molnar } 661e2780a68SIngo Molnar 662e2780a68SIngo Molnar #ifdef CONFIG_X86_32 663e2780a68SIngo Molnar static inline int default_cpu_present_to_apicid(int mps_cpu) 664e2780a68SIngo Molnar { 665e2780a68SIngo Molnar return __default_cpu_present_to_apicid(mps_cpu); 666e2780a68SIngo Molnar } 667e2780a68SIngo Molnar 668e2780a68SIngo Molnar static inline int 669e11dadabSThomas Gleixner default_check_phys_apicid_present(int phys_apicid) 670e2780a68SIngo Molnar { 671e11dadabSThomas Gleixner return __default_check_phys_apicid_present(phys_apicid); 672e2780a68SIngo Molnar } 673e2780a68SIngo Molnar #else 674e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 675e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 676e2780a68SIngo Molnar #endif 677e2780a68SIngo Molnar 678e2780a68SIngo Molnar #endif /* CONFIG_X86_LOCAL_APIC */ 679eddc0e92SSeiji Aguchi extern void irq_enter(void); 680eddc0e92SSeiji Aguchi extern void irq_exit(void); 681eddc0e92SSeiji Aguchi 682eddc0e92SSeiji Aguchi static inline void entering_irq(void) 683eddc0e92SSeiji Aguchi { 684eddc0e92SSeiji Aguchi irq_enter(); 685eddc0e92SSeiji Aguchi exit_idle(); 686eddc0e92SSeiji Aguchi } 687eddc0e92SSeiji Aguchi 688eddc0e92SSeiji Aguchi static inline void entering_ack_irq(void) 689eddc0e92SSeiji Aguchi { 690eddc0e92SSeiji Aguchi ack_APIC_irq(); 691eddc0e92SSeiji Aguchi entering_irq(); 692eddc0e92SSeiji Aguchi } 693eddc0e92SSeiji Aguchi 694eddc0e92SSeiji Aguchi static inline void exiting_irq(void) 695eddc0e92SSeiji Aguchi { 696eddc0e92SSeiji Aguchi irq_exit(); 697eddc0e92SSeiji Aguchi } 698eddc0e92SSeiji Aguchi 699eddc0e92SSeiji Aguchi static inline void exiting_ack_irq(void) 700eddc0e92SSeiji Aguchi { 701eddc0e92SSeiji Aguchi irq_exit(); 702eddc0e92SSeiji Aguchi /* Ack only at the end to avoid potential reentry */ 703eddc0e92SSeiji Aguchi ack_APIC_irq(); 704eddc0e92SSeiji Aguchi } 705e2780a68SIngo Molnar 70617405453SYoshihiro YUNOMAE extern void ioapic_zap_locks(void); 70717405453SYoshihiro YUNOMAE 7081965aae3SH. Peter Anvin #endif /* _ASM_X86_APIC_H */ 709