11965aae3SH. Peter Anvin #ifndef _ASM_X86_APIC_H 21965aae3SH. Peter Anvin #define _ASM_X86_APIC_H 3bb898558SAl Viro 4e2780a68SIngo Molnar #include <linux/cpumask.h> 5bb898558SAl Viro #include <linux/delay.h> 6e2780a68SIngo Molnar #include <linux/pm.h> 7bb898558SAl Viro 8bb898558SAl Viro #include <asm/alternative.h> 9bb898558SAl Viro #include <asm/cpufeature.h> 10e2780a68SIngo Molnar #include <asm/processor.h> 11e2780a68SIngo Molnar #include <asm/apicdef.h> 12e2780a68SIngo Molnar #include <asm/atomic.h> 13e2780a68SIngo Molnar #include <asm/fixmap.h> 14e2780a68SIngo Molnar #include <asm/mpspec.h> 15e2780a68SIngo Molnar #include <asm/system.h> 16bb898558SAl Viro #include <asm/msr.h> 17bb898558SAl Viro 18bb898558SAl Viro #define ARCH_APICTIMER_STOPS_ON_C3 1 19bb898558SAl Viro 20bb898558SAl Viro /* 21bb898558SAl Viro * Debugging macros 22bb898558SAl Viro */ 23bb898558SAl Viro #define APIC_QUIET 0 24bb898558SAl Viro #define APIC_VERBOSE 1 25bb898558SAl Viro #define APIC_DEBUG 2 26bb898558SAl Viro 27bb898558SAl Viro /* 28bb898558SAl Viro * Define the default level of output to be very little 29bb898558SAl Viro * This can be turned up by using apic=verbose for more 30bb898558SAl Viro * information and apic=debug for _lots_ of information. 31bb898558SAl Viro * apic_verbosity is defined in apic.c 32bb898558SAl Viro */ 33bb898558SAl Viro #define apic_printk(v, s, a...) do { \ 34bb898558SAl Viro if ((v) <= apic_verbosity) \ 35bb898558SAl Viro printk(s, ##a); \ 36bb898558SAl Viro } while (0) 37bb898558SAl Viro 38bb898558SAl Viro 39160d8dacSIngo Molnar #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 40bb898558SAl Viro extern void generic_apic_probe(void); 41160d8dacSIngo Molnar #else 42160d8dacSIngo Molnar static inline void generic_apic_probe(void) 43160d8dacSIngo Molnar { 44160d8dacSIngo Molnar } 45160d8dacSIngo Molnar #endif 46bb898558SAl Viro 47bb898558SAl Viro #ifdef CONFIG_X86_LOCAL_APIC 48bb898558SAl Viro 49bb898558SAl Viro extern unsigned int apic_verbosity; 50bb898558SAl Viro extern int local_apic_timer_c2_ok; 51bb898558SAl Viro 52bb898558SAl Viro extern int disable_apic; 530939e4fdSIngo Molnar 540939e4fdSIngo Molnar #ifdef CONFIG_SMP 550939e4fdSIngo Molnar extern void __inquire_remote_apic(int apicid); 560939e4fdSIngo Molnar #else /* CONFIG_SMP */ 570939e4fdSIngo Molnar static inline void __inquire_remote_apic(int apicid) 580939e4fdSIngo Molnar { 590939e4fdSIngo Molnar } 600939e4fdSIngo Molnar #endif /* CONFIG_SMP */ 610939e4fdSIngo Molnar 620939e4fdSIngo Molnar static inline void default_inquire_remote_apic(int apicid) 630939e4fdSIngo Molnar { 640939e4fdSIngo Molnar if (apic_verbosity >= APIC_DEBUG) 650939e4fdSIngo Molnar __inquire_remote_apic(apicid); 660939e4fdSIngo Molnar } 670939e4fdSIngo Molnar 68bb898558SAl Viro /* 698312136fSCyrill Gorcunov * With 82489DX we can't rely on apic feature bit 708312136fSCyrill Gorcunov * retrieved via cpuid but still have to deal with 718312136fSCyrill Gorcunov * such an apic chip so we assume that SMP configuration 728312136fSCyrill Gorcunov * is found from MP table (64bit case uses ACPI mostly 738312136fSCyrill Gorcunov * which set smp presence flag as well so we are safe 748312136fSCyrill Gorcunov * to use this helper too). 758312136fSCyrill Gorcunov */ 768312136fSCyrill Gorcunov static inline bool apic_from_smp_config(void) 778312136fSCyrill Gorcunov { 788312136fSCyrill Gorcunov return smp_found_config && !disable_apic; 798312136fSCyrill Gorcunov } 808312136fSCyrill Gorcunov 818312136fSCyrill Gorcunov /* 82bb898558SAl Viro * Basic functions accessing APICs. 83bb898558SAl Viro */ 84bb898558SAl Viro #ifdef CONFIG_PARAVIRT 85bb898558SAl Viro #include <asm/paravirt.h> 86bb898558SAl Viro #endif 87bb898558SAl Viro 8870511134SRavikiran G Thirumalai #ifdef CONFIG_X86_64 89bb898558SAl Viro extern int is_vsmp_box(void); 90129d8bc8SYinghai Lu #else 91129d8bc8SYinghai Lu static inline int is_vsmp_box(void) 92129d8bc8SYinghai Lu { 93129d8bc8SYinghai Lu return 0; 94129d8bc8SYinghai Lu } 95129d8bc8SYinghai Lu #endif 96bb898558SAl Viro extern void xapic_wait_icr_idle(void); 97bb898558SAl Viro extern u32 safe_xapic_wait_icr_idle(void); 98bb898558SAl Viro extern void xapic_icr_write(u32, u32); 99bb898558SAl Viro extern int setup_profiling_timer(unsigned int); 100bb898558SAl Viro 101bb898558SAl Viro static inline void native_apic_mem_write(u32 reg, u32 v) 102bb898558SAl Viro { 103bb898558SAl Viro volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104bb898558SAl Viro 105bb898558SAl Viro alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 106bb898558SAl Viro ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107bb898558SAl Viro ASM_OUTPUT2("0" (v), "m" (*addr))); 108bb898558SAl Viro } 109bb898558SAl Viro 110bb898558SAl Viro static inline u32 native_apic_mem_read(u32 reg) 111bb898558SAl Viro { 112bb898558SAl Viro return *((volatile u32 *)(APIC_BASE + reg)); 113bb898558SAl Viro } 114bb898558SAl Viro 115c1eeb2deSYinghai Lu extern void native_apic_wait_icr_idle(void); 116c1eeb2deSYinghai Lu extern u32 native_safe_apic_wait_icr_idle(void); 117c1eeb2deSYinghai Lu extern void native_apic_icr_write(u32 low, u32 id); 118c1eeb2deSYinghai Lu extern u64 native_apic_icr_read(void); 119c1eeb2deSYinghai Lu 120fc1edaf9SSuresh Siddha extern int x2apic_mode; 121b24696bcSFenghua Yu 122d0b03bd1SHan, Weidong #ifdef CONFIG_X86_X2APIC 123ce4e240cSSuresh Siddha /* 124ce4e240cSSuresh Siddha * Make previous memory operations globally visible before 125ce4e240cSSuresh Siddha * sending the IPI through x2apic wrmsr. We need a serializing instruction or 126ce4e240cSSuresh Siddha * mfence for this. 127ce4e240cSSuresh Siddha */ 128ce4e240cSSuresh Siddha static inline void x2apic_wrmsr_fence(void) 129ce4e240cSSuresh Siddha { 130ce4e240cSSuresh Siddha asm volatile("mfence" : : : "memory"); 131ce4e240cSSuresh Siddha } 132ce4e240cSSuresh Siddha 133bb898558SAl Viro static inline void native_apic_msr_write(u32 reg, u32 v) 134bb898558SAl Viro { 135bb898558SAl Viro if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 136bb898558SAl Viro reg == APIC_LVR) 137bb898558SAl Viro return; 138bb898558SAl Viro 139bb898558SAl Viro wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 140bb898558SAl Viro } 141bb898558SAl Viro 142bb898558SAl Viro static inline u32 native_apic_msr_read(u32 reg) 143bb898558SAl Viro { 144bb898558SAl Viro u32 low, high; 145bb898558SAl Viro 146bb898558SAl Viro if (reg == APIC_DFR) 147bb898558SAl Viro return -1; 148bb898558SAl Viro 149bb898558SAl Viro rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); 150bb898558SAl Viro return low; 151bb898558SAl Viro } 152bb898558SAl Viro 153c1eeb2deSYinghai Lu static inline void native_x2apic_wait_icr_idle(void) 154c1eeb2deSYinghai Lu { 155c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 156c1eeb2deSYinghai Lu return; 157c1eeb2deSYinghai Lu } 158c1eeb2deSYinghai Lu 159c1eeb2deSYinghai Lu static inline u32 native_safe_x2apic_wait_icr_idle(void) 160c1eeb2deSYinghai Lu { 161c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 162c1eeb2deSYinghai Lu return 0; 163c1eeb2deSYinghai Lu } 164c1eeb2deSYinghai Lu 165c1eeb2deSYinghai Lu static inline void native_x2apic_icr_write(u32 low, u32 id) 166c1eeb2deSYinghai Lu { 167c1eeb2deSYinghai Lu wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 168c1eeb2deSYinghai Lu } 169c1eeb2deSYinghai Lu 170c1eeb2deSYinghai Lu static inline u64 native_x2apic_icr_read(void) 171c1eeb2deSYinghai Lu { 172c1eeb2deSYinghai Lu unsigned long val; 173c1eeb2deSYinghai Lu 174c1eeb2deSYinghai Lu rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 175c1eeb2deSYinghai Lu return val; 176c1eeb2deSYinghai Lu } 177c1eeb2deSYinghai Lu 178fc1edaf9SSuresh Siddha extern int x2apic_phys; 179bb898558SAl Viro extern void check_x2apic(void); 180bb898558SAl Viro extern void enable_x2apic(void); 181bb898558SAl Viro extern void x2apic_icr_write(u32 low, u32 id); 182bb898558SAl Viro static inline int x2apic_enabled(void) 183bb898558SAl Viro { 184bb898558SAl Viro int msr, msr2; 185bb898558SAl Viro 186bb898558SAl Viro if (!cpu_has_x2apic) 187bb898558SAl Viro return 0; 188bb898558SAl Viro 189bb898558SAl Viro rdmsr(MSR_IA32_APICBASE, msr, msr2); 190bb898558SAl Viro if (msr & X2APIC_ENABLE) 191bb898558SAl Viro return 1; 192bb898558SAl Viro return 0; 193bb898558SAl Viro } 194fc1edaf9SSuresh Siddha 195fc1edaf9SSuresh Siddha #define x2apic_supported() (cpu_has_x2apic) 196ce69a784SGleb Natapov static inline void x2apic_force_phys(void) 197ce69a784SGleb Natapov { 198ce69a784SGleb Natapov x2apic_phys = 1; 199ce69a784SGleb Natapov } 200bb898558SAl Viro #else 20106cd9a7dSYinghai Lu static inline void check_x2apic(void) 20206cd9a7dSYinghai Lu { 20306cd9a7dSYinghai Lu } 20406cd9a7dSYinghai Lu static inline void enable_x2apic(void) 20506cd9a7dSYinghai Lu { 20606cd9a7dSYinghai Lu } 20706cd9a7dSYinghai Lu static inline int x2apic_enabled(void) 20806cd9a7dSYinghai Lu { 20906cd9a7dSYinghai Lu return 0; 21006cd9a7dSYinghai Lu } 211ce69a784SGleb Natapov static inline void x2apic_force_phys(void) 212ce69a784SGleb Natapov { 213ce69a784SGleb Natapov } 214cf6567feSSuresh Siddha 21593758238SWeidong Han #define x2apic_preenabled 0 216fc1edaf9SSuresh Siddha #define x2apic_supported() 0 217bb898558SAl Viro #endif 218bb898558SAl Viro 21993758238SWeidong Han extern void enable_IR_x2apic(void); 22093758238SWeidong Han 221bb898558SAl Viro extern int get_physical_broadcast(void); 222bb898558SAl Viro 22308306ce6SCyrill Gorcunov extern void apic_disable(void); 224bb898558SAl Viro extern int lapic_get_maxlvt(void); 225bb898558SAl Viro extern void clear_local_APIC(void); 226bb898558SAl Viro extern void connect_bsp_APIC(void); 227bb898558SAl Viro extern void disconnect_bsp_APIC(int virt_wire_setup); 228bb898558SAl Viro extern void disable_local_APIC(void); 229bb898558SAl Viro extern void lapic_shutdown(void); 230bb898558SAl Viro extern int verify_local_APIC(void); 231bb898558SAl Viro extern void cache_APIC_registers(void); 232bb898558SAl Viro extern void sync_Arb_IDs(void); 233bb898558SAl Viro extern void init_bsp_APIC(void); 234bb898558SAl Viro extern void setup_local_APIC(void); 235bb898558SAl Viro extern void end_local_APIC_setup(void); 236bb898558SAl Viro extern void init_apic_mappings(void); 237bb898558SAl Viro extern void setup_boot_APIC_clock(void); 238bb898558SAl Viro extern void setup_secondary_APIC_clock(void); 239bb898558SAl Viro extern int APIC_init_uniprocessor(void); 240bb898558SAl Viro extern void enable_NMI_through_LVT0(void); 241bb898558SAl Viro 242bb898558SAl Viro /* 243bb898558SAl Viro * On 32bit this is mach-xxx local 244bb898558SAl Viro */ 245bb898558SAl Viro #ifdef CONFIG_X86_64 246bb898558SAl Viro extern void early_init_lapic_mapping(void); 247bb898558SAl Viro extern int apic_is_clustered_box(void); 248bb898558SAl Viro #else 249bb898558SAl Viro static inline int apic_is_clustered_box(void) 250bb898558SAl Viro { 251bb898558SAl Viro return 0; 252bb898558SAl Viro } 253bb898558SAl Viro #endif 254bb898558SAl Viro 255bb898558SAl Viro extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 256bb898558SAl Viro extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 257bb898558SAl Viro 258bb898558SAl Viro 259bb898558SAl Viro #else /* !CONFIG_X86_LOCAL_APIC */ 260bb898558SAl Viro static inline void lapic_shutdown(void) { } 261bb898558SAl Viro #define local_apic_timer_c2_ok 1 262bb898558SAl Viro static inline void init_apic_mappings(void) { } 263d3ec5caeSIvan Vecera static inline void disable_local_APIC(void) { } 26408306ce6SCyrill Gorcunov static inline void apic_disable(void) { } 265736decacSThomas Gleixner # define setup_boot_APIC_clock x86_init_noop 266736decacSThomas Gleixner # define setup_secondary_APIC_clock x86_init_noop 267bb898558SAl Viro #endif /* !CONFIG_X86_LOCAL_APIC */ 268bb898558SAl Viro 2691f75ed0cSIngo Molnar #ifdef CONFIG_X86_64 2701f75ed0cSIngo Molnar #define SET_APIC_ID(x) (apic->set_apic_id(x)) 2711f75ed0cSIngo Molnar #else 2721f75ed0cSIngo Molnar 2731f75ed0cSIngo Molnar #endif 2741f75ed0cSIngo Molnar 275e2780a68SIngo Molnar /* 276e2780a68SIngo Molnar * Copyright 2004 James Cleverdon, IBM. 277e2780a68SIngo Molnar * Subject to the GNU Public License, v.2 278e2780a68SIngo Molnar * 279e2780a68SIngo Molnar * Generic APIC sub-arch data struct. 280e2780a68SIngo Molnar * 281e2780a68SIngo Molnar * Hacked for x86-64 by James Cleverdon from i386 architecture code by 282e2780a68SIngo Molnar * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 283e2780a68SIngo Molnar * James Cleverdon. 284e2780a68SIngo Molnar */ 285be163a15SIngo Molnar struct apic { 286e2780a68SIngo Molnar char *name; 287e2780a68SIngo Molnar 288e2780a68SIngo Molnar int (*probe)(void); 289e2780a68SIngo Molnar int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 290e2780a68SIngo Molnar int (*apic_id_registered)(void); 291e2780a68SIngo Molnar 292e2780a68SIngo Molnar u32 irq_delivery_mode; 293e2780a68SIngo Molnar u32 irq_dest_mode; 294e2780a68SIngo Molnar 295e2780a68SIngo Molnar const struct cpumask *(*target_cpus)(void); 296e2780a68SIngo Molnar 297e2780a68SIngo Molnar int disable_esr; 298e2780a68SIngo Molnar 299e2780a68SIngo Molnar int dest_logical; 3007abc0753SCyrill Gorcunov unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 301e2780a68SIngo Molnar unsigned long (*check_apicid_present)(int apicid); 302e2780a68SIngo Molnar 303e2780a68SIngo Molnar void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 304e2780a68SIngo Molnar void (*init_apic_ldr)(void); 305e2780a68SIngo Molnar 3067abc0753SCyrill Gorcunov void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 307e2780a68SIngo Molnar 308e2780a68SIngo Molnar void (*setup_apic_routing)(void); 309e2780a68SIngo Molnar int (*multi_timer_check)(int apic, int irq); 310e2780a68SIngo Molnar int (*apicid_to_node)(int logical_apicid); 311e2780a68SIngo Molnar int (*cpu_to_logical_apicid)(int cpu); 312e2780a68SIngo Molnar int (*cpu_present_to_apicid)(int mps_cpu); 3137abc0753SCyrill Gorcunov void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 314e2780a68SIngo Molnar void (*setup_portio_remap)(void); 315e11dadabSThomas Gleixner int (*check_phys_apicid_present)(int phys_apicid); 316e2780a68SIngo Molnar void (*enable_apic_mode)(void); 317e2780a68SIngo Molnar int (*phys_pkg_id)(int cpuid_apic, int index_msb); 318e2780a68SIngo Molnar 319e2780a68SIngo Molnar /* 320be163a15SIngo Molnar * When one of the next two hooks returns 1 the apic 321e2780a68SIngo Molnar * is switched to this. Essentially they are additional 322e2780a68SIngo Molnar * probe functions: 323e2780a68SIngo Molnar */ 324e2780a68SIngo Molnar int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 325e2780a68SIngo Molnar 326e2780a68SIngo Molnar unsigned int (*get_apic_id)(unsigned long x); 327e2780a68SIngo Molnar unsigned long (*set_apic_id)(unsigned int id); 328e2780a68SIngo Molnar unsigned long apic_id_mask; 329e2780a68SIngo Molnar 330e2780a68SIngo Molnar unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 331e2780a68SIngo Molnar unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 332e2780a68SIngo Molnar const struct cpumask *andmask); 333e2780a68SIngo Molnar 334e2780a68SIngo Molnar /* ipi */ 335e2780a68SIngo Molnar void (*send_IPI_mask)(const struct cpumask *mask, int vector); 336e2780a68SIngo Molnar void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 337e2780a68SIngo Molnar int vector); 338e2780a68SIngo Molnar void (*send_IPI_allbutself)(int vector); 339e2780a68SIngo Molnar void (*send_IPI_all)(int vector); 340e2780a68SIngo Molnar void (*send_IPI_self)(int vector); 341e2780a68SIngo Molnar 342e2780a68SIngo Molnar /* wakeup_secondary_cpu */ 3431f5bcabfSIngo Molnar int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 344e2780a68SIngo Molnar 345e2780a68SIngo Molnar int trampoline_phys_low; 346e2780a68SIngo Molnar int trampoline_phys_high; 347e2780a68SIngo Molnar 348e2780a68SIngo Molnar void (*wait_for_init_deassert)(atomic_t *deassert); 349e2780a68SIngo Molnar void (*smp_callin_clear_local_apic)(void); 350e2780a68SIngo Molnar void (*inquire_remote_apic)(int apicid); 351e2780a68SIngo Molnar 352e2780a68SIngo Molnar /* apic ops */ 353e2780a68SIngo Molnar u32 (*read)(u32 reg); 354e2780a68SIngo Molnar void (*write)(u32 reg, u32 v); 355e2780a68SIngo Molnar u64 (*icr_read)(void); 356e2780a68SIngo Molnar void (*icr_write)(u32 low, u32 high); 357e2780a68SIngo Molnar void (*wait_icr_idle)(void); 358e2780a68SIngo Molnar u32 (*safe_wait_icr_idle)(void); 359e2780a68SIngo Molnar }; 360e2780a68SIngo Molnar 3610917c01fSIngo Molnar /* 3620917c01fSIngo Molnar * Pointer to the local APIC driver in use on this system (there's 3630917c01fSIngo Molnar * always just one such driver in use - the kernel decides via an 3640917c01fSIngo Molnar * early probing process which one it picks - and then sticks to it): 3650917c01fSIngo Molnar */ 366be163a15SIngo Molnar extern struct apic *apic; 3670917c01fSIngo Molnar 3680917c01fSIngo Molnar /* 3690917c01fSIngo Molnar * APIC functionality to boot other CPUs - only used on SMP: 3700917c01fSIngo Molnar */ 3710917c01fSIngo Molnar #ifdef CONFIG_SMP 3722b6163bfSYinghai Lu extern atomic_t init_deasserted; 3732b6163bfSYinghai Lu extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 3740917c01fSIngo Molnar #endif 375e2780a68SIngo Molnar 376e2780a68SIngo Molnar static inline u32 apic_read(u32 reg) 377e2780a68SIngo Molnar { 378e2780a68SIngo Molnar return apic->read(reg); 379e2780a68SIngo Molnar } 380e2780a68SIngo Molnar 381e2780a68SIngo Molnar static inline void apic_write(u32 reg, u32 val) 382e2780a68SIngo Molnar { 383e2780a68SIngo Molnar apic->write(reg, val); 384e2780a68SIngo Molnar } 385e2780a68SIngo Molnar 386e2780a68SIngo Molnar static inline u64 apic_icr_read(void) 387e2780a68SIngo Molnar { 388e2780a68SIngo Molnar return apic->icr_read(); 389e2780a68SIngo Molnar } 390e2780a68SIngo Molnar 391e2780a68SIngo Molnar static inline void apic_icr_write(u32 low, u32 high) 392e2780a68SIngo Molnar { 393e2780a68SIngo Molnar apic->icr_write(low, high); 394e2780a68SIngo Molnar } 395e2780a68SIngo Molnar 396e2780a68SIngo Molnar static inline void apic_wait_icr_idle(void) 397e2780a68SIngo Molnar { 398e2780a68SIngo Molnar apic->wait_icr_idle(); 399e2780a68SIngo Molnar } 400e2780a68SIngo Molnar 401e2780a68SIngo Molnar static inline u32 safe_apic_wait_icr_idle(void) 402e2780a68SIngo Molnar { 403e2780a68SIngo Molnar return apic->safe_wait_icr_idle(); 404e2780a68SIngo Molnar } 405e2780a68SIngo Molnar 406e2780a68SIngo Molnar 407e2780a68SIngo Molnar static inline void ack_APIC_irq(void) 408e2780a68SIngo Molnar { 409b2b35259SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 410e2780a68SIngo Molnar /* 411e2780a68SIngo Molnar * ack_APIC_irq() actually gets compiled as a single instruction 412e2780a68SIngo Molnar * ... yummie. 413e2780a68SIngo Molnar */ 414e2780a68SIngo Molnar 415e2780a68SIngo Molnar /* Docs say use 0 for future compatibility */ 416e2780a68SIngo Molnar apic_write(APIC_EOI, 0); 417b2b35259SIngo Molnar #endif 418e2780a68SIngo Molnar } 419e2780a68SIngo Molnar 420e2780a68SIngo Molnar static inline unsigned default_get_apic_id(unsigned long x) 421e2780a68SIngo Molnar { 422e2780a68SIngo Molnar unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 423e2780a68SIngo Molnar 42442937e81SAndreas Herrmann if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 425e2780a68SIngo Molnar return (x >> 24) & 0xFF; 426e2780a68SIngo Molnar else 427e2780a68SIngo Molnar return (x >> 24) & 0x0F; 428e2780a68SIngo Molnar } 429e2780a68SIngo Molnar 430e2780a68SIngo Molnar /* 431e2780a68SIngo Molnar * Warm reset vector default position: 432e2780a68SIngo Molnar */ 433e2780a68SIngo Molnar #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 434e2780a68SIngo Molnar #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 435e2780a68SIngo Molnar 4362b6163bfSYinghai Lu #ifdef CONFIG_X86_64 437be163a15SIngo Molnar extern struct apic apic_flat; 438be163a15SIngo Molnar extern struct apic apic_physflat; 439be163a15SIngo Molnar extern struct apic apic_x2apic_cluster; 440be163a15SIngo Molnar extern struct apic apic_x2apic_phys; 441e2780a68SIngo Molnar extern int default_acpi_madt_oem_check(char *, char *); 442e2780a68SIngo Molnar 443e2780a68SIngo Molnar extern void apic_send_IPI_self(int vector); 444e2780a68SIngo Molnar 445be163a15SIngo Molnar extern struct apic apic_x2apic_uv_x; 446e2780a68SIngo Molnar DECLARE_PER_CPU(int, x2apic_extra_bits); 447e2780a68SIngo Molnar 448e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 449e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 450e2780a68SIngo Molnar #endif 451e2780a68SIngo Molnar 452e2780a68SIngo Molnar static inline void default_wait_for_init_deassert(atomic_t *deassert) 453e2780a68SIngo Molnar { 454e2780a68SIngo Molnar while (!atomic_read(deassert)) 455e2780a68SIngo Molnar cpu_relax(); 456e2780a68SIngo Molnar return; 457e2780a68SIngo Molnar } 458e2780a68SIngo Molnar 459e2780a68SIngo Molnar extern void generic_bigsmp_probe(void); 460e2780a68SIngo Molnar 461e2780a68SIngo Molnar 462e2780a68SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 463e2780a68SIngo Molnar 464e2780a68SIngo Molnar #include <asm/smp.h> 465e2780a68SIngo Molnar 466e2780a68SIngo Molnar #define APIC_DFR_VALUE (APIC_DFR_FLAT) 467e2780a68SIngo Molnar 468e2780a68SIngo Molnar static inline const struct cpumask *default_target_cpus(void) 469e2780a68SIngo Molnar { 470e2780a68SIngo Molnar #ifdef CONFIG_SMP 471e2780a68SIngo Molnar return cpu_online_mask; 472e2780a68SIngo Molnar #else 473e2780a68SIngo Molnar return cpumask_of(0); 474e2780a68SIngo Molnar #endif 475e2780a68SIngo Molnar } 476e2780a68SIngo Molnar 477e2780a68SIngo Molnar DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 478e2780a68SIngo Molnar 479e2780a68SIngo Molnar 480e2780a68SIngo Molnar static inline unsigned int read_apic_id(void) 481e2780a68SIngo Molnar { 482e2780a68SIngo Molnar unsigned int reg; 483e2780a68SIngo Molnar 484e2780a68SIngo Molnar reg = apic_read(APIC_ID); 485e2780a68SIngo Molnar 486e2780a68SIngo Molnar return apic->get_apic_id(reg); 487e2780a68SIngo Molnar } 488e2780a68SIngo Molnar 489e2780a68SIngo Molnar extern void default_setup_apic_routing(void); 490e2780a68SIngo Molnar 4919844ab11SCyrill Gorcunov extern struct apic apic_noop; 4929844ab11SCyrill Gorcunov 493e2780a68SIngo Molnar #ifdef CONFIG_X86_32 4942c1b284eSJaswinder Singh Rajput 4952c1b284eSJaswinder Singh Rajput extern struct apic apic_default; 4962c1b284eSJaswinder Singh Rajput 497e2780a68SIngo Molnar /* 498e2780a68SIngo Molnar * Set up the logical destination ID. 499e2780a68SIngo Molnar * 500e2780a68SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 501e2780a68SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 502e2780a68SIngo Molnar * document number 292116). So here it goes... 503e2780a68SIngo Molnar */ 504e2780a68SIngo Molnar extern void default_init_apic_ldr(void); 505e2780a68SIngo Molnar 506e2780a68SIngo Molnar static inline int default_apic_id_registered(void) 507e2780a68SIngo Molnar { 508e2780a68SIngo Molnar return physid_isset(read_apic_id(), phys_cpu_present_map); 509e2780a68SIngo Molnar } 510e2780a68SIngo Molnar 511f56e5034SYinghai Lu static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 512f56e5034SYinghai Lu { 513f56e5034SYinghai Lu return cpuid_apic >> index_msb; 514f56e5034SYinghai Lu } 515f56e5034SYinghai Lu 516f56e5034SYinghai Lu extern int default_apicid_to_node(int logical_apicid); 517f56e5034SYinghai Lu 518f56e5034SYinghai Lu #endif 519f56e5034SYinghai Lu 520e2780a68SIngo Molnar static inline unsigned int 521e2780a68SIngo Molnar default_cpu_mask_to_apicid(const struct cpumask *cpumask) 522e2780a68SIngo Molnar { 523f56e5034SYinghai Lu return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 524e2780a68SIngo Molnar } 525e2780a68SIngo Molnar 526e2780a68SIngo Molnar static inline unsigned int 527e2780a68SIngo Molnar default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 528e2780a68SIngo Molnar const struct cpumask *andmask) 529e2780a68SIngo Molnar { 530e2780a68SIngo Molnar unsigned long mask1 = cpumask_bits(cpumask)[0]; 531e2780a68SIngo Molnar unsigned long mask2 = cpumask_bits(andmask)[0]; 532e2780a68SIngo Molnar unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 533e2780a68SIngo Molnar 534e2780a68SIngo Molnar return (unsigned int)(mask1 & mask2 & mask3); 535e2780a68SIngo Molnar } 536e2780a68SIngo Molnar 5377abc0753SCyrill Gorcunov static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 538e2780a68SIngo Molnar { 5397abc0753SCyrill Gorcunov return physid_isset(apicid, *map); 540e2780a68SIngo Molnar } 541e2780a68SIngo Molnar 542e2780a68SIngo Molnar static inline unsigned long default_check_apicid_present(int bit) 543e2780a68SIngo Molnar { 544e2780a68SIngo Molnar return physid_isset(bit, phys_cpu_present_map); 545e2780a68SIngo Molnar } 546e2780a68SIngo Molnar 5477abc0753SCyrill Gorcunov static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 548e2780a68SIngo Molnar { 5497abc0753SCyrill Gorcunov *retmap = *phys_map; 550e2780a68SIngo Molnar } 551e2780a68SIngo Molnar 552e2780a68SIngo Molnar /* Mapping from cpu number to logical apicid */ 553e2780a68SIngo Molnar static inline int default_cpu_to_logical_apicid(int cpu) 554e2780a68SIngo Molnar { 555e2780a68SIngo Molnar return 1 << cpu; 556e2780a68SIngo Molnar } 557e2780a68SIngo Molnar 558e2780a68SIngo Molnar static inline int __default_cpu_present_to_apicid(int mps_cpu) 559e2780a68SIngo Molnar { 560e2780a68SIngo Molnar if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 561e2780a68SIngo Molnar return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 562e2780a68SIngo Molnar else 563e2780a68SIngo Molnar return BAD_APICID; 564e2780a68SIngo Molnar } 565e2780a68SIngo Molnar 566e2780a68SIngo Molnar static inline int 567e11dadabSThomas Gleixner __default_check_phys_apicid_present(int phys_apicid) 568e2780a68SIngo Molnar { 569e11dadabSThomas Gleixner return physid_isset(phys_apicid, phys_cpu_present_map); 570e2780a68SIngo Molnar } 571e2780a68SIngo Molnar 572e2780a68SIngo Molnar #ifdef CONFIG_X86_32 573e2780a68SIngo Molnar static inline int default_cpu_present_to_apicid(int mps_cpu) 574e2780a68SIngo Molnar { 575e2780a68SIngo Molnar return __default_cpu_present_to_apicid(mps_cpu); 576e2780a68SIngo Molnar } 577e2780a68SIngo Molnar 578e2780a68SIngo Molnar static inline int 579e11dadabSThomas Gleixner default_check_phys_apicid_present(int phys_apicid) 580e2780a68SIngo Molnar { 581e11dadabSThomas Gleixner return __default_check_phys_apicid_present(phys_apicid); 582e2780a68SIngo Molnar } 583e2780a68SIngo Molnar #else 584e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 585e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 586e2780a68SIngo Molnar #endif 587e2780a68SIngo Molnar 588e2780a68SIngo Molnar #endif /* CONFIG_X86_LOCAL_APIC */ 589e2780a68SIngo Molnar 5902f205bc4SIngo Molnar #ifdef CONFIG_X86_32 5912f205bc4SIngo Molnar extern u8 cpu_2_logical_apicid[NR_CPUS]; 5922f205bc4SIngo Molnar #endif 5932f205bc4SIngo Molnar 5941965aae3SH. Peter Anvin #endif /* _ASM_X86_APIC_H */ 595