11965aae3SH. Peter Anvin #ifndef _ASM_X86_APIC_H 21965aae3SH. Peter Anvin #define _ASM_X86_APIC_H 3bb898558SAl Viro 4e2780a68SIngo Molnar #include <linux/cpumask.h> 5e2780a68SIngo Molnar #include <linux/pm.h> 6bb898558SAl Viro 7bb898558SAl Viro #include <asm/alternative.h> 8bb898558SAl Viro #include <asm/cpufeature.h> 9e2780a68SIngo Molnar #include <asm/processor.h> 10e2780a68SIngo Molnar #include <asm/apicdef.h> 1160063497SArun Sharma #include <linux/atomic.h> 12e2780a68SIngo Molnar #include <asm/fixmap.h> 13e2780a68SIngo Molnar #include <asm/mpspec.h> 14bb898558SAl Viro #include <asm/msr.h> 15eddc0e92SSeiji Aguchi #include <asm/idle.h> 16bb898558SAl Viro 17bb898558SAl Viro #define ARCH_APICTIMER_STOPS_ON_C3 1 18bb898558SAl Viro 19bb898558SAl Viro /* 20bb898558SAl Viro * Debugging macros 21bb898558SAl Viro */ 22bb898558SAl Viro #define APIC_QUIET 0 23bb898558SAl Viro #define APIC_VERBOSE 1 24bb898558SAl Viro #define APIC_DEBUG 2 25bb898558SAl Viro 26bb898558SAl Viro /* 27bb898558SAl Viro * Define the default level of output to be very little 28bb898558SAl Viro * This can be turned up by using apic=verbose for more 29bb898558SAl Viro * information and apic=debug for _lots_ of information. 30bb898558SAl Viro * apic_verbosity is defined in apic.c 31bb898558SAl Viro */ 32bb898558SAl Viro #define apic_printk(v, s, a...) do { \ 33bb898558SAl Viro if ((v) <= apic_verbosity) \ 34bb898558SAl Viro printk(s, ##a); \ 35bb898558SAl Viro } while (0) 36bb898558SAl Viro 37bb898558SAl Viro 38160d8dacSIngo Molnar #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39bb898558SAl Viro extern void generic_apic_probe(void); 40160d8dacSIngo Molnar #else 41160d8dacSIngo Molnar static inline void generic_apic_probe(void) 42160d8dacSIngo Molnar { 43160d8dacSIngo Molnar } 44160d8dacSIngo Molnar #endif 45bb898558SAl Viro 46bb898558SAl Viro #ifdef CONFIG_X86_LOCAL_APIC 47bb898558SAl Viro 48bb898558SAl Viro extern unsigned int apic_verbosity; 49bb898558SAl Viro extern int local_apic_timer_c2_ok; 50bb898558SAl Viro 51bb898558SAl Viro extern int disable_apic; 521ade93efSJacob Pan extern unsigned int lapic_timer_frequency; 530939e4fdSIngo Molnar 540939e4fdSIngo Molnar #ifdef CONFIG_SMP 550939e4fdSIngo Molnar extern void __inquire_remote_apic(int apicid); 560939e4fdSIngo Molnar #else /* CONFIG_SMP */ 570939e4fdSIngo Molnar static inline void __inquire_remote_apic(int apicid) 580939e4fdSIngo Molnar { 590939e4fdSIngo Molnar } 600939e4fdSIngo Molnar #endif /* CONFIG_SMP */ 610939e4fdSIngo Molnar 620939e4fdSIngo Molnar static inline void default_inquire_remote_apic(int apicid) 630939e4fdSIngo Molnar { 640939e4fdSIngo Molnar if (apic_verbosity >= APIC_DEBUG) 650939e4fdSIngo Molnar __inquire_remote_apic(apicid); 660939e4fdSIngo Molnar } 670939e4fdSIngo Molnar 68bb898558SAl Viro /* 698312136fSCyrill Gorcunov * With 82489DX we can't rely on apic feature bit 708312136fSCyrill Gorcunov * retrieved via cpuid but still have to deal with 718312136fSCyrill Gorcunov * such an apic chip so we assume that SMP configuration 728312136fSCyrill Gorcunov * is found from MP table (64bit case uses ACPI mostly 738312136fSCyrill Gorcunov * which set smp presence flag as well so we are safe 748312136fSCyrill Gorcunov * to use this helper too). 758312136fSCyrill Gorcunov */ 768312136fSCyrill Gorcunov static inline bool apic_from_smp_config(void) 778312136fSCyrill Gorcunov { 788312136fSCyrill Gorcunov return smp_found_config && !disable_apic; 798312136fSCyrill Gorcunov } 808312136fSCyrill Gorcunov 818312136fSCyrill Gorcunov /* 82bb898558SAl Viro * Basic functions accessing APICs. 83bb898558SAl Viro */ 84bb898558SAl Viro #ifdef CONFIG_PARAVIRT 85bb898558SAl Viro #include <asm/paravirt.h> 86bb898558SAl Viro #endif 87bb898558SAl Viro 88bb898558SAl Viro extern int setup_profiling_timer(unsigned int); 89bb898558SAl Viro 90bb898558SAl Viro static inline void native_apic_mem_write(u32 reg, u32 v) 91bb898558SAl Viro { 92bb898558SAl Viro volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 93bb898558SAl Viro 949b13a93dSBorislav Petkov alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, 95bb898558SAl Viro ASM_OUTPUT2("=r" (v), "=m" (*addr)), 96bb898558SAl Viro ASM_OUTPUT2("0" (v), "m" (*addr))); 97bb898558SAl Viro } 98bb898558SAl Viro 99bb898558SAl Viro static inline u32 native_apic_mem_read(u32 reg) 100bb898558SAl Viro { 101bb898558SAl Viro return *((volatile u32 *)(APIC_BASE + reg)); 102bb898558SAl Viro } 103bb898558SAl Viro 104c1eeb2deSYinghai Lu extern void native_apic_wait_icr_idle(void); 105c1eeb2deSYinghai Lu extern u32 native_safe_apic_wait_icr_idle(void); 106c1eeb2deSYinghai Lu extern void native_apic_icr_write(u32 low, u32 id); 107c1eeb2deSYinghai Lu extern u64 native_apic_icr_read(void); 108c1eeb2deSYinghai Lu 1098d806960SThomas Gleixner static inline bool apic_is_x2apic_enabled(void) 1108d806960SThomas Gleixner { 1118d806960SThomas Gleixner u64 msr; 1128d806960SThomas Gleixner 1138d806960SThomas Gleixner if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 1148d806960SThomas Gleixner return false; 1158d806960SThomas Gleixner return msr & X2APIC_ENABLE; 1168d806960SThomas Gleixner } 1178d806960SThomas Gleixner 118d0b03bd1SHan, Weidong #ifdef CONFIG_X86_X2APIC 119ce4e240cSSuresh Siddha /* 120ce4e240cSSuresh Siddha * Make previous memory operations globally visible before 121ce4e240cSSuresh Siddha * sending the IPI through x2apic wrmsr. We need a serializing instruction or 122ce4e240cSSuresh Siddha * mfence for this. 123ce4e240cSSuresh Siddha */ 124ce4e240cSSuresh Siddha static inline void x2apic_wrmsr_fence(void) 125ce4e240cSSuresh Siddha { 126ce4e240cSSuresh Siddha asm volatile("mfence" : : : "memory"); 127ce4e240cSSuresh Siddha } 128ce4e240cSSuresh Siddha 129bb898558SAl Viro static inline void native_apic_msr_write(u32 reg, u32 v) 130bb898558SAl Viro { 131bb898558SAl Viro if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 132bb898558SAl Viro reg == APIC_LVR) 133bb898558SAl Viro return; 134bb898558SAl Viro 135bb898558SAl Viro wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 136bb898558SAl Viro } 137bb898558SAl Viro 1380ab711aeSMichael S. Tsirkin static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 1390ab711aeSMichael S. Tsirkin { 1400ab711aeSMichael S. Tsirkin wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 1410ab711aeSMichael S. Tsirkin } 1420ab711aeSMichael S. Tsirkin 143bb898558SAl Viro static inline u32 native_apic_msr_read(u32 reg) 144bb898558SAl Viro { 1450059b243SAndi Kleen u64 msr; 146bb898558SAl Viro 147bb898558SAl Viro if (reg == APIC_DFR) 148bb898558SAl Viro return -1; 149bb898558SAl Viro 1500059b243SAndi Kleen rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 1510059b243SAndi Kleen return (u32)msr; 152bb898558SAl Viro } 153bb898558SAl Viro 154c1eeb2deSYinghai Lu static inline void native_x2apic_wait_icr_idle(void) 155c1eeb2deSYinghai Lu { 156c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 157c1eeb2deSYinghai Lu return; 158c1eeb2deSYinghai Lu } 159c1eeb2deSYinghai Lu 160c1eeb2deSYinghai Lu static inline u32 native_safe_x2apic_wait_icr_idle(void) 161c1eeb2deSYinghai Lu { 162c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 163c1eeb2deSYinghai Lu return 0; 164c1eeb2deSYinghai Lu } 165c1eeb2deSYinghai Lu 166c1eeb2deSYinghai Lu static inline void native_x2apic_icr_write(u32 low, u32 id) 167c1eeb2deSYinghai Lu { 168c1eeb2deSYinghai Lu wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 169c1eeb2deSYinghai Lu } 170c1eeb2deSYinghai Lu 171c1eeb2deSYinghai Lu static inline u64 native_x2apic_icr_read(void) 172c1eeb2deSYinghai Lu { 173c1eeb2deSYinghai Lu unsigned long val; 174c1eeb2deSYinghai Lu 175c1eeb2deSYinghai Lu rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 176c1eeb2deSYinghai Lu return val; 177c1eeb2deSYinghai Lu } 178c1eeb2deSYinghai Lu 17981a46dd8SThomas Gleixner extern int x2apic_mode; 180fc1edaf9SSuresh Siddha extern int x2apic_phys; 181d524165cSThomas Gleixner extern void __init check_x2apic(void); 182bb898558SAl Viro extern void enable_x2apic(void); 183bb898558SAl Viro static inline int x2apic_enabled(void) 184bb898558SAl Viro { 1858d806960SThomas Gleixner return cpu_has_x2apic && apic_is_x2apic_enabled(); 186bb898558SAl Viro } 187fc1edaf9SSuresh Siddha 188fc1edaf9SSuresh Siddha #define x2apic_supported() (cpu_has_x2apic) 189bb898558SAl Viro #else 19055eae7deSThomas Gleixner static inline void disable_x2apic(void) { } 19155eae7deSThomas Gleixner static inline void check_x2apic(void) { } 19255eae7deSThomas Gleixner static inline void enable_x2apic(void) { } 19355eae7deSThomas Gleixner static inline int x2apic_enabled(void) { return 0; } 194cf6567feSSuresh Siddha 19581a46dd8SThomas Gleixner #define x2apic_mode (0) 19681a46dd8SThomas Gleixner #define x2apic_supported() (0) 197bb898558SAl Viro #endif 198bb898558SAl Viro 19993758238SWeidong Han extern void enable_IR_x2apic(void); 20093758238SWeidong Han 201bb898558SAl Viro extern int get_physical_broadcast(void); 202bb898558SAl Viro 203bb898558SAl Viro extern int lapic_get_maxlvt(void); 204bb898558SAl Viro extern void clear_local_APIC(void); 205bb898558SAl Viro extern void connect_bsp_APIC(void); 206bb898558SAl Viro extern void disconnect_bsp_APIC(int virt_wire_setup); 207bb898558SAl Viro extern void disable_local_APIC(void); 208bb898558SAl Viro extern void lapic_shutdown(void); 209bb898558SAl Viro extern int verify_local_APIC(void); 210bb898558SAl Viro extern void sync_Arb_IDs(void); 211bb898558SAl Viro extern void init_bsp_APIC(void); 212bb898558SAl Viro extern void setup_local_APIC(void); 213bb898558SAl Viro extern void end_local_APIC_setup(void); 2142fb270f3SJan Beulich extern void bsp_end_local_APIC_setup(void); 215bb898558SAl Viro extern void init_apic_mappings(void); 216c0104d38SYinghai Lu void register_lapic_address(unsigned long address); 217bb898558SAl Viro extern void setup_boot_APIC_clock(void); 218bb898558SAl Viro extern void setup_secondary_APIC_clock(void); 219bb898558SAl Viro extern int APIC_init_uniprocessor(void); 220a906fdaaSThomas Gleixner extern int apic_force_enable(unsigned long addr); 221bb898558SAl Viro 222bb898558SAl Viro /* 223bb898558SAl Viro * On 32bit this is mach-xxx local 224bb898558SAl Viro */ 225bb898558SAl Viro #ifdef CONFIG_X86_64 226bb898558SAl Viro extern int apic_is_clustered_box(void); 227bb898558SAl Viro #else 228bb898558SAl Viro static inline int apic_is_clustered_box(void) 229bb898558SAl Viro { 230bb898558SAl Viro return 0; 231bb898558SAl Viro } 232bb898558SAl Viro #endif 233bb898558SAl Viro 23427afdf20SRobert Richter extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 235bb898558SAl Viro 236bb898558SAl Viro #else /* !CONFIG_X86_LOCAL_APIC */ 237bb898558SAl Viro static inline void lapic_shutdown(void) { } 238bb898558SAl Viro #define local_apic_timer_c2_ok 1 239bb898558SAl Viro static inline void init_apic_mappings(void) { } 240d3ec5caeSIvan Vecera static inline void disable_local_APIC(void) { } 241736decacSThomas Gleixner # define setup_boot_APIC_clock x86_init_noop 242736decacSThomas Gleixner # define setup_secondary_APIC_clock x86_init_noop 243bb898558SAl Viro #endif /* !CONFIG_X86_LOCAL_APIC */ 244bb898558SAl Viro 2451f75ed0cSIngo Molnar #ifdef CONFIG_X86_64 2461f75ed0cSIngo Molnar #define SET_APIC_ID(x) (apic->set_apic_id(x)) 2471f75ed0cSIngo Molnar #else 2481f75ed0cSIngo Molnar 2491f75ed0cSIngo Molnar #endif 2501f75ed0cSIngo Molnar 251e2780a68SIngo Molnar /* 252e2780a68SIngo Molnar * Copyright 2004 James Cleverdon, IBM. 253e2780a68SIngo Molnar * Subject to the GNU Public License, v.2 254e2780a68SIngo Molnar * 255e2780a68SIngo Molnar * Generic APIC sub-arch data struct. 256e2780a68SIngo Molnar * 257e2780a68SIngo Molnar * Hacked for x86-64 by James Cleverdon from i386 architecture code by 258e2780a68SIngo Molnar * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 259e2780a68SIngo Molnar * James Cleverdon. 260e2780a68SIngo Molnar */ 261be163a15SIngo Molnar struct apic { 262e2780a68SIngo Molnar char *name; 263e2780a68SIngo Molnar 264e2780a68SIngo Molnar int (*probe)(void); 265e2780a68SIngo Molnar int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 266fa63030eSDaniel J Blueman int (*apic_id_valid)(int apicid); 267e2780a68SIngo Molnar int (*apic_id_registered)(void); 268e2780a68SIngo Molnar 269e2780a68SIngo Molnar u32 irq_delivery_mode; 270e2780a68SIngo Molnar u32 irq_dest_mode; 271e2780a68SIngo Molnar 272e2780a68SIngo Molnar const struct cpumask *(*target_cpus)(void); 273e2780a68SIngo Molnar 274e2780a68SIngo Molnar int disable_esr; 275e2780a68SIngo Molnar 276e2780a68SIngo Molnar int dest_logical; 2777abc0753SCyrill Gorcunov unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 278e2780a68SIngo Molnar 2791ac322d0SSuresh Siddha void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 2801ac322d0SSuresh Siddha const struct cpumask *mask); 281e2780a68SIngo Molnar void (*init_apic_ldr)(void); 282e2780a68SIngo Molnar 2837abc0753SCyrill Gorcunov void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 284e2780a68SIngo Molnar 285e2780a68SIngo Molnar void (*setup_apic_routing)(void); 286e2780a68SIngo Molnar int (*cpu_present_to_apicid)(int mps_cpu); 2877abc0753SCyrill Gorcunov void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 288e11dadabSThomas Gleixner int (*check_phys_apicid_present)(int phys_apicid); 289e2780a68SIngo Molnar int (*phys_pkg_id)(int cpuid_apic, int index_msb); 290e2780a68SIngo Molnar 291e2780a68SIngo Molnar unsigned int (*get_apic_id)(unsigned long x); 292e2780a68SIngo Molnar unsigned long (*set_apic_id)(unsigned int id); 293e2780a68SIngo Molnar unsigned long apic_id_mask; 294e2780a68SIngo Molnar 295ff164324SAlexander Gordeev int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 296ff164324SAlexander Gordeev const struct cpumask *andmask, 297ff164324SAlexander Gordeev unsigned int *apicid); 298e2780a68SIngo Molnar 299e2780a68SIngo Molnar /* ipi */ 300e2780a68SIngo Molnar void (*send_IPI_mask)(const struct cpumask *mask, int vector); 301e2780a68SIngo Molnar void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 302e2780a68SIngo Molnar int vector); 303e2780a68SIngo Molnar void (*send_IPI_allbutself)(int vector); 304e2780a68SIngo Molnar void (*send_IPI_all)(int vector); 305e2780a68SIngo Molnar void (*send_IPI_self)(int vector); 306e2780a68SIngo Molnar 307e2780a68SIngo Molnar /* wakeup_secondary_cpu */ 3081f5bcabfSIngo Molnar int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 309e2780a68SIngo Molnar 310465822cfSDavid Rientjes bool wait_for_init_deassert; 311e2780a68SIngo Molnar void (*inquire_remote_apic)(int apicid); 312e2780a68SIngo Molnar 313e2780a68SIngo Molnar /* apic ops */ 314e2780a68SIngo Molnar u32 (*read)(u32 reg); 315e2780a68SIngo Molnar void (*write)(u32 reg, u32 v); 3162a43195dSMichael S. Tsirkin /* 3172a43195dSMichael S. Tsirkin * ->eoi_write() has the same signature as ->write(). 3182a43195dSMichael S. Tsirkin * 3192a43195dSMichael S. Tsirkin * Drivers can support both ->eoi_write() and ->write() by passing the same 3202a43195dSMichael S. Tsirkin * callback value. Kernel can override ->eoi_write() and fall back 3212a43195dSMichael S. Tsirkin * on write for EOI. 3222a43195dSMichael S. Tsirkin */ 3232a43195dSMichael S. Tsirkin void (*eoi_write)(u32 reg, u32 v); 324e2780a68SIngo Molnar u64 (*icr_read)(void); 325e2780a68SIngo Molnar void (*icr_write)(u32 low, u32 high); 326e2780a68SIngo Molnar void (*wait_icr_idle)(void); 327e2780a68SIngo Molnar u32 (*safe_wait_icr_idle)(void); 328acb8bc09STejun Heo 329acb8bc09STejun Heo #ifdef CONFIG_X86_32 330acb8bc09STejun Heo /* 331acb8bc09STejun Heo * Called very early during boot from get_smp_config(). It should 332acb8bc09STejun Heo * return the logical apicid. x86_[bios]_cpu_to_apicid is 333acb8bc09STejun Heo * initialized before this function is called. 334acb8bc09STejun Heo * 335acb8bc09STejun Heo * If logical apicid can't be determined that early, the function 336acb8bc09STejun Heo * may return BAD_APICID. Logical apicid will be configured after 337acb8bc09STejun Heo * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 338acb8bc09STejun Heo * won't be applied properly during early boot in this case. 339acb8bc09STejun Heo */ 340acb8bc09STejun Heo int (*x86_32_early_logical_apicid)(int cpu); 341acb8bc09STejun Heo #endif 342e2780a68SIngo Molnar }; 343e2780a68SIngo Molnar 3440917c01fSIngo Molnar /* 3450917c01fSIngo Molnar * Pointer to the local APIC driver in use on this system (there's 3460917c01fSIngo Molnar * always just one such driver in use - the kernel decides via an 3470917c01fSIngo Molnar * early probing process which one it picks - and then sticks to it): 3480917c01fSIngo Molnar */ 349be163a15SIngo Molnar extern struct apic *apic; 3500917c01fSIngo Molnar 3510917c01fSIngo Molnar /* 352107e0e0cSSuresh Siddha * APIC drivers are probed based on how they are listed in the .apicdrivers 353107e0e0cSSuresh Siddha * section. So the order is important and enforced by the ordering 354107e0e0cSSuresh Siddha * of different apic driver files in the Makefile. 355107e0e0cSSuresh Siddha * 356107e0e0cSSuresh Siddha * For the files having two apic drivers, we use apic_drivers() 357107e0e0cSSuresh Siddha * to enforce the order with in them. 358107e0e0cSSuresh Siddha */ 359107e0e0cSSuresh Siddha #define apic_driver(sym) \ 36075fdd155SAndi Kleen static const struct apic *__apicdrivers_##sym __used \ 361107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 362107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym } 363107e0e0cSSuresh Siddha 364107e0e0cSSuresh Siddha #define apic_drivers(sym1, sym2) \ 365107e0e0cSSuresh Siddha static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 366107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 367107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym1, &sym2 } 368107e0e0cSSuresh Siddha 369107e0e0cSSuresh Siddha extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 370107e0e0cSSuresh Siddha 371107e0e0cSSuresh Siddha /* 3720917c01fSIngo Molnar * APIC functionality to boot other CPUs - only used on SMP: 3730917c01fSIngo Molnar */ 3740917c01fSIngo Molnar #ifdef CONFIG_SMP 3752b6163bfSYinghai Lu extern atomic_t init_deasserted; 3762b6163bfSYinghai Lu extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 3770917c01fSIngo Molnar #endif 378e2780a68SIngo Molnar 379d674cd19SCyrill Gorcunov #ifdef CONFIG_X86_LOCAL_APIC 380346b46beSFernando Luis Vázquez Cao 381e2780a68SIngo Molnar static inline u32 apic_read(u32 reg) 382e2780a68SIngo Molnar { 383e2780a68SIngo Molnar return apic->read(reg); 384e2780a68SIngo Molnar } 385e2780a68SIngo Molnar 386e2780a68SIngo Molnar static inline void apic_write(u32 reg, u32 val) 387e2780a68SIngo Molnar { 388e2780a68SIngo Molnar apic->write(reg, val); 389e2780a68SIngo Molnar } 390e2780a68SIngo Molnar 3912a43195dSMichael S. Tsirkin static inline void apic_eoi(void) 3922a43195dSMichael S. Tsirkin { 3932a43195dSMichael S. Tsirkin apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 3942a43195dSMichael S. Tsirkin } 3952a43195dSMichael S. Tsirkin 396e2780a68SIngo Molnar static inline u64 apic_icr_read(void) 397e2780a68SIngo Molnar { 398e2780a68SIngo Molnar return apic->icr_read(); 399e2780a68SIngo Molnar } 400e2780a68SIngo Molnar 401e2780a68SIngo Molnar static inline void apic_icr_write(u32 low, u32 high) 402e2780a68SIngo Molnar { 403e2780a68SIngo Molnar apic->icr_write(low, high); 404e2780a68SIngo Molnar } 405e2780a68SIngo Molnar 406e2780a68SIngo Molnar static inline void apic_wait_icr_idle(void) 407e2780a68SIngo Molnar { 408e2780a68SIngo Molnar apic->wait_icr_idle(); 409e2780a68SIngo Molnar } 410e2780a68SIngo Molnar 411e2780a68SIngo Molnar static inline u32 safe_apic_wait_icr_idle(void) 412e2780a68SIngo Molnar { 413e2780a68SIngo Molnar return apic->safe_wait_icr_idle(); 414e2780a68SIngo Molnar } 415e2780a68SIngo Molnar 4161551df64SMichael S. Tsirkin extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 4171551df64SMichael S. Tsirkin 418d674cd19SCyrill Gorcunov #else /* CONFIG_X86_LOCAL_APIC */ 419d674cd19SCyrill Gorcunov 420d674cd19SCyrill Gorcunov static inline u32 apic_read(u32 reg) { return 0; } 421d674cd19SCyrill Gorcunov static inline void apic_write(u32 reg, u32 val) { } 4222a43195dSMichael S. Tsirkin static inline void apic_eoi(void) { } 423d674cd19SCyrill Gorcunov static inline u64 apic_icr_read(void) { return 0; } 424d674cd19SCyrill Gorcunov static inline void apic_icr_write(u32 low, u32 high) { } 425d674cd19SCyrill Gorcunov static inline void apic_wait_icr_idle(void) { } 426d674cd19SCyrill Gorcunov static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 4271551df64SMichael S. Tsirkin static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 428d674cd19SCyrill Gorcunov 429d674cd19SCyrill Gorcunov #endif /* CONFIG_X86_LOCAL_APIC */ 430e2780a68SIngo Molnar 431e2780a68SIngo Molnar static inline void ack_APIC_irq(void) 432e2780a68SIngo Molnar { 433e2780a68SIngo Molnar /* 434e2780a68SIngo Molnar * ack_APIC_irq() actually gets compiled as a single instruction 435e2780a68SIngo Molnar * ... yummie. 436e2780a68SIngo Molnar */ 4372a43195dSMichael S. Tsirkin apic_eoi(); 438e2780a68SIngo Molnar } 439e2780a68SIngo Molnar 440e2780a68SIngo Molnar static inline unsigned default_get_apic_id(unsigned long x) 441e2780a68SIngo Molnar { 442e2780a68SIngo Molnar unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 443e2780a68SIngo Molnar 44442937e81SAndreas Herrmann if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 445e2780a68SIngo Molnar return (x >> 24) & 0xFF; 446e2780a68SIngo Molnar else 447e2780a68SIngo Molnar return (x >> 24) & 0x0F; 448e2780a68SIngo Molnar } 449e2780a68SIngo Molnar 450e2780a68SIngo Molnar /* 4516ab1b27cSDavid Rientjes * Warm reset vector position: 452e2780a68SIngo Molnar */ 4536ab1b27cSDavid Rientjes #define TRAMPOLINE_PHYS_LOW 0x467 4546ab1b27cSDavid Rientjes #define TRAMPOLINE_PHYS_HIGH 0x469 455e2780a68SIngo Molnar 4562b6163bfSYinghai Lu #ifdef CONFIG_X86_64 457e2780a68SIngo Molnar extern void apic_send_IPI_self(int vector); 458e2780a68SIngo Molnar 459e2780a68SIngo Molnar DECLARE_PER_CPU(int, x2apic_extra_bits); 460e2780a68SIngo Molnar 461e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 462e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 463e2780a68SIngo Molnar #endif 464e2780a68SIngo Molnar 465838312beSJan Beulich extern void generic_bigsmp_probe(void); 466e2780a68SIngo Molnar 467e2780a68SIngo Molnar 468e2780a68SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 469e2780a68SIngo Molnar 470e2780a68SIngo Molnar #include <asm/smp.h> 471e2780a68SIngo Molnar 472e2780a68SIngo Molnar #define APIC_DFR_VALUE (APIC_DFR_FLAT) 473e2780a68SIngo Molnar 474e2780a68SIngo Molnar static inline const struct cpumask *default_target_cpus(void) 475e2780a68SIngo Molnar { 476e2780a68SIngo Molnar #ifdef CONFIG_SMP 477e2780a68SIngo Molnar return cpu_online_mask; 478e2780a68SIngo Molnar #else 479e2780a68SIngo Molnar return cpumask_of(0); 480e2780a68SIngo Molnar #endif 481e2780a68SIngo Molnar } 482e2780a68SIngo Molnar 483bf721d3aSAlexander Gordeev static inline const struct cpumask *online_target_cpus(void) 484bf721d3aSAlexander Gordeev { 485bf721d3aSAlexander Gordeev return cpu_online_mask; 486bf721d3aSAlexander Gordeev } 487bf721d3aSAlexander Gordeev 4880816b0f0SVlad Zolotarov DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 489e2780a68SIngo Molnar 490e2780a68SIngo Molnar 491e2780a68SIngo Molnar static inline unsigned int read_apic_id(void) 492e2780a68SIngo Molnar { 493e2780a68SIngo Molnar unsigned int reg; 494e2780a68SIngo Molnar 495e2780a68SIngo Molnar reg = apic_read(APIC_ID); 496e2780a68SIngo Molnar 497e2780a68SIngo Molnar return apic->get_apic_id(reg); 498e2780a68SIngo Molnar } 499e2780a68SIngo Molnar 500fa63030eSDaniel J Blueman static inline int default_apic_id_valid(int apicid) 501fa63030eSDaniel J Blueman { 502b7157acfSSteffen Persvold return (apicid < 255); 503fa63030eSDaniel J Blueman } 504fa63030eSDaniel J Blueman 505a491cc90SJiang Liu extern int default_acpi_madt_oem_check(char *, char *); 506a491cc90SJiang Liu 507e2780a68SIngo Molnar extern void default_setup_apic_routing(void); 508e2780a68SIngo Molnar 5099844ab11SCyrill Gorcunov extern struct apic apic_noop; 5109844ab11SCyrill Gorcunov 511e2780a68SIngo Molnar #ifdef CONFIG_X86_32 5122c1b284eSJaswinder Singh Rajput 513acb8bc09STejun Heo static inline int noop_x86_32_early_logical_apicid(int cpu) 514acb8bc09STejun Heo { 515acb8bc09STejun Heo return BAD_APICID; 516acb8bc09STejun Heo } 517acb8bc09STejun Heo 518e2780a68SIngo Molnar /* 519e2780a68SIngo Molnar * Set up the logical destination ID. 520e2780a68SIngo Molnar * 521e2780a68SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 522e2780a68SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 523e2780a68SIngo Molnar * document number 292116). So here it goes... 524e2780a68SIngo Molnar */ 525e2780a68SIngo Molnar extern void default_init_apic_ldr(void); 526e2780a68SIngo Molnar 527e2780a68SIngo Molnar static inline int default_apic_id_registered(void) 528e2780a68SIngo Molnar { 529e2780a68SIngo Molnar return physid_isset(read_apic_id(), phys_cpu_present_map); 530e2780a68SIngo Molnar } 531e2780a68SIngo Molnar 532f56e5034SYinghai Lu static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 533f56e5034SYinghai Lu { 534f56e5034SYinghai Lu return cpuid_apic >> index_msb; 535f56e5034SYinghai Lu } 536f56e5034SYinghai Lu 537f56e5034SYinghai Lu #endif 538f56e5034SYinghai Lu 539ff164324SAlexander Gordeev static inline int 540a5a39156SAlexander Gordeev flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 541a5a39156SAlexander Gordeev const struct cpumask *andmask, 542a5a39156SAlexander Gordeev unsigned int *apicid) 543e2780a68SIngo Molnar { 544a5a39156SAlexander Gordeev unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 545a5a39156SAlexander Gordeev cpumask_bits(andmask)[0] & 546a5a39156SAlexander Gordeev cpumask_bits(cpu_online_mask)[0] & 547a5a39156SAlexander Gordeev APIC_ALL_CPUS; 548a5a39156SAlexander Gordeev 549ff164324SAlexander Gordeev if (likely(cpu_mask)) { 550ff164324SAlexander Gordeev *apicid = (unsigned int)cpu_mask; 551ff164324SAlexander Gordeev return 0; 552ff164324SAlexander Gordeev } else { 553ff164324SAlexander Gordeev return -EINVAL; 554ff164324SAlexander Gordeev } 555e2780a68SIngo Molnar } 556e2780a68SIngo Molnar 557ff164324SAlexander Gordeev extern int 5586398268dSAlexander Gordeev default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 559ff164324SAlexander Gordeev const struct cpumask *andmask, 560ff164324SAlexander Gordeev unsigned int *apicid); 5616398268dSAlexander Gordeev 562b39f25a8SSuresh Siddha static inline void 5631ac322d0SSuresh Siddha flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 5641ac322d0SSuresh Siddha const struct cpumask *mask) 5659d8e1066SAlexander Gordeev { 5669d8e1066SAlexander Gordeev /* Careful. Some cpus do not strictly honor the set of cpus 5679d8e1066SAlexander Gordeev * specified in the interrupt destination when using lowest 5689d8e1066SAlexander Gordeev * priority interrupt delivery mode. 5699d8e1066SAlexander Gordeev * 5709d8e1066SAlexander Gordeev * In particular there was a hyperthreading cpu observed to 5719d8e1066SAlexander Gordeev * deliver interrupts to the wrong hyperthread when only one 5729d8e1066SAlexander Gordeev * hyperthread was specified in the interrupt desitination. 5739d8e1066SAlexander Gordeev */ 5749d8e1066SAlexander Gordeev cpumask_clear(retmask); 5759d8e1066SAlexander Gordeev cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 5769d8e1066SAlexander Gordeev } 5779d8e1066SAlexander Gordeev 578b39f25a8SSuresh Siddha static inline void 5791ac322d0SSuresh Siddha default_vector_allocation_domain(int cpu, struct cpumask *retmask, 5801ac322d0SSuresh Siddha const struct cpumask *mask) 5819d8e1066SAlexander Gordeev { 5829d8e1066SAlexander Gordeev cpumask_copy(retmask, cpumask_of(cpu)); 5839d8e1066SAlexander Gordeev } 5849d8e1066SAlexander Gordeev 5857abc0753SCyrill Gorcunov static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 586e2780a68SIngo Molnar { 5877abc0753SCyrill Gorcunov return physid_isset(apicid, *map); 588e2780a68SIngo Molnar } 589e2780a68SIngo Molnar 5907abc0753SCyrill Gorcunov static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 591e2780a68SIngo Molnar { 5927abc0753SCyrill Gorcunov *retmap = *phys_map; 593e2780a68SIngo Molnar } 594e2780a68SIngo Molnar 595e2780a68SIngo Molnar static inline int __default_cpu_present_to_apicid(int mps_cpu) 596e2780a68SIngo Molnar { 597e2780a68SIngo Molnar if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 598e2780a68SIngo Molnar return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 599e2780a68SIngo Molnar else 600e2780a68SIngo Molnar return BAD_APICID; 601e2780a68SIngo Molnar } 602e2780a68SIngo Molnar 603e2780a68SIngo Molnar static inline int 604e11dadabSThomas Gleixner __default_check_phys_apicid_present(int phys_apicid) 605e2780a68SIngo Molnar { 606e11dadabSThomas Gleixner return physid_isset(phys_apicid, phys_cpu_present_map); 607e2780a68SIngo Molnar } 608e2780a68SIngo Molnar 609e2780a68SIngo Molnar #ifdef CONFIG_X86_32 610e2780a68SIngo Molnar static inline int default_cpu_present_to_apicid(int mps_cpu) 611e2780a68SIngo Molnar { 612e2780a68SIngo Molnar return __default_cpu_present_to_apicid(mps_cpu); 613e2780a68SIngo Molnar } 614e2780a68SIngo Molnar 615e2780a68SIngo Molnar static inline int 616e11dadabSThomas Gleixner default_check_phys_apicid_present(int phys_apicid) 617e2780a68SIngo Molnar { 618e11dadabSThomas Gleixner return __default_check_phys_apicid_present(phys_apicid); 619e2780a68SIngo Molnar } 620e2780a68SIngo Molnar #else 621e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 622e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 623e2780a68SIngo Molnar #endif 624e2780a68SIngo Molnar 625e2780a68SIngo Molnar #endif /* CONFIG_X86_LOCAL_APIC */ 626eddc0e92SSeiji Aguchi extern void irq_enter(void); 627eddc0e92SSeiji Aguchi extern void irq_exit(void); 628eddc0e92SSeiji Aguchi 629eddc0e92SSeiji Aguchi static inline void entering_irq(void) 630eddc0e92SSeiji Aguchi { 631eddc0e92SSeiji Aguchi irq_enter(); 632eddc0e92SSeiji Aguchi exit_idle(); 633eddc0e92SSeiji Aguchi } 634eddc0e92SSeiji Aguchi 635eddc0e92SSeiji Aguchi static inline void entering_ack_irq(void) 636eddc0e92SSeiji Aguchi { 637eddc0e92SSeiji Aguchi ack_APIC_irq(); 638eddc0e92SSeiji Aguchi entering_irq(); 639eddc0e92SSeiji Aguchi } 640eddc0e92SSeiji Aguchi 641eddc0e92SSeiji Aguchi static inline void exiting_irq(void) 642eddc0e92SSeiji Aguchi { 643eddc0e92SSeiji Aguchi irq_exit(); 644eddc0e92SSeiji Aguchi } 645eddc0e92SSeiji Aguchi 646eddc0e92SSeiji Aguchi static inline void exiting_ack_irq(void) 647eddc0e92SSeiji Aguchi { 648eddc0e92SSeiji Aguchi irq_exit(); 649eddc0e92SSeiji Aguchi /* Ack only at the end to avoid potential reentry */ 650eddc0e92SSeiji Aguchi ack_APIC_irq(); 651eddc0e92SSeiji Aguchi } 652e2780a68SIngo Molnar 65317405453SYoshihiro YUNOMAE extern void ioapic_zap_locks(void); 65417405453SYoshihiro YUNOMAE 6551965aae3SH. Peter Anvin #endif /* _ASM_X86_APIC_H */ 656