11965aae3SH. Peter Anvin #ifndef _ASM_X86_APIC_H 21965aae3SH. Peter Anvin #define _ASM_X86_APIC_H 3bb898558SAl Viro 4e2780a68SIngo Molnar #include <linux/cpumask.h> 5bb898558SAl Viro 6bb898558SAl Viro #include <asm/alternative.h> 7bb898558SAl Viro #include <asm/cpufeature.h> 8e2780a68SIngo Molnar #include <asm/apicdef.h> 960063497SArun Sharma #include <linux/atomic.h> 10e2780a68SIngo Molnar #include <asm/fixmap.h> 11e2780a68SIngo Molnar #include <asm/mpspec.h> 12bb898558SAl Viro #include <asm/msr.h> 13bb898558SAl Viro 14bb898558SAl Viro #define ARCH_APICTIMER_STOPS_ON_C3 1 15bb898558SAl Viro 16bb898558SAl Viro /* 17bb898558SAl Viro * Debugging macros 18bb898558SAl Viro */ 19bb898558SAl Viro #define APIC_QUIET 0 20bb898558SAl Viro #define APIC_VERBOSE 1 21bb898558SAl Viro #define APIC_DEBUG 2 22bb898558SAl Viro 23b7c4948eSHidehiro Kawai /* Macros for apic_extnmi which controls external NMI masking */ 24b7c4948eSHidehiro Kawai #define APIC_EXTNMI_BSP 0 /* Default */ 25b7c4948eSHidehiro Kawai #define APIC_EXTNMI_ALL 1 26b7c4948eSHidehiro Kawai #define APIC_EXTNMI_NONE 2 27b7c4948eSHidehiro Kawai 28bb898558SAl Viro /* 29bb898558SAl Viro * Define the default level of output to be very little 30bb898558SAl Viro * This can be turned up by using apic=verbose for more 31bb898558SAl Viro * information and apic=debug for _lots_ of information. 32bb898558SAl Viro * apic_verbosity is defined in apic.c 33bb898558SAl Viro */ 34bb898558SAl Viro #define apic_printk(v, s, a...) do { \ 35bb898558SAl Viro if ((v) <= apic_verbosity) \ 36bb898558SAl Viro printk(s, ##a); \ 37bb898558SAl Viro } while (0) 38bb898558SAl Viro 39bb898558SAl Viro 40160d8dacSIngo Molnar #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 41bb898558SAl Viro extern void generic_apic_probe(void); 42160d8dacSIngo Molnar #else 43160d8dacSIngo Molnar static inline void generic_apic_probe(void) 44160d8dacSIngo Molnar { 45160d8dacSIngo Molnar } 46160d8dacSIngo Molnar #endif 47bb898558SAl Viro 48bb898558SAl Viro #ifdef CONFIG_X86_LOCAL_APIC 49bb898558SAl Viro 50bb898558SAl Viro extern unsigned int apic_verbosity; 51bb898558SAl Viro extern int local_apic_timer_c2_ok; 52bb898558SAl Viro 53bb898558SAl Viro extern int disable_apic; 541ade93efSJacob Pan extern unsigned int lapic_timer_frequency; 550939e4fdSIngo Molnar 564f45ed9fSDou Liyang extern enum apic_intr_mode_id apic_intr_mode; 574f45ed9fSDou Liyang enum apic_intr_mode_id { 584f45ed9fSDou Liyang APIC_PIC, 594f45ed9fSDou Liyang APIC_VIRTUAL_WIRE, 604f45ed9fSDou Liyang APIC_VIRTUAL_WIRE_NO_CONFIG, 614f45ed9fSDou Liyang APIC_SYMMETRIC_IO, 624f45ed9fSDou Liyang APIC_SYMMETRIC_IO_NO_ROUTING 634f45ed9fSDou Liyang }; 644f45ed9fSDou Liyang 650939e4fdSIngo Molnar #ifdef CONFIG_SMP 660939e4fdSIngo Molnar extern void __inquire_remote_apic(int apicid); 670939e4fdSIngo Molnar #else /* CONFIG_SMP */ 680939e4fdSIngo Molnar static inline void __inquire_remote_apic(int apicid) 690939e4fdSIngo Molnar { 700939e4fdSIngo Molnar } 710939e4fdSIngo Molnar #endif /* CONFIG_SMP */ 720939e4fdSIngo Molnar 730939e4fdSIngo Molnar static inline void default_inquire_remote_apic(int apicid) 740939e4fdSIngo Molnar { 750939e4fdSIngo Molnar if (apic_verbosity >= APIC_DEBUG) 760939e4fdSIngo Molnar __inquire_remote_apic(apicid); 770939e4fdSIngo Molnar } 780939e4fdSIngo Molnar 79bb898558SAl Viro /* 808312136fSCyrill Gorcunov * With 82489DX we can't rely on apic feature bit 818312136fSCyrill Gorcunov * retrieved via cpuid but still have to deal with 828312136fSCyrill Gorcunov * such an apic chip so we assume that SMP configuration 838312136fSCyrill Gorcunov * is found from MP table (64bit case uses ACPI mostly 848312136fSCyrill Gorcunov * which set smp presence flag as well so we are safe 858312136fSCyrill Gorcunov * to use this helper too). 868312136fSCyrill Gorcunov */ 878312136fSCyrill Gorcunov static inline bool apic_from_smp_config(void) 888312136fSCyrill Gorcunov { 898312136fSCyrill Gorcunov return smp_found_config && !disable_apic; 908312136fSCyrill Gorcunov } 918312136fSCyrill Gorcunov 928312136fSCyrill Gorcunov /* 93bb898558SAl Viro * Basic functions accessing APICs. 94bb898558SAl Viro */ 95bb898558SAl Viro #ifdef CONFIG_PARAVIRT 96bb898558SAl Viro #include <asm/paravirt.h> 97bb898558SAl Viro #endif 98bb898558SAl Viro 99bb898558SAl Viro extern int setup_profiling_timer(unsigned int); 100bb898558SAl Viro 101bb898558SAl Viro static inline void native_apic_mem_write(u32 reg, u32 v) 102bb898558SAl Viro { 103bb898558SAl Viro volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104bb898558SAl Viro 105a930dc45SBorislav Petkov alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 106bb898558SAl Viro ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107bb898558SAl Viro ASM_OUTPUT2("0" (v), "m" (*addr))); 108bb898558SAl Viro } 109bb898558SAl Viro 110bb898558SAl Viro static inline u32 native_apic_mem_read(u32 reg) 111bb898558SAl Viro { 112bb898558SAl Viro return *((volatile u32 *)(APIC_BASE + reg)); 113bb898558SAl Viro } 114bb898558SAl Viro 115c1eeb2deSYinghai Lu extern void native_apic_wait_icr_idle(void); 116c1eeb2deSYinghai Lu extern u32 native_safe_apic_wait_icr_idle(void); 117c1eeb2deSYinghai Lu extern void native_apic_icr_write(u32 low, u32 id); 118c1eeb2deSYinghai Lu extern u64 native_apic_icr_read(void); 119c1eeb2deSYinghai Lu 1208d806960SThomas Gleixner static inline bool apic_is_x2apic_enabled(void) 1218d806960SThomas Gleixner { 1228d806960SThomas Gleixner u64 msr; 1238d806960SThomas Gleixner 1248d806960SThomas Gleixner if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 1258d806960SThomas Gleixner return false; 1268d806960SThomas Gleixner return msr & X2APIC_ENABLE; 1278d806960SThomas Gleixner } 1288d806960SThomas Gleixner 129e02ae387SPaolo Bonzini extern void enable_IR_x2apic(void); 130e02ae387SPaolo Bonzini 131e02ae387SPaolo Bonzini extern int get_physical_broadcast(void); 132e02ae387SPaolo Bonzini 133e02ae387SPaolo Bonzini extern int lapic_get_maxlvt(void); 134e02ae387SPaolo Bonzini extern void clear_local_APIC(void); 135e02ae387SPaolo Bonzini extern void disconnect_bsp_APIC(int virt_wire_setup); 136e02ae387SPaolo Bonzini extern void disable_local_APIC(void); 137e02ae387SPaolo Bonzini extern void lapic_shutdown(void); 138e02ae387SPaolo Bonzini extern void sync_Arb_IDs(void); 139e02ae387SPaolo Bonzini extern void init_bsp_APIC(void); 1404b1669e8SDou Liyang extern void apic_intr_mode_init(void); 141e02ae387SPaolo Bonzini extern void setup_local_APIC(void); 142e02ae387SPaolo Bonzini extern void init_apic_mappings(void); 143e02ae387SPaolo Bonzini void register_lapic_address(unsigned long address); 144e02ae387SPaolo Bonzini extern void setup_boot_APIC_clock(void); 145e02ae387SPaolo Bonzini extern void setup_secondary_APIC_clock(void); 1466731b0d6SNicolai Stange extern void lapic_update_tsc_freq(void); 147e02ae387SPaolo Bonzini extern int APIC_init_uniprocessor(void); 148e02ae387SPaolo Bonzini 149e02ae387SPaolo Bonzini #ifdef CONFIG_X86_64 150e02ae387SPaolo Bonzini static inline int apic_force_enable(unsigned long addr) 151e02ae387SPaolo Bonzini { 152e02ae387SPaolo Bonzini return -1; 153e02ae387SPaolo Bonzini } 154e02ae387SPaolo Bonzini #else 155e02ae387SPaolo Bonzini extern int apic_force_enable(unsigned long addr); 156e02ae387SPaolo Bonzini #endif 157e02ae387SPaolo Bonzini 1584b1244b4SDou Liyang extern void apic_bsp_setup(bool upmode); 159e02ae387SPaolo Bonzini extern void apic_ap_setup(void); 160e02ae387SPaolo Bonzini 161e02ae387SPaolo Bonzini /* 162e02ae387SPaolo Bonzini * On 32bit this is mach-xxx local 163e02ae387SPaolo Bonzini */ 164e02ae387SPaolo Bonzini #ifdef CONFIG_X86_64 165e02ae387SPaolo Bonzini extern int apic_is_clustered_box(void); 166e02ae387SPaolo Bonzini #else 167e02ae387SPaolo Bonzini static inline int apic_is_clustered_box(void) 168e02ae387SPaolo Bonzini { 169e02ae387SPaolo Bonzini return 0; 170e02ae387SPaolo Bonzini } 171e02ae387SPaolo Bonzini #endif 172e02ae387SPaolo Bonzini 173e02ae387SPaolo Bonzini extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 174e02ae387SPaolo Bonzini 175e02ae387SPaolo Bonzini #else /* !CONFIG_X86_LOCAL_APIC */ 176e02ae387SPaolo Bonzini static inline void lapic_shutdown(void) { } 177e02ae387SPaolo Bonzini #define local_apic_timer_c2_ok 1 178e02ae387SPaolo Bonzini static inline void init_apic_mappings(void) { } 179e02ae387SPaolo Bonzini static inline void disable_local_APIC(void) { } 180e02ae387SPaolo Bonzini # define setup_boot_APIC_clock x86_init_noop 181e02ae387SPaolo Bonzini # define setup_secondary_APIC_clock x86_init_noop 1826731b0d6SNicolai Stange static inline void lapic_update_tsc_freq(void) { } 1834b1669e8SDou Liyang static inline void apic_intr_mode_init(void) { } 184e02ae387SPaolo Bonzini #endif /* !CONFIG_X86_LOCAL_APIC */ 185e02ae387SPaolo Bonzini 186d0b03bd1SHan, Weidong #ifdef CONFIG_X86_X2APIC 187ce4e240cSSuresh Siddha /* 188ce4e240cSSuresh Siddha * Make previous memory operations globally visible before 189ce4e240cSSuresh Siddha * sending the IPI through x2apic wrmsr. We need a serializing instruction or 190ce4e240cSSuresh Siddha * mfence for this. 191ce4e240cSSuresh Siddha */ 192ce4e240cSSuresh Siddha static inline void x2apic_wrmsr_fence(void) 193ce4e240cSSuresh Siddha { 194ce4e240cSSuresh Siddha asm volatile("mfence" : : : "memory"); 195ce4e240cSSuresh Siddha } 196ce4e240cSSuresh Siddha 197bb898558SAl Viro static inline void native_apic_msr_write(u32 reg, u32 v) 198bb898558SAl Viro { 199bb898558SAl Viro if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 200bb898558SAl Viro reg == APIC_LVR) 201bb898558SAl Viro return; 202bb898558SAl Viro 203bb898558SAl Viro wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 204bb898558SAl Viro } 205bb898558SAl Viro 2060ab711aeSMichael S. Tsirkin static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 2070ab711aeSMichael S. Tsirkin { 208a585df8eSBorislav Petkov __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 2090ab711aeSMichael S. Tsirkin } 2100ab711aeSMichael S. Tsirkin 211bb898558SAl Viro static inline u32 native_apic_msr_read(u32 reg) 212bb898558SAl Viro { 2130059b243SAndi Kleen u64 msr; 214bb898558SAl Viro 215bb898558SAl Viro if (reg == APIC_DFR) 216bb898558SAl Viro return -1; 217bb898558SAl Viro 2180059b243SAndi Kleen rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 2190059b243SAndi Kleen return (u32)msr; 220bb898558SAl Viro } 221bb898558SAl Viro 222c1eeb2deSYinghai Lu static inline void native_x2apic_wait_icr_idle(void) 223c1eeb2deSYinghai Lu { 224c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 225c1eeb2deSYinghai Lu return; 226c1eeb2deSYinghai Lu } 227c1eeb2deSYinghai Lu 228c1eeb2deSYinghai Lu static inline u32 native_safe_x2apic_wait_icr_idle(void) 229c1eeb2deSYinghai Lu { 230c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 231c1eeb2deSYinghai Lu return 0; 232c1eeb2deSYinghai Lu } 233c1eeb2deSYinghai Lu 234c1eeb2deSYinghai Lu static inline void native_x2apic_icr_write(u32 low, u32 id) 235c1eeb2deSYinghai Lu { 236c1eeb2deSYinghai Lu wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 237c1eeb2deSYinghai Lu } 238c1eeb2deSYinghai Lu 239c1eeb2deSYinghai Lu static inline u64 native_x2apic_icr_read(void) 240c1eeb2deSYinghai Lu { 241c1eeb2deSYinghai Lu unsigned long val; 242c1eeb2deSYinghai Lu 243c1eeb2deSYinghai Lu rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 244c1eeb2deSYinghai Lu return val; 245c1eeb2deSYinghai Lu } 246c1eeb2deSYinghai Lu 24781a46dd8SThomas Gleixner extern int x2apic_mode; 248fc1edaf9SSuresh Siddha extern int x2apic_phys; 249d524165cSThomas Gleixner extern void __init check_x2apic(void); 250659006bfSThomas Gleixner extern void x2apic_setup(void); 251bb898558SAl Viro static inline int x2apic_enabled(void) 252bb898558SAl Viro { 25362436a4dSBorislav Petkov return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 254bb898558SAl Viro } 255fc1edaf9SSuresh Siddha 25662436a4dSBorislav Petkov #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 257e02ae387SPaolo Bonzini #else /* !CONFIG_X86_X2APIC */ 25855eae7deSThomas Gleixner static inline void check_x2apic(void) { } 259659006bfSThomas Gleixner static inline void x2apic_setup(void) { } 26055eae7deSThomas Gleixner static inline int x2apic_enabled(void) { return 0; } 261cf6567feSSuresh Siddha 26281a46dd8SThomas Gleixner #define x2apic_mode (0) 26381a46dd8SThomas Gleixner #define x2apic_supported() (0) 264e02ae387SPaolo Bonzini #endif /* !CONFIG_X86_X2APIC */ 265bb898558SAl Viro 2660e24f7c9SThomas Gleixner struct irq_data; 2670e24f7c9SThomas Gleixner 268e2780a68SIngo Molnar /* 269e2780a68SIngo Molnar * Copyright 2004 James Cleverdon, IBM. 270e2780a68SIngo Molnar * Subject to the GNU Public License, v.2 271e2780a68SIngo Molnar * 272e2780a68SIngo Molnar * Generic APIC sub-arch data struct. 273e2780a68SIngo Molnar * 274e2780a68SIngo Molnar * Hacked for x86-64 by James Cleverdon from i386 architecture code by 275e2780a68SIngo Molnar * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 276e2780a68SIngo Molnar * James Cleverdon. 277e2780a68SIngo Molnar */ 278be163a15SIngo Molnar struct apic { 279e2780a68SIngo Molnar char *name; 280e2780a68SIngo Molnar 281e2780a68SIngo Molnar int (*probe)(void); 282e2780a68SIngo Molnar int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 283fa63030eSDaniel J Blueman int (*apic_id_valid)(int apicid); 284e2780a68SIngo Molnar int (*apic_id_registered)(void); 285e2780a68SIngo Molnar 286e2780a68SIngo Molnar u32 irq_delivery_mode; 287e2780a68SIngo Molnar u32 irq_dest_mode; 288e2780a68SIngo Molnar 289e2780a68SIngo Molnar const struct cpumask *(*target_cpus)(void); 290e2780a68SIngo Molnar 291e2780a68SIngo Molnar int disable_esr; 292e2780a68SIngo Molnar 293e2780a68SIngo Molnar int dest_logical; 2947abc0753SCyrill Gorcunov unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 295e2780a68SIngo Molnar 2961ac322d0SSuresh Siddha void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 2971ac322d0SSuresh Siddha const struct cpumask *mask); 298e2780a68SIngo Molnar void (*init_apic_ldr)(void); 299e2780a68SIngo Molnar 3007abc0753SCyrill Gorcunov void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 301e2780a68SIngo Molnar 302e2780a68SIngo Molnar void (*setup_apic_routing)(void); 303e2780a68SIngo Molnar int (*cpu_present_to_apicid)(int mps_cpu); 3047abc0753SCyrill Gorcunov void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 305e11dadabSThomas Gleixner int (*check_phys_apicid_present)(int phys_apicid); 306e2780a68SIngo Molnar int (*phys_pkg_id)(int cpuid_apic, int index_msb); 307e2780a68SIngo Molnar 308e2780a68SIngo Molnar unsigned int (*get_apic_id)(unsigned long x); 3095d64d209SDou Liyang /* Can't be NULL on 64-bit */ 310e2780a68SIngo Molnar unsigned long (*set_apic_id)(unsigned int id); 311e2780a68SIngo Molnar 31291cd9cb7SThomas Gleixner int (*cpu_mask_to_apicid)(const struct cpumask *cpumask, 3130e24f7c9SThomas Gleixner struct irq_data *irqdata, 314ff164324SAlexander Gordeev unsigned int *apicid); 315e2780a68SIngo Molnar 316e2780a68SIngo Molnar /* ipi */ 317539da787SLinus Torvalds void (*send_IPI)(int cpu, int vector); 318e2780a68SIngo Molnar void (*send_IPI_mask)(const struct cpumask *mask, int vector); 319e2780a68SIngo Molnar void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 320e2780a68SIngo Molnar int vector); 321e2780a68SIngo Molnar void (*send_IPI_allbutself)(int vector); 322e2780a68SIngo Molnar void (*send_IPI_all)(int vector); 323e2780a68SIngo Molnar void (*send_IPI_self)(int vector); 324e2780a68SIngo Molnar 325e2780a68SIngo Molnar /* wakeup_secondary_cpu */ 3261f5bcabfSIngo Molnar int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 327e2780a68SIngo Molnar 328e2780a68SIngo Molnar void (*inquire_remote_apic)(int apicid); 329e2780a68SIngo Molnar 330e2780a68SIngo Molnar /* apic ops */ 331e2780a68SIngo Molnar u32 (*read)(u32 reg); 332e2780a68SIngo Molnar void (*write)(u32 reg, u32 v); 3332a43195dSMichael S. Tsirkin /* 3342a43195dSMichael S. Tsirkin * ->eoi_write() has the same signature as ->write(). 3352a43195dSMichael S. Tsirkin * 3362a43195dSMichael S. Tsirkin * Drivers can support both ->eoi_write() and ->write() by passing the same 3372a43195dSMichael S. Tsirkin * callback value. Kernel can override ->eoi_write() and fall back 3382a43195dSMichael S. Tsirkin * on write for EOI. 3392a43195dSMichael S. Tsirkin */ 3402a43195dSMichael S. Tsirkin void (*eoi_write)(u32 reg, u32 v); 3418ca22552SWanpeng Li void (*native_eoi_write)(u32 reg, u32 v); 342e2780a68SIngo Molnar u64 (*icr_read)(void); 343e2780a68SIngo Molnar void (*icr_write)(u32 low, u32 high); 344e2780a68SIngo Molnar void (*wait_icr_idle)(void); 345e2780a68SIngo Molnar u32 (*safe_wait_icr_idle)(void); 346acb8bc09STejun Heo 347acb8bc09STejun Heo #ifdef CONFIG_X86_32 348acb8bc09STejun Heo /* 349acb8bc09STejun Heo * Called very early during boot from get_smp_config(). It should 350acb8bc09STejun Heo * return the logical apicid. x86_[bios]_cpu_to_apicid is 351acb8bc09STejun Heo * initialized before this function is called. 352acb8bc09STejun Heo * 353acb8bc09STejun Heo * If logical apicid can't be determined that early, the function 354acb8bc09STejun Heo * may return BAD_APICID. Logical apicid will be configured after 355acb8bc09STejun Heo * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 356acb8bc09STejun Heo * won't be applied properly during early boot in this case. 357acb8bc09STejun Heo */ 358acb8bc09STejun Heo int (*x86_32_early_logical_apicid)(int cpu); 359acb8bc09STejun Heo #endif 360e2780a68SIngo Molnar }; 361e2780a68SIngo Molnar 3620917c01fSIngo Molnar /* 3630917c01fSIngo Molnar * Pointer to the local APIC driver in use on this system (there's 3640917c01fSIngo Molnar * always just one such driver in use - the kernel decides via an 3650917c01fSIngo Molnar * early probing process which one it picks - and then sticks to it): 3660917c01fSIngo Molnar */ 367be163a15SIngo Molnar extern struct apic *apic; 3680917c01fSIngo Molnar 3690917c01fSIngo Molnar /* 370107e0e0cSSuresh Siddha * APIC drivers are probed based on how they are listed in the .apicdrivers 371107e0e0cSSuresh Siddha * section. So the order is important and enforced by the ordering 372107e0e0cSSuresh Siddha * of different apic driver files in the Makefile. 373107e0e0cSSuresh Siddha * 374107e0e0cSSuresh Siddha * For the files having two apic drivers, we use apic_drivers() 375107e0e0cSSuresh Siddha * to enforce the order with in them. 376107e0e0cSSuresh Siddha */ 377107e0e0cSSuresh Siddha #define apic_driver(sym) \ 37875fdd155SAndi Kleen static const struct apic *__apicdrivers_##sym __used \ 379107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 380107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym } 381107e0e0cSSuresh Siddha 382107e0e0cSSuresh Siddha #define apic_drivers(sym1, sym2) \ 383107e0e0cSSuresh Siddha static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 384107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 385107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym1, &sym2 } 386107e0e0cSSuresh Siddha 387107e0e0cSSuresh Siddha extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 388107e0e0cSSuresh Siddha 389107e0e0cSSuresh Siddha /* 3900917c01fSIngo Molnar * APIC functionality to boot other CPUs - only used on SMP: 3910917c01fSIngo Molnar */ 3920917c01fSIngo Molnar #ifdef CONFIG_SMP 3932b6163bfSYinghai Lu extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 3940917c01fSIngo Molnar #endif 395e2780a68SIngo Molnar 396d674cd19SCyrill Gorcunov #ifdef CONFIG_X86_LOCAL_APIC 397346b46beSFernando Luis Vázquez Cao 398e2780a68SIngo Molnar static inline u32 apic_read(u32 reg) 399e2780a68SIngo Molnar { 400e2780a68SIngo Molnar return apic->read(reg); 401e2780a68SIngo Molnar } 402e2780a68SIngo Molnar 403e2780a68SIngo Molnar static inline void apic_write(u32 reg, u32 val) 404e2780a68SIngo Molnar { 405e2780a68SIngo Molnar apic->write(reg, val); 406e2780a68SIngo Molnar } 407e2780a68SIngo Molnar 4082a43195dSMichael S. Tsirkin static inline void apic_eoi(void) 4092a43195dSMichael S. Tsirkin { 4102a43195dSMichael S. Tsirkin apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 4112a43195dSMichael S. Tsirkin } 4122a43195dSMichael S. Tsirkin 413e2780a68SIngo Molnar static inline u64 apic_icr_read(void) 414e2780a68SIngo Molnar { 415e2780a68SIngo Molnar return apic->icr_read(); 416e2780a68SIngo Molnar } 417e2780a68SIngo Molnar 418e2780a68SIngo Molnar static inline void apic_icr_write(u32 low, u32 high) 419e2780a68SIngo Molnar { 420e2780a68SIngo Molnar apic->icr_write(low, high); 421e2780a68SIngo Molnar } 422e2780a68SIngo Molnar 423e2780a68SIngo Molnar static inline void apic_wait_icr_idle(void) 424e2780a68SIngo Molnar { 425e2780a68SIngo Molnar apic->wait_icr_idle(); 426e2780a68SIngo Molnar } 427e2780a68SIngo Molnar 428e2780a68SIngo Molnar static inline u32 safe_apic_wait_icr_idle(void) 429e2780a68SIngo Molnar { 430e2780a68SIngo Molnar return apic->safe_wait_icr_idle(); 431e2780a68SIngo Molnar } 432e2780a68SIngo Molnar 4331551df64SMichael S. Tsirkin extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 4341551df64SMichael S. Tsirkin 435d674cd19SCyrill Gorcunov #else /* CONFIG_X86_LOCAL_APIC */ 436d674cd19SCyrill Gorcunov 437d674cd19SCyrill Gorcunov static inline u32 apic_read(u32 reg) { return 0; } 438d674cd19SCyrill Gorcunov static inline void apic_write(u32 reg, u32 val) { } 4392a43195dSMichael S. Tsirkin static inline void apic_eoi(void) { } 440d674cd19SCyrill Gorcunov static inline u64 apic_icr_read(void) { return 0; } 441d674cd19SCyrill Gorcunov static inline void apic_icr_write(u32 low, u32 high) { } 442d674cd19SCyrill Gorcunov static inline void apic_wait_icr_idle(void) { } 443d674cd19SCyrill Gorcunov static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 4441551df64SMichael S. Tsirkin static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 445d674cd19SCyrill Gorcunov 446d674cd19SCyrill Gorcunov #endif /* CONFIG_X86_LOCAL_APIC */ 447e2780a68SIngo Molnar 448e2780a68SIngo Molnar static inline void ack_APIC_irq(void) 449e2780a68SIngo Molnar { 450e2780a68SIngo Molnar /* 451e2780a68SIngo Molnar * ack_APIC_irq() actually gets compiled as a single instruction 452e2780a68SIngo Molnar * ... yummie. 453e2780a68SIngo Molnar */ 4542a43195dSMichael S. Tsirkin apic_eoi(); 455e2780a68SIngo Molnar } 456e2780a68SIngo Molnar 457e2780a68SIngo Molnar static inline unsigned default_get_apic_id(unsigned long x) 458e2780a68SIngo Molnar { 459e2780a68SIngo Molnar unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 460e2780a68SIngo Molnar 46142937e81SAndreas Herrmann if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 462e2780a68SIngo Molnar return (x >> 24) & 0xFF; 463e2780a68SIngo Molnar else 464e2780a68SIngo Molnar return (x >> 24) & 0x0F; 465e2780a68SIngo Molnar } 466e2780a68SIngo Molnar 467e2780a68SIngo Molnar /* 4686ab1b27cSDavid Rientjes * Warm reset vector position: 469e2780a68SIngo Molnar */ 4706ab1b27cSDavid Rientjes #define TRAMPOLINE_PHYS_LOW 0x467 4716ab1b27cSDavid Rientjes #define TRAMPOLINE_PHYS_HIGH 0x469 472e2780a68SIngo Molnar 4732b6163bfSYinghai Lu #ifdef CONFIG_X86_64 474e2780a68SIngo Molnar extern void apic_send_IPI_self(int vector); 475e2780a68SIngo Molnar 476e2780a68SIngo Molnar DECLARE_PER_CPU(int, x2apic_extra_bits); 477e2780a68SIngo Molnar 478e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 479e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 480e2780a68SIngo Molnar #endif 481e2780a68SIngo Molnar 482838312beSJan Beulich extern void generic_bigsmp_probe(void); 483e2780a68SIngo Molnar 484e2780a68SIngo Molnar 485e2780a68SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 486e2780a68SIngo Molnar 487e2780a68SIngo Molnar #include <asm/smp.h> 488e2780a68SIngo Molnar 489e2780a68SIngo Molnar #define APIC_DFR_VALUE (APIC_DFR_FLAT) 490e2780a68SIngo Molnar 491e2780a68SIngo Molnar static inline const struct cpumask *default_target_cpus(void) 492e2780a68SIngo Molnar { 493e2780a68SIngo Molnar #ifdef CONFIG_SMP 494e2780a68SIngo Molnar return cpu_online_mask; 495e2780a68SIngo Molnar #else 496e2780a68SIngo Molnar return cpumask_of(0); 497e2780a68SIngo Molnar #endif 498e2780a68SIngo Molnar } 499e2780a68SIngo Molnar 500bf721d3aSAlexander Gordeev static inline const struct cpumask *online_target_cpus(void) 501bf721d3aSAlexander Gordeev { 502bf721d3aSAlexander Gordeev return cpu_online_mask; 503bf721d3aSAlexander Gordeev } 504bf721d3aSAlexander Gordeev 5050816b0f0SVlad Zolotarov DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 506e2780a68SIngo Molnar 507e2780a68SIngo Molnar 508e2780a68SIngo Molnar static inline unsigned int read_apic_id(void) 509e2780a68SIngo Molnar { 510e2780a68SIngo Molnar unsigned int reg; 511e2780a68SIngo Molnar 512e2780a68SIngo Molnar reg = apic_read(APIC_ID); 513e2780a68SIngo Molnar 514e2780a68SIngo Molnar return apic->get_apic_id(reg); 515e2780a68SIngo Molnar } 516e2780a68SIngo Molnar 517fa63030eSDaniel J Blueman static inline int default_apic_id_valid(int apicid) 518fa63030eSDaniel J Blueman { 519b7157acfSSteffen Persvold return (apicid < 255); 520fa63030eSDaniel J Blueman } 521fa63030eSDaniel J Blueman 522a491cc90SJiang Liu extern int default_acpi_madt_oem_check(char *, char *); 523a491cc90SJiang Liu 524e2780a68SIngo Molnar extern void default_setup_apic_routing(void); 525e2780a68SIngo Molnar 5269844ab11SCyrill Gorcunov extern struct apic apic_noop; 5279844ab11SCyrill Gorcunov 528e2780a68SIngo Molnar #ifdef CONFIG_X86_32 5292c1b284eSJaswinder Singh Rajput 530acb8bc09STejun Heo static inline int noop_x86_32_early_logical_apicid(int cpu) 531acb8bc09STejun Heo { 532acb8bc09STejun Heo return BAD_APICID; 533acb8bc09STejun Heo } 534acb8bc09STejun Heo 535e2780a68SIngo Molnar /* 536e2780a68SIngo Molnar * Set up the logical destination ID. 537e2780a68SIngo Molnar * 538e2780a68SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 539e2780a68SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 540e2780a68SIngo Molnar * document number 292116). So here it goes... 541e2780a68SIngo Molnar */ 542e2780a68SIngo Molnar extern void default_init_apic_ldr(void); 543e2780a68SIngo Molnar 544e2780a68SIngo Molnar static inline int default_apic_id_registered(void) 545e2780a68SIngo Molnar { 546e2780a68SIngo Molnar return physid_isset(read_apic_id(), phys_cpu_present_map); 547e2780a68SIngo Molnar } 548e2780a68SIngo Molnar 549f56e5034SYinghai Lu static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 550f56e5034SYinghai Lu { 551f56e5034SYinghai Lu return cpuid_apic >> index_msb; 552f56e5034SYinghai Lu } 553f56e5034SYinghai Lu 554f56e5034SYinghai Lu #endif 555f56e5034SYinghai Lu 55691cd9cb7SThomas Gleixner extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask, 5570e24f7c9SThomas Gleixner struct irq_data *irqdata, 558ad95212eSThomas Gleixner unsigned int *apicid); 55991cd9cb7SThomas Gleixner extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask, 5600e24f7c9SThomas Gleixner struct irq_data *irqdata, 561ff164324SAlexander Gordeev unsigned int *apicid); 5626398268dSAlexander Gordeev 563b39f25a8SSuresh Siddha static inline void 5641ac322d0SSuresh Siddha flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 5651ac322d0SSuresh Siddha const struct cpumask *mask) 5669d8e1066SAlexander Gordeev { 5679d8e1066SAlexander Gordeev /* Careful. Some cpus do not strictly honor the set of cpus 5689d8e1066SAlexander Gordeev * specified in the interrupt destination when using lowest 5699d8e1066SAlexander Gordeev * priority interrupt delivery mode. 5709d8e1066SAlexander Gordeev * 5719d8e1066SAlexander Gordeev * In particular there was a hyperthreading cpu observed to 5729d8e1066SAlexander Gordeev * deliver interrupts to the wrong hyperthread when only one 5739d8e1066SAlexander Gordeev * hyperthread was specified in the interrupt desitination. 5749d8e1066SAlexander Gordeev */ 5759d8e1066SAlexander Gordeev cpumask_clear(retmask); 5769d8e1066SAlexander Gordeev cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 5779d8e1066SAlexander Gordeev } 5789d8e1066SAlexander Gordeev 579b39f25a8SSuresh Siddha static inline void 5801ac322d0SSuresh Siddha default_vector_allocation_domain(int cpu, struct cpumask *retmask, 5811ac322d0SSuresh Siddha const struct cpumask *mask) 5829d8e1066SAlexander Gordeev { 5839d8e1066SAlexander Gordeev cpumask_copy(retmask, cpumask_of(cpu)); 5849d8e1066SAlexander Gordeev } 5859d8e1066SAlexander Gordeev 5867abc0753SCyrill Gorcunov static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 587e2780a68SIngo Molnar { 5887abc0753SCyrill Gorcunov return physid_isset(apicid, *map); 589e2780a68SIngo Molnar } 590e2780a68SIngo Molnar 5917abc0753SCyrill Gorcunov static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 592e2780a68SIngo Molnar { 5937abc0753SCyrill Gorcunov *retmap = *phys_map; 594e2780a68SIngo Molnar } 595e2780a68SIngo Molnar 596e2780a68SIngo Molnar static inline int __default_cpu_present_to_apicid(int mps_cpu) 597e2780a68SIngo Molnar { 598e2780a68SIngo Molnar if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 599e2780a68SIngo Molnar return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 600e2780a68SIngo Molnar else 601e2780a68SIngo Molnar return BAD_APICID; 602e2780a68SIngo Molnar } 603e2780a68SIngo Molnar 604e2780a68SIngo Molnar static inline int 605e11dadabSThomas Gleixner __default_check_phys_apicid_present(int phys_apicid) 606e2780a68SIngo Molnar { 607e11dadabSThomas Gleixner return physid_isset(phys_apicid, phys_cpu_present_map); 608e2780a68SIngo Molnar } 609e2780a68SIngo Molnar 610e2780a68SIngo Molnar #ifdef CONFIG_X86_32 611e2780a68SIngo Molnar static inline int default_cpu_present_to_apicid(int mps_cpu) 612e2780a68SIngo Molnar { 613e2780a68SIngo Molnar return __default_cpu_present_to_apicid(mps_cpu); 614e2780a68SIngo Molnar } 615e2780a68SIngo Molnar 616e2780a68SIngo Molnar static inline int 617e11dadabSThomas Gleixner default_check_phys_apicid_present(int phys_apicid) 618e2780a68SIngo Molnar { 619e11dadabSThomas Gleixner return __default_check_phys_apicid_present(phys_apicid); 620e2780a68SIngo Molnar } 621e2780a68SIngo Molnar #else 622e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 623e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 624e2780a68SIngo Molnar #endif 625e2780a68SIngo Molnar 626e2780a68SIngo Molnar #endif /* CONFIG_X86_LOCAL_APIC */ 627eddc0e92SSeiji Aguchi extern void irq_enter(void); 628eddc0e92SSeiji Aguchi extern void irq_exit(void); 629eddc0e92SSeiji Aguchi 630eddc0e92SSeiji Aguchi static inline void entering_irq(void) 631eddc0e92SSeiji Aguchi { 632eddc0e92SSeiji Aguchi irq_enter(); 633eddc0e92SSeiji Aguchi } 634eddc0e92SSeiji Aguchi 635eddc0e92SSeiji Aguchi static inline void entering_ack_irq(void) 636eddc0e92SSeiji Aguchi { 637eddc0e92SSeiji Aguchi entering_irq(); 6387834c103SDave Jones ack_APIC_irq(); 639eddc0e92SSeiji Aguchi } 640eddc0e92SSeiji Aguchi 6416dc17876SThomas Gleixner static inline void ipi_entering_ack_irq(void) 6426dc17876SThomas Gleixner { 6436dc17876SThomas Gleixner irq_enter(); 644b0f48706SWanpeng Li ack_APIC_irq(); 6456dc17876SThomas Gleixner } 6466dc17876SThomas Gleixner 647eddc0e92SSeiji Aguchi static inline void exiting_irq(void) 648eddc0e92SSeiji Aguchi { 649eddc0e92SSeiji Aguchi irq_exit(); 650eddc0e92SSeiji Aguchi } 651eddc0e92SSeiji Aguchi 652eddc0e92SSeiji Aguchi static inline void exiting_ack_irq(void) 653eddc0e92SSeiji Aguchi { 654eddc0e92SSeiji Aguchi ack_APIC_irq(); 655b0f48706SWanpeng Li irq_exit(); 656eddc0e92SSeiji Aguchi } 657e2780a68SIngo Molnar 65817405453SYoshihiro YUNOMAE extern void ioapic_zap_locks(void); 65917405453SYoshihiro YUNOMAE 6601965aae3SH. Peter Anvin #endif /* _ASM_X86_APIC_H */ 661