11965aae3SH. Peter Anvin #ifndef _ASM_X86_APIC_H 21965aae3SH. Peter Anvin #define _ASM_X86_APIC_H 3bb898558SAl Viro 4e2780a68SIngo Molnar #include <linux/cpumask.h> 5bb898558SAl Viro 6bb898558SAl Viro #include <asm/alternative.h> 7bb898558SAl Viro #include <asm/cpufeature.h> 8e2780a68SIngo Molnar #include <asm/apicdef.h> 960063497SArun Sharma #include <linux/atomic.h> 10e2780a68SIngo Molnar #include <asm/fixmap.h> 11e2780a68SIngo Molnar #include <asm/mpspec.h> 12bb898558SAl Viro #include <asm/msr.h> 13bb898558SAl Viro 14bb898558SAl Viro #define ARCH_APICTIMER_STOPS_ON_C3 1 15bb898558SAl Viro 16bb898558SAl Viro /* 17bb898558SAl Viro * Debugging macros 18bb898558SAl Viro */ 19bb898558SAl Viro #define APIC_QUIET 0 20bb898558SAl Viro #define APIC_VERBOSE 1 21bb898558SAl Viro #define APIC_DEBUG 2 22bb898558SAl Viro 23b7c4948eSHidehiro Kawai /* Macros for apic_extnmi which controls external NMI masking */ 24b7c4948eSHidehiro Kawai #define APIC_EXTNMI_BSP 0 /* Default */ 25b7c4948eSHidehiro Kawai #define APIC_EXTNMI_ALL 1 26b7c4948eSHidehiro Kawai #define APIC_EXTNMI_NONE 2 27b7c4948eSHidehiro Kawai 28bb898558SAl Viro /* 29bb898558SAl Viro * Define the default level of output to be very little 30bb898558SAl Viro * This can be turned up by using apic=verbose for more 31bb898558SAl Viro * information and apic=debug for _lots_ of information. 32bb898558SAl Viro * apic_verbosity is defined in apic.c 33bb898558SAl Viro */ 34bb898558SAl Viro #define apic_printk(v, s, a...) do { \ 35bb898558SAl Viro if ((v) <= apic_verbosity) \ 36bb898558SAl Viro printk(s, ##a); \ 37bb898558SAl Viro } while (0) 38bb898558SAl Viro 39bb898558SAl Viro 40160d8dacSIngo Molnar #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 41bb898558SAl Viro extern void generic_apic_probe(void); 42160d8dacSIngo Molnar #else 43160d8dacSIngo Molnar static inline void generic_apic_probe(void) 44160d8dacSIngo Molnar { 45160d8dacSIngo Molnar } 46160d8dacSIngo Molnar #endif 47bb898558SAl Viro 48bb898558SAl Viro #ifdef CONFIG_X86_LOCAL_APIC 49bb898558SAl Viro 50bb898558SAl Viro extern unsigned int apic_verbosity; 51bb898558SAl Viro extern int local_apic_timer_c2_ok; 52bb898558SAl Viro 53bb898558SAl Viro extern int disable_apic; 541ade93efSJacob Pan extern unsigned int lapic_timer_frequency; 550939e4fdSIngo Molnar 560939e4fdSIngo Molnar #ifdef CONFIG_SMP 570939e4fdSIngo Molnar extern void __inquire_remote_apic(int apicid); 580939e4fdSIngo Molnar #else /* CONFIG_SMP */ 590939e4fdSIngo Molnar static inline void __inquire_remote_apic(int apicid) 600939e4fdSIngo Molnar { 610939e4fdSIngo Molnar } 620939e4fdSIngo Molnar #endif /* CONFIG_SMP */ 630939e4fdSIngo Molnar 640939e4fdSIngo Molnar static inline void default_inquire_remote_apic(int apicid) 650939e4fdSIngo Molnar { 660939e4fdSIngo Molnar if (apic_verbosity >= APIC_DEBUG) 670939e4fdSIngo Molnar __inquire_remote_apic(apicid); 680939e4fdSIngo Molnar } 690939e4fdSIngo Molnar 70bb898558SAl Viro /* 718312136fSCyrill Gorcunov * With 82489DX we can't rely on apic feature bit 728312136fSCyrill Gorcunov * retrieved via cpuid but still have to deal with 738312136fSCyrill Gorcunov * such an apic chip so we assume that SMP configuration 748312136fSCyrill Gorcunov * is found from MP table (64bit case uses ACPI mostly 758312136fSCyrill Gorcunov * which set smp presence flag as well so we are safe 768312136fSCyrill Gorcunov * to use this helper too). 778312136fSCyrill Gorcunov */ 788312136fSCyrill Gorcunov static inline bool apic_from_smp_config(void) 798312136fSCyrill Gorcunov { 808312136fSCyrill Gorcunov return smp_found_config && !disable_apic; 818312136fSCyrill Gorcunov } 828312136fSCyrill Gorcunov 838312136fSCyrill Gorcunov /* 84bb898558SAl Viro * Basic functions accessing APICs. 85bb898558SAl Viro */ 86bb898558SAl Viro #ifdef CONFIG_PARAVIRT 87bb898558SAl Viro #include <asm/paravirt.h> 88bb898558SAl Viro #endif 89bb898558SAl Viro 90bb898558SAl Viro extern int setup_profiling_timer(unsigned int); 91bb898558SAl Viro 92bb898558SAl Viro static inline void native_apic_mem_write(u32 reg, u32 v) 93bb898558SAl Viro { 94bb898558SAl Viro volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 95bb898558SAl Viro 96a930dc45SBorislav Petkov alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 97bb898558SAl Viro ASM_OUTPUT2("=r" (v), "=m" (*addr)), 98bb898558SAl Viro ASM_OUTPUT2("0" (v), "m" (*addr))); 99bb898558SAl Viro } 100bb898558SAl Viro 101bb898558SAl Viro static inline u32 native_apic_mem_read(u32 reg) 102bb898558SAl Viro { 103bb898558SAl Viro return *((volatile u32 *)(APIC_BASE + reg)); 104bb898558SAl Viro } 105bb898558SAl Viro 106c1eeb2deSYinghai Lu extern void native_apic_wait_icr_idle(void); 107c1eeb2deSYinghai Lu extern u32 native_safe_apic_wait_icr_idle(void); 108c1eeb2deSYinghai Lu extern void native_apic_icr_write(u32 low, u32 id); 109c1eeb2deSYinghai Lu extern u64 native_apic_icr_read(void); 110c1eeb2deSYinghai Lu 1118d806960SThomas Gleixner static inline bool apic_is_x2apic_enabled(void) 1128d806960SThomas Gleixner { 1138d806960SThomas Gleixner u64 msr; 1148d806960SThomas Gleixner 1158d806960SThomas Gleixner if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 1168d806960SThomas Gleixner return false; 1178d806960SThomas Gleixner return msr & X2APIC_ENABLE; 1188d806960SThomas Gleixner } 1198d806960SThomas Gleixner 120e02ae387SPaolo Bonzini extern void enable_IR_x2apic(void); 121e02ae387SPaolo Bonzini 122e02ae387SPaolo Bonzini extern int get_physical_broadcast(void); 123e02ae387SPaolo Bonzini 124e02ae387SPaolo Bonzini extern int lapic_get_maxlvt(void); 125e02ae387SPaolo Bonzini extern void clear_local_APIC(void); 126e02ae387SPaolo Bonzini extern void disconnect_bsp_APIC(int virt_wire_setup); 127e02ae387SPaolo Bonzini extern void disable_local_APIC(void); 128e02ae387SPaolo Bonzini extern void lapic_shutdown(void); 129e02ae387SPaolo Bonzini extern void sync_Arb_IDs(void); 130e02ae387SPaolo Bonzini extern void init_bsp_APIC(void); 1314b1669e8SDou Liyang extern void apic_intr_mode_init(void); 132e02ae387SPaolo Bonzini extern void setup_local_APIC(void); 133e02ae387SPaolo Bonzini extern void init_apic_mappings(void); 134e02ae387SPaolo Bonzini void register_lapic_address(unsigned long address); 135e02ae387SPaolo Bonzini extern void setup_boot_APIC_clock(void); 136e02ae387SPaolo Bonzini extern void setup_secondary_APIC_clock(void); 1376731b0d6SNicolai Stange extern void lapic_update_tsc_freq(void); 138e02ae387SPaolo Bonzini extern int APIC_init_uniprocessor(void); 139e02ae387SPaolo Bonzini 140e02ae387SPaolo Bonzini #ifdef CONFIG_X86_64 141e02ae387SPaolo Bonzini static inline int apic_force_enable(unsigned long addr) 142e02ae387SPaolo Bonzini { 143e02ae387SPaolo Bonzini return -1; 144e02ae387SPaolo Bonzini } 145e02ae387SPaolo Bonzini #else 146e02ae387SPaolo Bonzini extern int apic_force_enable(unsigned long addr); 147e02ae387SPaolo Bonzini #endif 148e02ae387SPaolo Bonzini 149e02ae387SPaolo Bonzini extern int apic_bsp_setup(bool upmode); 150e02ae387SPaolo Bonzini extern void apic_ap_setup(void); 151e02ae387SPaolo Bonzini 152e02ae387SPaolo Bonzini /* 153e02ae387SPaolo Bonzini * On 32bit this is mach-xxx local 154e02ae387SPaolo Bonzini */ 155e02ae387SPaolo Bonzini #ifdef CONFIG_X86_64 156e02ae387SPaolo Bonzini extern int apic_is_clustered_box(void); 157e02ae387SPaolo Bonzini #else 158e02ae387SPaolo Bonzini static inline int apic_is_clustered_box(void) 159e02ae387SPaolo Bonzini { 160e02ae387SPaolo Bonzini return 0; 161e02ae387SPaolo Bonzini } 162e02ae387SPaolo Bonzini #endif 163e02ae387SPaolo Bonzini 164e02ae387SPaolo Bonzini extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 165e02ae387SPaolo Bonzini 166e02ae387SPaolo Bonzini #else /* !CONFIG_X86_LOCAL_APIC */ 167e02ae387SPaolo Bonzini static inline void lapic_shutdown(void) { } 168e02ae387SPaolo Bonzini #define local_apic_timer_c2_ok 1 169e02ae387SPaolo Bonzini static inline void init_apic_mappings(void) { } 170e02ae387SPaolo Bonzini static inline void disable_local_APIC(void) { } 171e02ae387SPaolo Bonzini # define setup_boot_APIC_clock x86_init_noop 172e02ae387SPaolo Bonzini # define setup_secondary_APIC_clock x86_init_noop 1736731b0d6SNicolai Stange static inline void lapic_update_tsc_freq(void) { } 1744b1669e8SDou Liyang static inline void apic_intr_mode_init(void) { } 175e02ae387SPaolo Bonzini #endif /* !CONFIG_X86_LOCAL_APIC */ 176e02ae387SPaolo Bonzini 177d0b03bd1SHan, Weidong #ifdef CONFIG_X86_X2APIC 178ce4e240cSSuresh Siddha /* 179ce4e240cSSuresh Siddha * Make previous memory operations globally visible before 180ce4e240cSSuresh Siddha * sending the IPI through x2apic wrmsr. We need a serializing instruction or 181ce4e240cSSuresh Siddha * mfence for this. 182ce4e240cSSuresh Siddha */ 183ce4e240cSSuresh Siddha static inline void x2apic_wrmsr_fence(void) 184ce4e240cSSuresh Siddha { 185ce4e240cSSuresh Siddha asm volatile("mfence" : : : "memory"); 186ce4e240cSSuresh Siddha } 187ce4e240cSSuresh Siddha 188bb898558SAl Viro static inline void native_apic_msr_write(u32 reg, u32 v) 189bb898558SAl Viro { 190bb898558SAl Viro if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 191bb898558SAl Viro reg == APIC_LVR) 192bb898558SAl Viro return; 193bb898558SAl Viro 194bb898558SAl Viro wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 195bb898558SAl Viro } 196bb898558SAl Viro 1970ab711aeSMichael S. Tsirkin static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 1980ab711aeSMichael S. Tsirkin { 199a585df8eSBorislav Petkov __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 2000ab711aeSMichael S. Tsirkin } 2010ab711aeSMichael S. Tsirkin 202bb898558SAl Viro static inline u32 native_apic_msr_read(u32 reg) 203bb898558SAl Viro { 2040059b243SAndi Kleen u64 msr; 205bb898558SAl Viro 206bb898558SAl Viro if (reg == APIC_DFR) 207bb898558SAl Viro return -1; 208bb898558SAl Viro 2090059b243SAndi Kleen rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 2100059b243SAndi Kleen return (u32)msr; 211bb898558SAl Viro } 212bb898558SAl Viro 213c1eeb2deSYinghai Lu static inline void native_x2apic_wait_icr_idle(void) 214c1eeb2deSYinghai Lu { 215c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 216c1eeb2deSYinghai Lu return; 217c1eeb2deSYinghai Lu } 218c1eeb2deSYinghai Lu 219c1eeb2deSYinghai Lu static inline u32 native_safe_x2apic_wait_icr_idle(void) 220c1eeb2deSYinghai Lu { 221c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 222c1eeb2deSYinghai Lu return 0; 223c1eeb2deSYinghai Lu } 224c1eeb2deSYinghai Lu 225c1eeb2deSYinghai Lu static inline void native_x2apic_icr_write(u32 low, u32 id) 226c1eeb2deSYinghai Lu { 227c1eeb2deSYinghai Lu wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 228c1eeb2deSYinghai Lu } 229c1eeb2deSYinghai Lu 230c1eeb2deSYinghai Lu static inline u64 native_x2apic_icr_read(void) 231c1eeb2deSYinghai Lu { 232c1eeb2deSYinghai Lu unsigned long val; 233c1eeb2deSYinghai Lu 234c1eeb2deSYinghai Lu rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 235c1eeb2deSYinghai Lu return val; 236c1eeb2deSYinghai Lu } 237c1eeb2deSYinghai Lu 23881a46dd8SThomas Gleixner extern int x2apic_mode; 239fc1edaf9SSuresh Siddha extern int x2apic_phys; 240d524165cSThomas Gleixner extern void __init check_x2apic(void); 241659006bfSThomas Gleixner extern void x2apic_setup(void); 242bb898558SAl Viro static inline int x2apic_enabled(void) 243bb898558SAl Viro { 24462436a4dSBorislav Petkov return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 245bb898558SAl Viro } 246fc1edaf9SSuresh Siddha 24762436a4dSBorislav Petkov #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 248e02ae387SPaolo Bonzini #else /* !CONFIG_X86_X2APIC */ 24955eae7deSThomas Gleixner static inline void check_x2apic(void) { } 250659006bfSThomas Gleixner static inline void x2apic_setup(void) { } 25155eae7deSThomas Gleixner static inline int x2apic_enabled(void) { return 0; } 252cf6567feSSuresh Siddha 25381a46dd8SThomas Gleixner #define x2apic_mode (0) 25481a46dd8SThomas Gleixner #define x2apic_supported() (0) 255e02ae387SPaolo Bonzini #endif /* !CONFIG_X86_X2APIC */ 256bb898558SAl Viro 2570e24f7c9SThomas Gleixner struct irq_data; 2580e24f7c9SThomas Gleixner 259e2780a68SIngo Molnar /* 260e2780a68SIngo Molnar * Copyright 2004 James Cleverdon, IBM. 261e2780a68SIngo Molnar * Subject to the GNU Public License, v.2 262e2780a68SIngo Molnar * 263e2780a68SIngo Molnar * Generic APIC sub-arch data struct. 264e2780a68SIngo Molnar * 265e2780a68SIngo Molnar * Hacked for x86-64 by James Cleverdon from i386 architecture code by 266e2780a68SIngo Molnar * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 267e2780a68SIngo Molnar * James Cleverdon. 268e2780a68SIngo Molnar */ 269be163a15SIngo Molnar struct apic { 270e2780a68SIngo Molnar char *name; 271e2780a68SIngo Molnar 272e2780a68SIngo Molnar int (*probe)(void); 273e2780a68SIngo Molnar int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 274fa63030eSDaniel J Blueman int (*apic_id_valid)(int apicid); 275e2780a68SIngo Molnar int (*apic_id_registered)(void); 276e2780a68SIngo Molnar 277e2780a68SIngo Molnar u32 irq_delivery_mode; 278e2780a68SIngo Molnar u32 irq_dest_mode; 279e2780a68SIngo Molnar 280e2780a68SIngo Molnar const struct cpumask *(*target_cpus)(void); 281e2780a68SIngo Molnar 282e2780a68SIngo Molnar int disable_esr; 283e2780a68SIngo Molnar 284e2780a68SIngo Molnar int dest_logical; 2857abc0753SCyrill Gorcunov unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 286e2780a68SIngo Molnar 2871ac322d0SSuresh Siddha void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 2881ac322d0SSuresh Siddha const struct cpumask *mask); 289e2780a68SIngo Molnar void (*init_apic_ldr)(void); 290e2780a68SIngo Molnar 2917abc0753SCyrill Gorcunov void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 292e2780a68SIngo Molnar 293e2780a68SIngo Molnar void (*setup_apic_routing)(void); 294e2780a68SIngo Molnar int (*cpu_present_to_apicid)(int mps_cpu); 2957abc0753SCyrill Gorcunov void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 296e11dadabSThomas Gleixner int (*check_phys_apicid_present)(int phys_apicid); 297e2780a68SIngo Molnar int (*phys_pkg_id)(int cpuid_apic, int index_msb); 298e2780a68SIngo Molnar 299e2780a68SIngo Molnar unsigned int (*get_apic_id)(unsigned long x); 3005d64d209SDou Liyang /* Can't be NULL on 64-bit */ 301e2780a68SIngo Molnar unsigned long (*set_apic_id)(unsigned int id); 302e2780a68SIngo Molnar 30391cd9cb7SThomas Gleixner int (*cpu_mask_to_apicid)(const struct cpumask *cpumask, 3040e24f7c9SThomas Gleixner struct irq_data *irqdata, 305ff164324SAlexander Gordeev unsigned int *apicid); 306e2780a68SIngo Molnar 307e2780a68SIngo Molnar /* ipi */ 308539da787SLinus Torvalds void (*send_IPI)(int cpu, int vector); 309e2780a68SIngo Molnar void (*send_IPI_mask)(const struct cpumask *mask, int vector); 310e2780a68SIngo Molnar void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 311e2780a68SIngo Molnar int vector); 312e2780a68SIngo Molnar void (*send_IPI_allbutself)(int vector); 313e2780a68SIngo Molnar void (*send_IPI_all)(int vector); 314e2780a68SIngo Molnar void (*send_IPI_self)(int vector); 315e2780a68SIngo Molnar 316e2780a68SIngo Molnar /* wakeup_secondary_cpu */ 3171f5bcabfSIngo Molnar int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 318e2780a68SIngo Molnar 319e2780a68SIngo Molnar void (*inquire_remote_apic)(int apicid); 320e2780a68SIngo Molnar 321e2780a68SIngo Molnar /* apic ops */ 322e2780a68SIngo Molnar u32 (*read)(u32 reg); 323e2780a68SIngo Molnar void (*write)(u32 reg, u32 v); 3242a43195dSMichael S. Tsirkin /* 3252a43195dSMichael S. Tsirkin * ->eoi_write() has the same signature as ->write(). 3262a43195dSMichael S. Tsirkin * 3272a43195dSMichael S. Tsirkin * Drivers can support both ->eoi_write() and ->write() by passing the same 3282a43195dSMichael S. Tsirkin * callback value. Kernel can override ->eoi_write() and fall back 3292a43195dSMichael S. Tsirkin * on write for EOI. 3302a43195dSMichael S. Tsirkin */ 3312a43195dSMichael S. Tsirkin void (*eoi_write)(u32 reg, u32 v); 3328ca22552SWanpeng Li void (*native_eoi_write)(u32 reg, u32 v); 333e2780a68SIngo Molnar u64 (*icr_read)(void); 334e2780a68SIngo Molnar void (*icr_write)(u32 low, u32 high); 335e2780a68SIngo Molnar void (*wait_icr_idle)(void); 336e2780a68SIngo Molnar u32 (*safe_wait_icr_idle)(void); 337acb8bc09STejun Heo 338acb8bc09STejun Heo #ifdef CONFIG_X86_32 339acb8bc09STejun Heo /* 340acb8bc09STejun Heo * Called very early during boot from get_smp_config(). It should 341acb8bc09STejun Heo * return the logical apicid. x86_[bios]_cpu_to_apicid is 342acb8bc09STejun Heo * initialized before this function is called. 343acb8bc09STejun Heo * 344acb8bc09STejun Heo * If logical apicid can't be determined that early, the function 345acb8bc09STejun Heo * may return BAD_APICID. Logical apicid will be configured after 346acb8bc09STejun Heo * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 347acb8bc09STejun Heo * won't be applied properly during early boot in this case. 348acb8bc09STejun Heo */ 349acb8bc09STejun Heo int (*x86_32_early_logical_apicid)(int cpu); 350acb8bc09STejun Heo #endif 351e2780a68SIngo Molnar }; 352e2780a68SIngo Molnar 3530917c01fSIngo Molnar /* 3540917c01fSIngo Molnar * Pointer to the local APIC driver in use on this system (there's 3550917c01fSIngo Molnar * always just one such driver in use - the kernel decides via an 3560917c01fSIngo Molnar * early probing process which one it picks - and then sticks to it): 3570917c01fSIngo Molnar */ 358be163a15SIngo Molnar extern struct apic *apic; 3590917c01fSIngo Molnar 3600917c01fSIngo Molnar /* 361107e0e0cSSuresh Siddha * APIC drivers are probed based on how they are listed in the .apicdrivers 362107e0e0cSSuresh Siddha * section. So the order is important and enforced by the ordering 363107e0e0cSSuresh Siddha * of different apic driver files in the Makefile. 364107e0e0cSSuresh Siddha * 365107e0e0cSSuresh Siddha * For the files having two apic drivers, we use apic_drivers() 366107e0e0cSSuresh Siddha * to enforce the order with in them. 367107e0e0cSSuresh Siddha */ 368107e0e0cSSuresh Siddha #define apic_driver(sym) \ 36975fdd155SAndi Kleen static const struct apic *__apicdrivers_##sym __used \ 370107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 371107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym } 372107e0e0cSSuresh Siddha 373107e0e0cSSuresh Siddha #define apic_drivers(sym1, sym2) \ 374107e0e0cSSuresh Siddha static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 375107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 376107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym1, &sym2 } 377107e0e0cSSuresh Siddha 378107e0e0cSSuresh Siddha extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 379107e0e0cSSuresh Siddha 380107e0e0cSSuresh Siddha /* 3810917c01fSIngo Molnar * APIC functionality to boot other CPUs - only used on SMP: 3820917c01fSIngo Molnar */ 3830917c01fSIngo Molnar #ifdef CONFIG_SMP 3842b6163bfSYinghai Lu extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 3850917c01fSIngo Molnar #endif 386e2780a68SIngo Molnar 387d674cd19SCyrill Gorcunov #ifdef CONFIG_X86_LOCAL_APIC 388346b46beSFernando Luis Vázquez Cao 389e2780a68SIngo Molnar static inline u32 apic_read(u32 reg) 390e2780a68SIngo Molnar { 391e2780a68SIngo Molnar return apic->read(reg); 392e2780a68SIngo Molnar } 393e2780a68SIngo Molnar 394e2780a68SIngo Molnar static inline void apic_write(u32 reg, u32 val) 395e2780a68SIngo Molnar { 396e2780a68SIngo Molnar apic->write(reg, val); 397e2780a68SIngo Molnar } 398e2780a68SIngo Molnar 3992a43195dSMichael S. Tsirkin static inline void apic_eoi(void) 4002a43195dSMichael S. Tsirkin { 4012a43195dSMichael S. Tsirkin apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 4022a43195dSMichael S. Tsirkin } 4032a43195dSMichael S. Tsirkin 404e2780a68SIngo Molnar static inline u64 apic_icr_read(void) 405e2780a68SIngo Molnar { 406e2780a68SIngo Molnar return apic->icr_read(); 407e2780a68SIngo Molnar } 408e2780a68SIngo Molnar 409e2780a68SIngo Molnar static inline void apic_icr_write(u32 low, u32 high) 410e2780a68SIngo Molnar { 411e2780a68SIngo Molnar apic->icr_write(low, high); 412e2780a68SIngo Molnar } 413e2780a68SIngo Molnar 414e2780a68SIngo Molnar static inline void apic_wait_icr_idle(void) 415e2780a68SIngo Molnar { 416e2780a68SIngo Molnar apic->wait_icr_idle(); 417e2780a68SIngo Molnar } 418e2780a68SIngo Molnar 419e2780a68SIngo Molnar static inline u32 safe_apic_wait_icr_idle(void) 420e2780a68SIngo Molnar { 421e2780a68SIngo Molnar return apic->safe_wait_icr_idle(); 422e2780a68SIngo Molnar } 423e2780a68SIngo Molnar 4241551df64SMichael S. Tsirkin extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 4251551df64SMichael S. Tsirkin 426d674cd19SCyrill Gorcunov #else /* CONFIG_X86_LOCAL_APIC */ 427d674cd19SCyrill Gorcunov 428d674cd19SCyrill Gorcunov static inline u32 apic_read(u32 reg) { return 0; } 429d674cd19SCyrill Gorcunov static inline void apic_write(u32 reg, u32 val) { } 4302a43195dSMichael S. Tsirkin static inline void apic_eoi(void) { } 431d674cd19SCyrill Gorcunov static inline u64 apic_icr_read(void) { return 0; } 432d674cd19SCyrill Gorcunov static inline void apic_icr_write(u32 low, u32 high) { } 433d674cd19SCyrill Gorcunov static inline void apic_wait_icr_idle(void) { } 434d674cd19SCyrill Gorcunov static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 4351551df64SMichael S. Tsirkin static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 436d674cd19SCyrill Gorcunov 437d674cd19SCyrill Gorcunov #endif /* CONFIG_X86_LOCAL_APIC */ 438e2780a68SIngo Molnar 439e2780a68SIngo Molnar static inline void ack_APIC_irq(void) 440e2780a68SIngo Molnar { 441e2780a68SIngo Molnar /* 442e2780a68SIngo Molnar * ack_APIC_irq() actually gets compiled as a single instruction 443e2780a68SIngo Molnar * ... yummie. 444e2780a68SIngo Molnar */ 4452a43195dSMichael S. Tsirkin apic_eoi(); 446e2780a68SIngo Molnar } 447e2780a68SIngo Molnar 448e2780a68SIngo Molnar static inline unsigned default_get_apic_id(unsigned long x) 449e2780a68SIngo Molnar { 450e2780a68SIngo Molnar unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 451e2780a68SIngo Molnar 45242937e81SAndreas Herrmann if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 453e2780a68SIngo Molnar return (x >> 24) & 0xFF; 454e2780a68SIngo Molnar else 455e2780a68SIngo Molnar return (x >> 24) & 0x0F; 456e2780a68SIngo Molnar } 457e2780a68SIngo Molnar 458e2780a68SIngo Molnar /* 4596ab1b27cSDavid Rientjes * Warm reset vector position: 460e2780a68SIngo Molnar */ 4616ab1b27cSDavid Rientjes #define TRAMPOLINE_PHYS_LOW 0x467 4626ab1b27cSDavid Rientjes #define TRAMPOLINE_PHYS_HIGH 0x469 463e2780a68SIngo Molnar 4642b6163bfSYinghai Lu #ifdef CONFIG_X86_64 465e2780a68SIngo Molnar extern void apic_send_IPI_self(int vector); 466e2780a68SIngo Molnar 467e2780a68SIngo Molnar DECLARE_PER_CPU(int, x2apic_extra_bits); 468e2780a68SIngo Molnar 469e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 470e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 471e2780a68SIngo Molnar #endif 472e2780a68SIngo Molnar 473838312beSJan Beulich extern void generic_bigsmp_probe(void); 474e2780a68SIngo Molnar 475e2780a68SIngo Molnar 476e2780a68SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 477e2780a68SIngo Molnar 478e2780a68SIngo Molnar #include <asm/smp.h> 479e2780a68SIngo Molnar 480e2780a68SIngo Molnar #define APIC_DFR_VALUE (APIC_DFR_FLAT) 481e2780a68SIngo Molnar 482e2780a68SIngo Molnar static inline const struct cpumask *default_target_cpus(void) 483e2780a68SIngo Molnar { 484e2780a68SIngo Molnar #ifdef CONFIG_SMP 485e2780a68SIngo Molnar return cpu_online_mask; 486e2780a68SIngo Molnar #else 487e2780a68SIngo Molnar return cpumask_of(0); 488e2780a68SIngo Molnar #endif 489e2780a68SIngo Molnar } 490e2780a68SIngo Molnar 491bf721d3aSAlexander Gordeev static inline const struct cpumask *online_target_cpus(void) 492bf721d3aSAlexander Gordeev { 493bf721d3aSAlexander Gordeev return cpu_online_mask; 494bf721d3aSAlexander Gordeev } 495bf721d3aSAlexander Gordeev 4960816b0f0SVlad Zolotarov DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 497e2780a68SIngo Molnar 498e2780a68SIngo Molnar 499e2780a68SIngo Molnar static inline unsigned int read_apic_id(void) 500e2780a68SIngo Molnar { 501e2780a68SIngo Molnar unsigned int reg; 502e2780a68SIngo Molnar 503e2780a68SIngo Molnar reg = apic_read(APIC_ID); 504e2780a68SIngo Molnar 505e2780a68SIngo Molnar return apic->get_apic_id(reg); 506e2780a68SIngo Molnar } 507e2780a68SIngo Molnar 508fa63030eSDaniel J Blueman static inline int default_apic_id_valid(int apicid) 509fa63030eSDaniel J Blueman { 510b7157acfSSteffen Persvold return (apicid < 255); 511fa63030eSDaniel J Blueman } 512fa63030eSDaniel J Blueman 513a491cc90SJiang Liu extern int default_acpi_madt_oem_check(char *, char *); 514a491cc90SJiang Liu 515e2780a68SIngo Molnar extern void default_setup_apic_routing(void); 516e2780a68SIngo Molnar 5179844ab11SCyrill Gorcunov extern struct apic apic_noop; 5189844ab11SCyrill Gorcunov 519e2780a68SIngo Molnar #ifdef CONFIG_X86_32 5202c1b284eSJaswinder Singh Rajput 521acb8bc09STejun Heo static inline int noop_x86_32_early_logical_apicid(int cpu) 522acb8bc09STejun Heo { 523acb8bc09STejun Heo return BAD_APICID; 524acb8bc09STejun Heo } 525acb8bc09STejun Heo 526e2780a68SIngo Molnar /* 527e2780a68SIngo Molnar * Set up the logical destination ID. 528e2780a68SIngo Molnar * 529e2780a68SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 530e2780a68SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 531e2780a68SIngo Molnar * document number 292116). So here it goes... 532e2780a68SIngo Molnar */ 533e2780a68SIngo Molnar extern void default_init_apic_ldr(void); 534e2780a68SIngo Molnar 535e2780a68SIngo Molnar static inline int default_apic_id_registered(void) 536e2780a68SIngo Molnar { 537e2780a68SIngo Molnar return physid_isset(read_apic_id(), phys_cpu_present_map); 538e2780a68SIngo Molnar } 539e2780a68SIngo Molnar 540f56e5034SYinghai Lu static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 541f56e5034SYinghai Lu { 542f56e5034SYinghai Lu return cpuid_apic >> index_msb; 543f56e5034SYinghai Lu } 544f56e5034SYinghai Lu 545f56e5034SYinghai Lu #endif 546f56e5034SYinghai Lu 54791cd9cb7SThomas Gleixner extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask, 5480e24f7c9SThomas Gleixner struct irq_data *irqdata, 549ad95212eSThomas Gleixner unsigned int *apicid); 55091cd9cb7SThomas Gleixner extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask, 5510e24f7c9SThomas Gleixner struct irq_data *irqdata, 552ff164324SAlexander Gordeev unsigned int *apicid); 5536398268dSAlexander Gordeev 554b39f25a8SSuresh Siddha static inline void 5551ac322d0SSuresh Siddha flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 5561ac322d0SSuresh Siddha const struct cpumask *mask) 5579d8e1066SAlexander Gordeev { 5589d8e1066SAlexander Gordeev /* Careful. Some cpus do not strictly honor the set of cpus 5599d8e1066SAlexander Gordeev * specified in the interrupt destination when using lowest 5609d8e1066SAlexander Gordeev * priority interrupt delivery mode. 5619d8e1066SAlexander Gordeev * 5629d8e1066SAlexander Gordeev * In particular there was a hyperthreading cpu observed to 5639d8e1066SAlexander Gordeev * deliver interrupts to the wrong hyperthread when only one 5649d8e1066SAlexander Gordeev * hyperthread was specified in the interrupt desitination. 5659d8e1066SAlexander Gordeev */ 5669d8e1066SAlexander Gordeev cpumask_clear(retmask); 5679d8e1066SAlexander Gordeev cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 5689d8e1066SAlexander Gordeev } 5699d8e1066SAlexander Gordeev 570b39f25a8SSuresh Siddha static inline void 5711ac322d0SSuresh Siddha default_vector_allocation_domain(int cpu, struct cpumask *retmask, 5721ac322d0SSuresh Siddha const struct cpumask *mask) 5739d8e1066SAlexander Gordeev { 5749d8e1066SAlexander Gordeev cpumask_copy(retmask, cpumask_of(cpu)); 5759d8e1066SAlexander Gordeev } 5769d8e1066SAlexander Gordeev 5777abc0753SCyrill Gorcunov static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 578e2780a68SIngo Molnar { 5797abc0753SCyrill Gorcunov return physid_isset(apicid, *map); 580e2780a68SIngo Molnar } 581e2780a68SIngo Molnar 5827abc0753SCyrill Gorcunov static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 583e2780a68SIngo Molnar { 5847abc0753SCyrill Gorcunov *retmap = *phys_map; 585e2780a68SIngo Molnar } 586e2780a68SIngo Molnar 587e2780a68SIngo Molnar static inline int __default_cpu_present_to_apicid(int mps_cpu) 588e2780a68SIngo Molnar { 589e2780a68SIngo Molnar if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 590e2780a68SIngo Molnar return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 591e2780a68SIngo Molnar else 592e2780a68SIngo Molnar return BAD_APICID; 593e2780a68SIngo Molnar } 594e2780a68SIngo Molnar 595e2780a68SIngo Molnar static inline int 596e11dadabSThomas Gleixner __default_check_phys_apicid_present(int phys_apicid) 597e2780a68SIngo Molnar { 598e11dadabSThomas Gleixner return physid_isset(phys_apicid, phys_cpu_present_map); 599e2780a68SIngo Molnar } 600e2780a68SIngo Molnar 601e2780a68SIngo Molnar #ifdef CONFIG_X86_32 602e2780a68SIngo Molnar static inline int default_cpu_present_to_apicid(int mps_cpu) 603e2780a68SIngo Molnar { 604e2780a68SIngo Molnar return __default_cpu_present_to_apicid(mps_cpu); 605e2780a68SIngo Molnar } 606e2780a68SIngo Molnar 607e2780a68SIngo Molnar static inline int 608e11dadabSThomas Gleixner default_check_phys_apicid_present(int phys_apicid) 609e2780a68SIngo Molnar { 610e11dadabSThomas Gleixner return __default_check_phys_apicid_present(phys_apicid); 611e2780a68SIngo Molnar } 612e2780a68SIngo Molnar #else 613e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 614e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 615e2780a68SIngo Molnar #endif 616e2780a68SIngo Molnar 617e2780a68SIngo Molnar #endif /* CONFIG_X86_LOCAL_APIC */ 618eddc0e92SSeiji Aguchi extern void irq_enter(void); 619eddc0e92SSeiji Aguchi extern void irq_exit(void); 620eddc0e92SSeiji Aguchi 621eddc0e92SSeiji Aguchi static inline void entering_irq(void) 622eddc0e92SSeiji Aguchi { 623eddc0e92SSeiji Aguchi irq_enter(); 624eddc0e92SSeiji Aguchi } 625eddc0e92SSeiji Aguchi 626eddc0e92SSeiji Aguchi static inline void entering_ack_irq(void) 627eddc0e92SSeiji Aguchi { 628eddc0e92SSeiji Aguchi entering_irq(); 6297834c103SDave Jones ack_APIC_irq(); 630eddc0e92SSeiji Aguchi } 631eddc0e92SSeiji Aguchi 6326dc17876SThomas Gleixner static inline void ipi_entering_ack_irq(void) 6336dc17876SThomas Gleixner { 6346dc17876SThomas Gleixner irq_enter(); 635b0f48706SWanpeng Li ack_APIC_irq(); 6366dc17876SThomas Gleixner } 6376dc17876SThomas Gleixner 638eddc0e92SSeiji Aguchi static inline void exiting_irq(void) 639eddc0e92SSeiji Aguchi { 640eddc0e92SSeiji Aguchi irq_exit(); 641eddc0e92SSeiji Aguchi } 642eddc0e92SSeiji Aguchi 643eddc0e92SSeiji Aguchi static inline void exiting_ack_irq(void) 644eddc0e92SSeiji Aguchi { 645eddc0e92SSeiji Aguchi ack_APIC_irq(); 646b0f48706SWanpeng Li irq_exit(); 647eddc0e92SSeiji Aguchi } 648e2780a68SIngo Molnar 64917405453SYoshihiro YUNOMAE extern void ioapic_zap_locks(void); 65017405453SYoshihiro YUNOMAE 6511965aae3SH. Peter Anvin #endif /* _ASM_X86_APIC_H */ 652