11965aae3SH. Peter Anvin #ifndef _ASM_X86_APIC_H 21965aae3SH. Peter Anvin #define _ASM_X86_APIC_H 3bb898558SAl Viro 4e2780a68SIngo Molnar #include <linux/cpumask.h> 5e2780a68SIngo Molnar #include <linux/pm.h> 6bb898558SAl Viro 7bb898558SAl Viro #include <asm/alternative.h> 8bb898558SAl Viro #include <asm/cpufeature.h> 9e2780a68SIngo Molnar #include <asm/processor.h> 10e2780a68SIngo Molnar #include <asm/apicdef.h> 1160063497SArun Sharma #include <linux/atomic.h> 12e2780a68SIngo Molnar #include <asm/fixmap.h> 13e2780a68SIngo Molnar #include <asm/mpspec.h> 14e2780a68SIngo Molnar #include <asm/system.h> 15bb898558SAl Viro #include <asm/msr.h> 16bb898558SAl Viro 17bb898558SAl Viro #define ARCH_APICTIMER_STOPS_ON_C3 1 18bb898558SAl Viro 19bb898558SAl Viro /* 20bb898558SAl Viro * Debugging macros 21bb898558SAl Viro */ 22bb898558SAl Viro #define APIC_QUIET 0 23bb898558SAl Viro #define APIC_VERBOSE 1 24bb898558SAl Viro #define APIC_DEBUG 2 25bb898558SAl Viro 26bb898558SAl Viro /* 27bb898558SAl Viro * Define the default level of output to be very little 28bb898558SAl Viro * This can be turned up by using apic=verbose for more 29bb898558SAl Viro * information and apic=debug for _lots_ of information. 30bb898558SAl Viro * apic_verbosity is defined in apic.c 31bb898558SAl Viro */ 32bb898558SAl Viro #define apic_printk(v, s, a...) do { \ 33bb898558SAl Viro if ((v) <= apic_verbosity) \ 34bb898558SAl Viro printk(s, ##a); \ 35bb898558SAl Viro } while (0) 36bb898558SAl Viro 37bb898558SAl Viro 38160d8dacSIngo Molnar #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39bb898558SAl Viro extern void generic_apic_probe(void); 40160d8dacSIngo Molnar #else 41160d8dacSIngo Molnar static inline void generic_apic_probe(void) 42160d8dacSIngo Molnar { 43160d8dacSIngo Molnar } 44160d8dacSIngo Molnar #endif 45bb898558SAl Viro 46bb898558SAl Viro #ifdef CONFIG_X86_LOCAL_APIC 47bb898558SAl Viro 48bb898558SAl Viro extern unsigned int apic_verbosity; 49bb898558SAl Viro extern int local_apic_timer_c2_ok; 50bb898558SAl Viro 51bb898558SAl Viro extern int disable_apic; 521ade93efSJacob Pan extern unsigned int lapic_timer_frequency; 530939e4fdSIngo Molnar 540939e4fdSIngo Molnar #ifdef CONFIG_SMP 550939e4fdSIngo Molnar extern void __inquire_remote_apic(int apicid); 560939e4fdSIngo Molnar #else /* CONFIG_SMP */ 570939e4fdSIngo Molnar static inline void __inquire_remote_apic(int apicid) 580939e4fdSIngo Molnar { 590939e4fdSIngo Molnar } 600939e4fdSIngo Molnar #endif /* CONFIG_SMP */ 610939e4fdSIngo Molnar 620939e4fdSIngo Molnar static inline void default_inquire_remote_apic(int apicid) 630939e4fdSIngo Molnar { 640939e4fdSIngo Molnar if (apic_verbosity >= APIC_DEBUG) 650939e4fdSIngo Molnar __inquire_remote_apic(apicid); 660939e4fdSIngo Molnar } 670939e4fdSIngo Molnar 68bb898558SAl Viro /* 698312136fSCyrill Gorcunov * With 82489DX we can't rely on apic feature bit 708312136fSCyrill Gorcunov * retrieved via cpuid but still have to deal with 718312136fSCyrill Gorcunov * such an apic chip so we assume that SMP configuration 728312136fSCyrill Gorcunov * is found from MP table (64bit case uses ACPI mostly 738312136fSCyrill Gorcunov * which set smp presence flag as well so we are safe 748312136fSCyrill Gorcunov * to use this helper too). 758312136fSCyrill Gorcunov */ 768312136fSCyrill Gorcunov static inline bool apic_from_smp_config(void) 778312136fSCyrill Gorcunov { 788312136fSCyrill Gorcunov return smp_found_config && !disable_apic; 798312136fSCyrill Gorcunov } 808312136fSCyrill Gorcunov 818312136fSCyrill Gorcunov /* 82bb898558SAl Viro * Basic functions accessing APICs. 83bb898558SAl Viro */ 84bb898558SAl Viro #ifdef CONFIG_PARAVIRT 85bb898558SAl Viro #include <asm/paravirt.h> 86bb898558SAl Viro #endif 87bb898558SAl Viro 8870511134SRavikiran G Thirumalai #ifdef CONFIG_X86_64 89bb898558SAl Viro extern int is_vsmp_box(void); 90129d8bc8SYinghai Lu #else 91129d8bc8SYinghai Lu static inline int is_vsmp_box(void) 92129d8bc8SYinghai Lu { 93129d8bc8SYinghai Lu return 0; 94129d8bc8SYinghai Lu } 95129d8bc8SYinghai Lu #endif 96bb898558SAl Viro extern void xapic_wait_icr_idle(void); 97bb898558SAl Viro extern u32 safe_xapic_wait_icr_idle(void); 98bb898558SAl Viro extern void xapic_icr_write(u32, u32); 99bb898558SAl Viro extern int setup_profiling_timer(unsigned int); 100bb898558SAl Viro 101bb898558SAl Viro static inline void native_apic_mem_write(u32 reg, u32 v) 102bb898558SAl Viro { 103bb898558SAl Viro volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104bb898558SAl Viro 105bb898558SAl Viro alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 106bb898558SAl Viro ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107bb898558SAl Viro ASM_OUTPUT2("0" (v), "m" (*addr))); 108bb898558SAl Viro } 109bb898558SAl Viro 110bb898558SAl Viro static inline u32 native_apic_mem_read(u32 reg) 111bb898558SAl Viro { 112bb898558SAl Viro return *((volatile u32 *)(APIC_BASE + reg)); 113bb898558SAl Viro } 114bb898558SAl Viro 115c1eeb2deSYinghai Lu extern void native_apic_wait_icr_idle(void); 116c1eeb2deSYinghai Lu extern u32 native_safe_apic_wait_icr_idle(void); 117c1eeb2deSYinghai Lu extern void native_apic_icr_write(u32 low, u32 id); 118c1eeb2deSYinghai Lu extern u64 native_apic_icr_read(void); 119c1eeb2deSYinghai Lu 120fc1edaf9SSuresh Siddha extern int x2apic_mode; 121b24696bcSFenghua Yu 122d0b03bd1SHan, Weidong #ifdef CONFIG_X86_X2APIC 123ce4e240cSSuresh Siddha /* 124ce4e240cSSuresh Siddha * Make previous memory operations globally visible before 125ce4e240cSSuresh Siddha * sending the IPI through x2apic wrmsr. We need a serializing instruction or 126ce4e240cSSuresh Siddha * mfence for this. 127ce4e240cSSuresh Siddha */ 128ce4e240cSSuresh Siddha static inline void x2apic_wrmsr_fence(void) 129ce4e240cSSuresh Siddha { 130ce4e240cSSuresh Siddha asm volatile("mfence" : : : "memory"); 131ce4e240cSSuresh Siddha } 132ce4e240cSSuresh Siddha 133bb898558SAl Viro static inline void native_apic_msr_write(u32 reg, u32 v) 134bb898558SAl Viro { 135bb898558SAl Viro if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 136bb898558SAl Viro reg == APIC_LVR) 137bb898558SAl Viro return; 138bb898558SAl Viro 139bb898558SAl Viro wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 140bb898558SAl Viro } 141bb898558SAl Viro 142bb898558SAl Viro static inline u32 native_apic_msr_read(u32 reg) 143bb898558SAl Viro { 1440059b243SAndi Kleen u64 msr; 145bb898558SAl Viro 146bb898558SAl Viro if (reg == APIC_DFR) 147bb898558SAl Viro return -1; 148bb898558SAl Viro 1490059b243SAndi Kleen rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 1500059b243SAndi Kleen return (u32)msr; 151bb898558SAl Viro } 152bb898558SAl Viro 153c1eeb2deSYinghai Lu static inline void native_x2apic_wait_icr_idle(void) 154c1eeb2deSYinghai Lu { 155c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 156c1eeb2deSYinghai Lu return; 157c1eeb2deSYinghai Lu } 158c1eeb2deSYinghai Lu 159c1eeb2deSYinghai Lu static inline u32 native_safe_x2apic_wait_icr_idle(void) 160c1eeb2deSYinghai Lu { 161c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 162c1eeb2deSYinghai Lu return 0; 163c1eeb2deSYinghai Lu } 164c1eeb2deSYinghai Lu 165c1eeb2deSYinghai Lu static inline void native_x2apic_icr_write(u32 low, u32 id) 166c1eeb2deSYinghai Lu { 167c1eeb2deSYinghai Lu wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 168c1eeb2deSYinghai Lu } 169c1eeb2deSYinghai Lu 170c1eeb2deSYinghai Lu static inline u64 native_x2apic_icr_read(void) 171c1eeb2deSYinghai Lu { 172c1eeb2deSYinghai Lu unsigned long val; 173c1eeb2deSYinghai Lu 174c1eeb2deSYinghai Lu rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 175c1eeb2deSYinghai Lu return val; 176c1eeb2deSYinghai Lu } 177c1eeb2deSYinghai Lu 178fc1edaf9SSuresh Siddha extern int x2apic_phys; 179bb898558SAl Viro extern void check_x2apic(void); 180bb898558SAl Viro extern void enable_x2apic(void); 181bb898558SAl Viro extern void x2apic_icr_write(u32 low, u32 id); 182bb898558SAl Viro static inline int x2apic_enabled(void) 183bb898558SAl Viro { 1840059b243SAndi Kleen u64 msr; 185bb898558SAl Viro 186bb898558SAl Viro if (!cpu_has_x2apic) 187bb898558SAl Viro return 0; 188bb898558SAl Viro 1890059b243SAndi Kleen rdmsrl(MSR_IA32_APICBASE, msr); 190bb898558SAl Viro if (msr & X2APIC_ENABLE) 191bb898558SAl Viro return 1; 192bb898558SAl Viro return 0; 193bb898558SAl Viro } 194fc1edaf9SSuresh Siddha 195fc1edaf9SSuresh Siddha #define x2apic_supported() (cpu_has_x2apic) 196ce69a784SGleb Natapov static inline void x2apic_force_phys(void) 197ce69a784SGleb Natapov { 198ce69a784SGleb Natapov x2apic_phys = 1; 199ce69a784SGleb Natapov } 200bb898558SAl Viro #else 20106cd9a7dSYinghai Lu static inline void check_x2apic(void) 20206cd9a7dSYinghai Lu { 20306cd9a7dSYinghai Lu } 20406cd9a7dSYinghai Lu static inline void enable_x2apic(void) 20506cd9a7dSYinghai Lu { 20606cd9a7dSYinghai Lu } 20706cd9a7dSYinghai Lu static inline int x2apic_enabled(void) 20806cd9a7dSYinghai Lu { 20906cd9a7dSYinghai Lu return 0; 21006cd9a7dSYinghai Lu } 211ce69a784SGleb Natapov static inline void x2apic_force_phys(void) 212ce69a784SGleb Natapov { 213ce69a784SGleb Natapov } 214cf6567feSSuresh Siddha 21593758238SWeidong Han #define x2apic_preenabled 0 216fc1edaf9SSuresh Siddha #define x2apic_supported() 0 217bb898558SAl Viro #endif 218bb898558SAl Viro 21993758238SWeidong Han extern void enable_IR_x2apic(void); 22093758238SWeidong Han 221bb898558SAl Viro extern int get_physical_broadcast(void); 222bb898558SAl Viro 223bb898558SAl Viro extern int lapic_get_maxlvt(void); 224bb898558SAl Viro extern void clear_local_APIC(void); 225bb898558SAl Viro extern void connect_bsp_APIC(void); 226bb898558SAl Viro extern void disconnect_bsp_APIC(int virt_wire_setup); 227bb898558SAl Viro extern void disable_local_APIC(void); 228bb898558SAl Viro extern void lapic_shutdown(void); 229bb898558SAl Viro extern int verify_local_APIC(void); 230bb898558SAl Viro extern void sync_Arb_IDs(void); 231bb898558SAl Viro extern void init_bsp_APIC(void); 232bb898558SAl Viro extern void setup_local_APIC(void); 233bb898558SAl Viro extern void end_local_APIC_setup(void); 2342fb270f3SJan Beulich extern void bsp_end_local_APIC_setup(void); 235bb898558SAl Viro extern void init_apic_mappings(void); 236c0104d38SYinghai Lu void register_lapic_address(unsigned long address); 237bb898558SAl Viro extern void setup_boot_APIC_clock(void); 238bb898558SAl Viro extern void setup_secondary_APIC_clock(void); 239bb898558SAl Viro extern int APIC_init_uniprocessor(void); 240a906fdaaSThomas Gleixner extern int apic_force_enable(unsigned long addr); 241bb898558SAl Viro 242bb898558SAl Viro /* 243bb898558SAl Viro * On 32bit this is mach-xxx local 244bb898558SAl Viro */ 245bb898558SAl Viro #ifdef CONFIG_X86_64 246bb898558SAl Viro extern int apic_is_clustered_box(void); 247bb898558SAl Viro #else 248bb898558SAl Viro static inline int apic_is_clustered_box(void) 249bb898558SAl Viro { 250bb898558SAl Viro return 0; 251bb898558SAl Viro } 252bb898558SAl Viro #endif 253bb898558SAl Viro 25427afdf20SRobert Richter extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 255bb898558SAl Viro 256bb898558SAl Viro #else /* !CONFIG_X86_LOCAL_APIC */ 257bb898558SAl Viro static inline void lapic_shutdown(void) { } 258bb898558SAl Viro #define local_apic_timer_c2_ok 1 259bb898558SAl Viro static inline void init_apic_mappings(void) { } 260d3ec5caeSIvan Vecera static inline void disable_local_APIC(void) { } 261736decacSThomas Gleixner # define setup_boot_APIC_clock x86_init_noop 262736decacSThomas Gleixner # define setup_secondary_APIC_clock x86_init_noop 263bb898558SAl Viro #endif /* !CONFIG_X86_LOCAL_APIC */ 264bb898558SAl Viro 2651f75ed0cSIngo Molnar #ifdef CONFIG_X86_64 2661f75ed0cSIngo Molnar #define SET_APIC_ID(x) (apic->set_apic_id(x)) 2671f75ed0cSIngo Molnar #else 2681f75ed0cSIngo Molnar 2691f75ed0cSIngo Molnar #endif 2701f75ed0cSIngo Molnar 271e2780a68SIngo Molnar /* 272e2780a68SIngo Molnar * Copyright 2004 James Cleverdon, IBM. 273e2780a68SIngo Molnar * Subject to the GNU Public License, v.2 274e2780a68SIngo Molnar * 275e2780a68SIngo Molnar * Generic APIC sub-arch data struct. 276e2780a68SIngo Molnar * 277e2780a68SIngo Molnar * Hacked for x86-64 by James Cleverdon from i386 architecture code by 278e2780a68SIngo Molnar * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 279e2780a68SIngo Molnar * James Cleverdon. 280e2780a68SIngo Molnar */ 281be163a15SIngo Molnar struct apic { 282e2780a68SIngo Molnar char *name; 283e2780a68SIngo Molnar 284e2780a68SIngo Molnar int (*probe)(void); 285e2780a68SIngo Molnar int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 286e2780a68SIngo Molnar int (*apic_id_registered)(void); 287e2780a68SIngo Molnar 288e2780a68SIngo Molnar u32 irq_delivery_mode; 289e2780a68SIngo Molnar u32 irq_dest_mode; 290e2780a68SIngo Molnar 291e2780a68SIngo Molnar const struct cpumask *(*target_cpus)(void); 292e2780a68SIngo Molnar 293e2780a68SIngo Molnar int disable_esr; 294e2780a68SIngo Molnar 295e2780a68SIngo Molnar int dest_logical; 2967abc0753SCyrill Gorcunov unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 297e2780a68SIngo Molnar unsigned long (*check_apicid_present)(int apicid); 298e2780a68SIngo Molnar 299e2780a68SIngo Molnar void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 300e2780a68SIngo Molnar void (*init_apic_ldr)(void); 301e2780a68SIngo Molnar 3027abc0753SCyrill Gorcunov void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 303e2780a68SIngo Molnar 304e2780a68SIngo Molnar void (*setup_apic_routing)(void); 305e2780a68SIngo Molnar int (*multi_timer_check)(int apic, int irq); 306e2780a68SIngo Molnar int (*cpu_present_to_apicid)(int mps_cpu); 3077abc0753SCyrill Gorcunov void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 308e2780a68SIngo Molnar void (*setup_portio_remap)(void); 309e11dadabSThomas Gleixner int (*check_phys_apicid_present)(int phys_apicid); 310e2780a68SIngo Molnar void (*enable_apic_mode)(void); 311e2780a68SIngo Molnar int (*phys_pkg_id)(int cpuid_apic, int index_msb); 312e2780a68SIngo Molnar 313e2780a68SIngo Molnar /* 314be163a15SIngo Molnar * When one of the next two hooks returns 1 the apic 315e2780a68SIngo Molnar * is switched to this. Essentially they are additional 316e2780a68SIngo Molnar * probe functions: 317e2780a68SIngo Molnar */ 318e2780a68SIngo Molnar int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 319e2780a68SIngo Molnar 320e2780a68SIngo Molnar unsigned int (*get_apic_id)(unsigned long x); 321e2780a68SIngo Molnar unsigned long (*set_apic_id)(unsigned int id); 322e2780a68SIngo Molnar unsigned long apic_id_mask; 323e2780a68SIngo Molnar 324e2780a68SIngo Molnar unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 325e2780a68SIngo Molnar unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 326e2780a68SIngo Molnar const struct cpumask *andmask); 327e2780a68SIngo Molnar 328e2780a68SIngo Molnar /* ipi */ 329e2780a68SIngo Molnar void (*send_IPI_mask)(const struct cpumask *mask, int vector); 330e2780a68SIngo Molnar void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 331e2780a68SIngo Molnar int vector); 332e2780a68SIngo Molnar void (*send_IPI_allbutself)(int vector); 333e2780a68SIngo Molnar void (*send_IPI_all)(int vector); 334e2780a68SIngo Molnar void (*send_IPI_self)(int vector); 335e2780a68SIngo Molnar 336e2780a68SIngo Molnar /* wakeup_secondary_cpu */ 3371f5bcabfSIngo Molnar int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 338e2780a68SIngo Molnar 339e2780a68SIngo Molnar int trampoline_phys_low; 340e2780a68SIngo Molnar int trampoline_phys_high; 341e2780a68SIngo Molnar 342e2780a68SIngo Molnar void (*wait_for_init_deassert)(atomic_t *deassert); 343e2780a68SIngo Molnar void (*smp_callin_clear_local_apic)(void); 344e2780a68SIngo Molnar void (*inquire_remote_apic)(int apicid); 345e2780a68SIngo Molnar 346e2780a68SIngo Molnar /* apic ops */ 347e2780a68SIngo Molnar u32 (*read)(u32 reg); 348e2780a68SIngo Molnar void (*write)(u32 reg, u32 v); 349e2780a68SIngo Molnar u64 (*icr_read)(void); 350e2780a68SIngo Molnar void (*icr_write)(u32 low, u32 high); 351e2780a68SIngo Molnar void (*wait_icr_idle)(void); 352e2780a68SIngo Molnar u32 (*safe_wait_icr_idle)(void); 353acb8bc09STejun Heo 354acb8bc09STejun Heo #ifdef CONFIG_X86_32 355acb8bc09STejun Heo /* 356acb8bc09STejun Heo * Called very early during boot from get_smp_config(). It should 357acb8bc09STejun Heo * return the logical apicid. x86_[bios]_cpu_to_apicid is 358acb8bc09STejun Heo * initialized before this function is called. 359acb8bc09STejun Heo * 360acb8bc09STejun Heo * If logical apicid can't be determined that early, the function 361acb8bc09STejun Heo * may return BAD_APICID. Logical apicid will be configured after 362acb8bc09STejun Heo * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 363acb8bc09STejun Heo * won't be applied properly during early boot in this case. 364acb8bc09STejun Heo */ 365acb8bc09STejun Heo int (*x86_32_early_logical_apicid)(int cpu); 36689e5dc21STejun Heo 36784914ed0STejun Heo /* 36884914ed0STejun Heo * Optional method called from setup_local_APIC() after logical 36984914ed0STejun Heo * apicid is guaranteed to be known to initialize apicid -> node 37084914ed0STejun Heo * mapping if NUMA initialization hasn't done so already. Don't 37184914ed0STejun Heo * add new users. 37284914ed0STejun Heo */ 37389e5dc21STejun Heo int (*x86_32_numa_cpu_node)(int cpu); 374acb8bc09STejun Heo #endif 375e2780a68SIngo Molnar }; 376e2780a68SIngo Molnar 3770917c01fSIngo Molnar /* 3780917c01fSIngo Molnar * Pointer to the local APIC driver in use on this system (there's 3790917c01fSIngo Molnar * always just one such driver in use - the kernel decides via an 3800917c01fSIngo Molnar * early probing process which one it picks - and then sticks to it): 3810917c01fSIngo Molnar */ 382be163a15SIngo Molnar extern struct apic *apic; 3830917c01fSIngo Molnar 3840917c01fSIngo Molnar /* 385107e0e0cSSuresh Siddha * APIC drivers are probed based on how they are listed in the .apicdrivers 386107e0e0cSSuresh Siddha * section. So the order is important and enforced by the ordering 387107e0e0cSSuresh Siddha * of different apic driver files in the Makefile. 388107e0e0cSSuresh Siddha * 389107e0e0cSSuresh Siddha * For the files having two apic drivers, we use apic_drivers() 390107e0e0cSSuresh Siddha * to enforce the order with in them. 391107e0e0cSSuresh Siddha */ 392107e0e0cSSuresh Siddha #define apic_driver(sym) \ 393107e0e0cSSuresh Siddha static struct apic *__apicdrivers_##sym __used \ 394107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 395107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym } 396107e0e0cSSuresh Siddha 397107e0e0cSSuresh Siddha #define apic_drivers(sym1, sym2) \ 398107e0e0cSSuresh Siddha static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 399107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 400107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym1, &sym2 } 401107e0e0cSSuresh Siddha 402107e0e0cSSuresh Siddha extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 403107e0e0cSSuresh Siddha 404107e0e0cSSuresh Siddha /* 4050917c01fSIngo Molnar * APIC functionality to boot other CPUs - only used on SMP: 4060917c01fSIngo Molnar */ 4070917c01fSIngo Molnar #ifdef CONFIG_SMP 4082b6163bfSYinghai Lu extern atomic_t init_deasserted; 4092b6163bfSYinghai Lu extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 4100917c01fSIngo Molnar #endif 411e2780a68SIngo Molnar 412d674cd19SCyrill Gorcunov #ifdef CONFIG_X86_LOCAL_APIC 413346b46beSFernando Luis Vázquez Cao 414346b46beSFernando Luis Vázquez Cao DECLARE_PER_CPU(unsigned, icr_read_retry_count); 415346b46beSFernando Luis Vázquez Cao 416e2780a68SIngo Molnar static inline u32 apic_read(u32 reg) 417e2780a68SIngo Molnar { 418e2780a68SIngo Molnar return apic->read(reg); 419e2780a68SIngo Molnar } 420e2780a68SIngo Molnar 421e2780a68SIngo Molnar static inline void apic_write(u32 reg, u32 val) 422e2780a68SIngo Molnar { 423e2780a68SIngo Molnar apic->write(reg, val); 424e2780a68SIngo Molnar } 425e2780a68SIngo Molnar 426e2780a68SIngo Molnar static inline u64 apic_icr_read(void) 427e2780a68SIngo Molnar { 428e2780a68SIngo Molnar return apic->icr_read(); 429e2780a68SIngo Molnar } 430e2780a68SIngo Molnar 431e2780a68SIngo Molnar static inline void apic_icr_write(u32 low, u32 high) 432e2780a68SIngo Molnar { 433e2780a68SIngo Molnar apic->icr_write(low, high); 434e2780a68SIngo Molnar } 435e2780a68SIngo Molnar 436e2780a68SIngo Molnar static inline void apic_wait_icr_idle(void) 437e2780a68SIngo Molnar { 438e2780a68SIngo Molnar apic->wait_icr_idle(); 439e2780a68SIngo Molnar } 440e2780a68SIngo Molnar 441e2780a68SIngo Molnar static inline u32 safe_apic_wait_icr_idle(void) 442e2780a68SIngo Molnar { 443e2780a68SIngo Molnar return apic->safe_wait_icr_idle(); 444e2780a68SIngo Molnar } 445e2780a68SIngo Molnar 446d674cd19SCyrill Gorcunov #else /* CONFIG_X86_LOCAL_APIC */ 447d674cd19SCyrill Gorcunov 448d674cd19SCyrill Gorcunov static inline u32 apic_read(u32 reg) { return 0; } 449d674cd19SCyrill Gorcunov static inline void apic_write(u32 reg, u32 val) { } 450d674cd19SCyrill Gorcunov static inline u64 apic_icr_read(void) { return 0; } 451d674cd19SCyrill Gorcunov static inline void apic_icr_write(u32 low, u32 high) { } 452d674cd19SCyrill Gorcunov static inline void apic_wait_icr_idle(void) { } 453d674cd19SCyrill Gorcunov static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 454d674cd19SCyrill Gorcunov 455d674cd19SCyrill Gorcunov #endif /* CONFIG_X86_LOCAL_APIC */ 456e2780a68SIngo Molnar 457e2780a68SIngo Molnar static inline void ack_APIC_irq(void) 458e2780a68SIngo Molnar { 459e2780a68SIngo Molnar /* 460e2780a68SIngo Molnar * ack_APIC_irq() actually gets compiled as a single instruction 461e2780a68SIngo Molnar * ... yummie. 462e2780a68SIngo Molnar */ 463e2780a68SIngo Molnar 464e2780a68SIngo Molnar /* Docs say use 0 for future compatibility */ 465e2780a68SIngo Molnar apic_write(APIC_EOI, 0); 466e2780a68SIngo Molnar } 467e2780a68SIngo Molnar 468e2780a68SIngo Molnar static inline unsigned default_get_apic_id(unsigned long x) 469e2780a68SIngo Molnar { 470e2780a68SIngo Molnar unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 471e2780a68SIngo Molnar 47242937e81SAndreas Herrmann if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 473e2780a68SIngo Molnar return (x >> 24) & 0xFF; 474e2780a68SIngo Molnar else 475e2780a68SIngo Molnar return (x >> 24) & 0x0F; 476e2780a68SIngo Molnar } 477e2780a68SIngo Molnar 478e2780a68SIngo Molnar /* 479e2780a68SIngo Molnar * Warm reset vector default position: 480e2780a68SIngo Molnar */ 481e2780a68SIngo Molnar #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 482e2780a68SIngo Molnar #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 483e2780a68SIngo Molnar 4842b6163bfSYinghai Lu #ifdef CONFIG_X86_64 485e2780a68SIngo Molnar extern int default_acpi_madt_oem_check(char *, char *); 486e2780a68SIngo Molnar 487e2780a68SIngo Molnar extern void apic_send_IPI_self(int vector); 488e2780a68SIngo Molnar 489e2780a68SIngo Molnar DECLARE_PER_CPU(int, x2apic_extra_bits); 490e2780a68SIngo Molnar 491e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 492e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 493e2780a68SIngo Molnar #endif 494e2780a68SIngo Molnar 495e2780a68SIngo Molnar static inline void default_wait_for_init_deassert(atomic_t *deassert) 496e2780a68SIngo Molnar { 497e2780a68SIngo Molnar while (!atomic_read(deassert)) 498e2780a68SIngo Molnar cpu_relax(); 499e2780a68SIngo Molnar return; 500e2780a68SIngo Molnar } 501e2780a68SIngo Molnar 502838312beSJan Beulich extern void generic_bigsmp_probe(void); 503e2780a68SIngo Molnar 504e2780a68SIngo Molnar 505e2780a68SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 506e2780a68SIngo Molnar 507e2780a68SIngo Molnar #include <asm/smp.h> 508e2780a68SIngo Molnar 509e2780a68SIngo Molnar #define APIC_DFR_VALUE (APIC_DFR_FLAT) 510e2780a68SIngo Molnar 511e2780a68SIngo Molnar static inline const struct cpumask *default_target_cpus(void) 512e2780a68SIngo Molnar { 513e2780a68SIngo Molnar #ifdef CONFIG_SMP 514e2780a68SIngo Molnar return cpu_online_mask; 515e2780a68SIngo Molnar #else 516e2780a68SIngo Molnar return cpumask_of(0); 517e2780a68SIngo Molnar #endif 518e2780a68SIngo Molnar } 519e2780a68SIngo Molnar 520e2780a68SIngo Molnar DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 521e2780a68SIngo Molnar 522e2780a68SIngo Molnar 523e2780a68SIngo Molnar static inline unsigned int read_apic_id(void) 524e2780a68SIngo Molnar { 525e2780a68SIngo Molnar unsigned int reg; 526e2780a68SIngo Molnar 527e2780a68SIngo Molnar reg = apic_read(APIC_ID); 528e2780a68SIngo Molnar 529e2780a68SIngo Molnar return apic->get_apic_id(reg); 530e2780a68SIngo Molnar } 531e2780a68SIngo Molnar 532e2780a68SIngo Molnar extern void default_setup_apic_routing(void); 533e2780a68SIngo Molnar 5349844ab11SCyrill Gorcunov extern struct apic apic_noop; 5359844ab11SCyrill Gorcunov 536e2780a68SIngo Molnar #ifdef CONFIG_X86_32 5372c1b284eSJaswinder Singh Rajput 538acb8bc09STejun Heo static inline int noop_x86_32_early_logical_apicid(int cpu) 539acb8bc09STejun Heo { 540acb8bc09STejun Heo return BAD_APICID; 541acb8bc09STejun Heo } 542acb8bc09STejun Heo 543e2780a68SIngo Molnar /* 544e2780a68SIngo Molnar * Set up the logical destination ID. 545e2780a68SIngo Molnar * 546e2780a68SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 547e2780a68SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 548e2780a68SIngo Molnar * document number 292116). So here it goes... 549e2780a68SIngo Molnar */ 550e2780a68SIngo Molnar extern void default_init_apic_ldr(void); 551e2780a68SIngo Molnar 552e2780a68SIngo Molnar static inline int default_apic_id_registered(void) 553e2780a68SIngo Molnar { 554e2780a68SIngo Molnar return physid_isset(read_apic_id(), phys_cpu_present_map); 555e2780a68SIngo Molnar } 556e2780a68SIngo Molnar 557f56e5034SYinghai Lu static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 558f56e5034SYinghai Lu { 559f56e5034SYinghai Lu return cpuid_apic >> index_msb; 560f56e5034SYinghai Lu } 561f56e5034SYinghai Lu 562f56e5034SYinghai Lu #endif 563f56e5034SYinghai Lu 564e2780a68SIngo Molnar static inline unsigned int 565e2780a68SIngo Molnar default_cpu_mask_to_apicid(const struct cpumask *cpumask) 566e2780a68SIngo Molnar { 567f56e5034SYinghai Lu return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 568e2780a68SIngo Molnar } 569e2780a68SIngo Molnar 570e2780a68SIngo Molnar static inline unsigned int 571e2780a68SIngo Molnar default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 572e2780a68SIngo Molnar const struct cpumask *andmask) 573e2780a68SIngo Molnar { 574e2780a68SIngo Molnar unsigned long mask1 = cpumask_bits(cpumask)[0]; 575e2780a68SIngo Molnar unsigned long mask2 = cpumask_bits(andmask)[0]; 576e2780a68SIngo Molnar unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 577e2780a68SIngo Molnar 578e2780a68SIngo Molnar return (unsigned int)(mask1 & mask2 & mask3); 579e2780a68SIngo Molnar } 580e2780a68SIngo Molnar 5817abc0753SCyrill Gorcunov static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 582e2780a68SIngo Molnar { 5837abc0753SCyrill Gorcunov return physid_isset(apicid, *map); 584e2780a68SIngo Molnar } 585e2780a68SIngo Molnar 586e2780a68SIngo Molnar static inline unsigned long default_check_apicid_present(int bit) 587e2780a68SIngo Molnar { 588e2780a68SIngo Molnar return physid_isset(bit, phys_cpu_present_map); 589e2780a68SIngo Molnar } 590e2780a68SIngo Molnar 5917abc0753SCyrill Gorcunov static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 592e2780a68SIngo Molnar { 5937abc0753SCyrill Gorcunov *retmap = *phys_map; 594e2780a68SIngo Molnar } 595e2780a68SIngo Molnar 596e2780a68SIngo Molnar static inline int __default_cpu_present_to_apicid(int mps_cpu) 597e2780a68SIngo Molnar { 598e2780a68SIngo Molnar if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 599e2780a68SIngo Molnar return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 600e2780a68SIngo Molnar else 601e2780a68SIngo Molnar return BAD_APICID; 602e2780a68SIngo Molnar } 603e2780a68SIngo Molnar 604e2780a68SIngo Molnar static inline int 605e11dadabSThomas Gleixner __default_check_phys_apicid_present(int phys_apicid) 606e2780a68SIngo Molnar { 607e11dadabSThomas Gleixner return physid_isset(phys_apicid, phys_cpu_present_map); 608e2780a68SIngo Molnar } 609e2780a68SIngo Molnar 610e2780a68SIngo Molnar #ifdef CONFIG_X86_32 611e2780a68SIngo Molnar static inline int default_cpu_present_to_apicid(int mps_cpu) 612e2780a68SIngo Molnar { 613e2780a68SIngo Molnar return __default_cpu_present_to_apicid(mps_cpu); 614e2780a68SIngo Molnar } 615e2780a68SIngo Molnar 616e2780a68SIngo Molnar static inline int 617e11dadabSThomas Gleixner default_check_phys_apicid_present(int phys_apicid) 618e2780a68SIngo Molnar { 619e11dadabSThomas Gleixner return __default_check_phys_apicid_present(phys_apicid); 620e2780a68SIngo Molnar } 621e2780a68SIngo Molnar #else 622e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 623e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 624e2780a68SIngo Molnar #endif 625e2780a68SIngo Molnar 626e2780a68SIngo Molnar #endif /* CONFIG_X86_LOCAL_APIC */ 627e2780a68SIngo Molnar 6281965aae3SH. Peter Anvin #endif /* _ASM_X86_APIC_H */ 629