11965aae3SH. Peter Anvin #ifndef _ASM_X86_APIC_H 21965aae3SH. Peter Anvin #define _ASM_X86_APIC_H 3bb898558SAl Viro 4e2780a68SIngo Molnar #include <linux/cpumask.h> 5e2780a68SIngo Molnar #include <linux/pm.h> 6bb898558SAl Viro 7bb898558SAl Viro #include <asm/alternative.h> 8bb898558SAl Viro #include <asm/cpufeature.h> 9e2780a68SIngo Molnar #include <asm/processor.h> 10e2780a68SIngo Molnar #include <asm/apicdef.h> 1160063497SArun Sharma #include <linux/atomic.h> 12e2780a68SIngo Molnar #include <asm/fixmap.h> 13e2780a68SIngo Molnar #include <asm/mpspec.h> 14bb898558SAl Viro #include <asm/msr.h> 15eddc0e92SSeiji Aguchi #include <asm/idle.h> 16bb898558SAl Viro 17bb898558SAl Viro #define ARCH_APICTIMER_STOPS_ON_C3 1 18bb898558SAl Viro 19bb898558SAl Viro /* 20bb898558SAl Viro * Debugging macros 21bb898558SAl Viro */ 22bb898558SAl Viro #define APIC_QUIET 0 23bb898558SAl Viro #define APIC_VERBOSE 1 24bb898558SAl Viro #define APIC_DEBUG 2 25bb898558SAl Viro 26bb898558SAl Viro /* 27bb898558SAl Viro * Define the default level of output to be very little 28bb898558SAl Viro * This can be turned up by using apic=verbose for more 29bb898558SAl Viro * information and apic=debug for _lots_ of information. 30bb898558SAl Viro * apic_verbosity is defined in apic.c 31bb898558SAl Viro */ 32bb898558SAl Viro #define apic_printk(v, s, a...) do { \ 33bb898558SAl Viro if ((v) <= apic_verbosity) \ 34bb898558SAl Viro printk(s, ##a); \ 35bb898558SAl Viro } while (0) 36bb898558SAl Viro 37bb898558SAl Viro 38160d8dacSIngo Molnar #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39bb898558SAl Viro extern void generic_apic_probe(void); 40160d8dacSIngo Molnar #else 41160d8dacSIngo Molnar static inline void generic_apic_probe(void) 42160d8dacSIngo Molnar { 43160d8dacSIngo Molnar } 44160d8dacSIngo Molnar #endif 45bb898558SAl Viro 46bb898558SAl Viro #ifdef CONFIG_X86_LOCAL_APIC 47bb898558SAl Viro 48bb898558SAl Viro extern unsigned int apic_verbosity; 49bb898558SAl Viro extern int local_apic_timer_c2_ok; 50bb898558SAl Viro 51bb898558SAl Viro extern int disable_apic; 521ade93efSJacob Pan extern unsigned int lapic_timer_frequency; 530939e4fdSIngo Molnar 540939e4fdSIngo Molnar #ifdef CONFIG_SMP 550939e4fdSIngo Molnar extern void __inquire_remote_apic(int apicid); 560939e4fdSIngo Molnar #else /* CONFIG_SMP */ 570939e4fdSIngo Molnar static inline void __inquire_remote_apic(int apicid) 580939e4fdSIngo Molnar { 590939e4fdSIngo Molnar } 600939e4fdSIngo Molnar #endif /* CONFIG_SMP */ 610939e4fdSIngo Molnar 620939e4fdSIngo Molnar static inline void default_inquire_remote_apic(int apicid) 630939e4fdSIngo Molnar { 640939e4fdSIngo Molnar if (apic_verbosity >= APIC_DEBUG) 650939e4fdSIngo Molnar __inquire_remote_apic(apicid); 660939e4fdSIngo Molnar } 670939e4fdSIngo Molnar 68bb898558SAl Viro /* 698312136fSCyrill Gorcunov * With 82489DX we can't rely on apic feature bit 708312136fSCyrill Gorcunov * retrieved via cpuid but still have to deal with 718312136fSCyrill Gorcunov * such an apic chip so we assume that SMP configuration 728312136fSCyrill Gorcunov * is found from MP table (64bit case uses ACPI mostly 738312136fSCyrill Gorcunov * which set smp presence flag as well so we are safe 748312136fSCyrill Gorcunov * to use this helper too). 758312136fSCyrill Gorcunov */ 768312136fSCyrill Gorcunov static inline bool apic_from_smp_config(void) 778312136fSCyrill Gorcunov { 788312136fSCyrill Gorcunov return smp_found_config && !disable_apic; 798312136fSCyrill Gorcunov } 808312136fSCyrill Gorcunov 818312136fSCyrill Gorcunov /* 82bb898558SAl Viro * Basic functions accessing APICs. 83bb898558SAl Viro */ 84bb898558SAl Viro #ifdef CONFIG_PARAVIRT 85bb898558SAl Viro #include <asm/paravirt.h> 86bb898558SAl Viro #endif 87bb898558SAl Viro 8870511134SRavikiran G Thirumalai #ifdef CONFIG_X86_64 89bb898558SAl Viro extern int is_vsmp_box(void); 90129d8bc8SYinghai Lu #else 91129d8bc8SYinghai Lu static inline int is_vsmp_box(void) 92129d8bc8SYinghai Lu { 93129d8bc8SYinghai Lu return 0; 94129d8bc8SYinghai Lu } 95129d8bc8SYinghai Lu #endif 96bb898558SAl Viro extern void xapic_wait_icr_idle(void); 97bb898558SAl Viro extern u32 safe_xapic_wait_icr_idle(void); 98bb898558SAl Viro extern void xapic_icr_write(u32, u32); 99bb898558SAl Viro extern int setup_profiling_timer(unsigned int); 100bb898558SAl Viro 101bb898558SAl Viro static inline void native_apic_mem_write(u32 reg, u32 v) 102bb898558SAl Viro { 103bb898558SAl Viro volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104bb898558SAl Viro 105bb898558SAl Viro alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 106bb898558SAl Viro ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107bb898558SAl Viro ASM_OUTPUT2("0" (v), "m" (*addr))); 108bb898558SAl Viro } 109bb898558SAl Viro 110bb898558SAl Viro static inline u32 native_apic_mem_read(u32 reg) 111bb898558SAl Viro { 112bb898558SAl Viro return *((volatile u32 *)(APIC_BASE + reg)); 113bb898558SAl Viro } 114bb898558SAl Viro 115c1eeb2deSYinghai Lu extern void native_apic_wait_icr_idle(void); 116c1eeb2deSYinghai Lu extern u32 native_safe_apic_wait_icr_idle(void); 117c1eeb2deSYinghai Lu extern void native_apic_icr_write(u32 low, u32 id); 118c1eeb2deSYinghai Lu extern u64 native_apic_icr_read(void); 119c1eeb2deSYinghai Lu 120fc1edaf9SSuresh Siddha extern int x2apic_mode; 121b24696bcSFenghua Yu 122d0b03bd1SHan, Weidong #ifdef CONFIG_X86_X2APIC 123ce4e240cSSuresh Siddha /* 124ce4e240cSSuresh Siddha * Make previous memory operations globally visible before 125ce4e240cSSuresh Siddha * sending the IPI through x2apic wrmsr. We need a serializing instruction or 126ce4e240cSSuresh Siddha * mfence for this. 127ce4e240cSSuresh Siddha */ 128ce4e240cSSuresh Siddha static inline void x2apic_wrmsr_fence(void) 129ce4e240cSSuresh Siddha { 130ce4e240cSSuresh Siddha asm volatile("mfence" : : : "memory"); 131ce4e240cSSuresh Siddha } 132ce4e240cSSuresh Siddha 133bb898558SAl Viro static inline void native_apic_msr_write(u32 reg, u32 v) 134bb898558SAl Viro { 135bb898558SAl Viro if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 136bb898558SAl Viro reg == APIC_LVR) 137bb898558SAl Viro return; 138bb898558SAl Viro 139bb898558SAl Viro wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 140bb898558SAl Viro } 141bb898558SAl Viro 1420ab711aeSMichael S. Tsirkin static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 1430ab711aeSMichael S. Tsirkin { 1440ab711aeSMichael S. Tsirkin wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 1450ab711aeSMichael S. Tsirkin } 1460ab711aeSMichael S. Tsirkin 147bb898558SAl Viro static inline u32 native_apic_msr_read(u32 reg) 148bb898558SAl Viro { 1490059b243SAndi Kleen u64 msr; 150bb898558SAl Viro 151bb898558SAl Viro if (reg == APIC_DFR) 152bb898558SAl Viro return -1; 153bb898558SAl Viro 1540059b243SAndi Kleen rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 1550059b243SAndi Kleen return (u32)msr; 156bb898558SAl Viro } 157bb898558SAl Viro 158c1eeb2deSYinghai Lu static inline void native_x2apic_wait_icr_idle(void) 159c1eeb2deSYinghai Lu { 160c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 161c1eeb2deSYinghai Lu return; 162c1eeb2deSYinghai Lu } 163c1eeb2deSYinghai Lu 164c1eeb2deSYinghai Lu static inline u32 native_safe_x2apic_wait_icr_idle(void) 165c1eeb2deSYinghai Lu { 166c1eeb2deSYinghai Lu /* no need to wait for icr idle in x2apic */ 167c1eeb2deSYinghai Lu return 0; 168c1eeb2deSYinghai Lu } 169c1eeb2deSYinghai Lu 170c1eeb2deSYinghai Lu static inline void native_x2apic_icr_write(u32 low, u32 id) 171c1eeb2deSYinghai Lu { 172c1eeb2deSYinghai Lu wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 173c1eeb2deSYinghai Lu } 174c1eeb2deSYinghai Lu 175c1eeb2deSYinghai Lu static inline u64 native_x2apic_icr_read(void) 176c1eeb2deSYinghai Lu { 177c1eeb2deSYinghai Lu unsigned long val; 178c1eeb2deSYinghai Lu 179c1eeb2deSYinghai Lu rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 180c1eeb2deSYinghai Lu return val; 181c1eeb2deSYinghai Lu } 182c1eeb2deSYinghai Lu 183fc1edaf9SSuresh Siddha extern int x2apic_phys; 184fb209bd8SYinghai Lu extern int x2apic_preenabled; 185bb898558SAl Viro extern void check_x2apic(void); 186bb898558SAl Viro extern void enable_x2apic(void); 187bb898558SAl Viro extern void x2apic_icr_write(u32 low, u32 id); 188bb898558SAl Viro static inline int x2apic_enabled(void) 189bb898558SAl Viro { 1900059b243SAndi Kleen u64 msr; 191bb898558SAl Viro 192bb898558SAl Viro if (!cpu_has_x2apic) 193bb898558SAl Viro return 0; 194bb898558SAl Viro 1950059b243SAndi Kleen rdmsrl(MSR_IA32_APICBASE, msr); 196bb898558SAl Viro if (msr & X2APIC_ENABLE) 197bb898558SAl Viro return 1; 198bb898558SAl Viro return 0; 199bb898558SAl Viro } 200fc1edaf9SSuresh Siddha 201fc1edaf9SSuresh Siddha #define x2apic_supported() (cpu_has_x2apic) 202ce69a784SGleb Natapov static inline void x2apic_force_phys(void) 203ce69a784SGleb Natapov { 204ce69a784SGleb Natapov x2apic_phys = 1; 205ce69a784SGleb Natapov } 206bb898558SAl Viro #else 207fb209bd8SYinghai Lu static inline void disable_x2apic(void) 208fb209bd8SYinghai Lu { 209fb209bd8SYinghai Lu } 21006cd9a7dSYinghai Lu static inline void check_x2apic(void) 21106cd9a7dSYinghai Lu { 21206cd9a7dSYinghai Lu } 21306cd9a7dSYinghai Lu static inline void enable_x2apic(void) 21406cd9a7dSYinghai Lu { 21506cd9a7dSYinghai Lu } 21606cd9a7dSYinghai Lu static inline int x2apic_enabled(void) 21706cd9a7dSYinghai Lu { 21806cd9a7dSYinghai Lu return 0; 21906cd9a7dSYinghai Lu } 220ce69a784SGleb Natapov static inline void x2apic_force_phys(void) 221ce69a784SGleb Natapov { 222ce69a784SGleb Natapov } 223cf6567feSSuresh Siddha 224a31bc327SYinghai Lu #define nox2apic 0 22593758238SWeidong Han #define x2apic_preenabled 0 226fc1edaf9SSuresh Siddha #define x2apic_supported() 0 227bb898558SAl Viro #endif 228bb898558SAl Viro 22993758238SWeidong Han extern void enable_IR_x2apic(void); 23093758238SWeidong Han 231bb898558SAl Viro extern int get_physical_broadcast(void); 232bb898558SAl Viro 233bb898558SAl Viro extern int lapic_get_maxlvt(void); 234bb898558SAl Viro extern void clear_local_APIC(void); 235bb898558SAl Viro extern void connect_bsp_APIC(void); 236bb898558SAl Viro extern void disconnect_bsp_APIC(int virt_wire_setup); 237bb898558SAl Viro extern void disable_local_APIC(void); 238bb898558SAl Viro extern void lapic_shutdown(void); 239bb898558SAl Viro extern int verify_local_APIC(void); 240bb898558SAl Viro extern void sync_Arb_IDs(void); 241bb898558SAl Viro extern void init_bsp_APIC(void); 242bb898558SAl Viro extern void setup_local_APIC(void); 243bb898558SAl Viro extern void end_local_APIC_setup(void); 2442fb270f3SJan Beulich extern void bsp_end_local_APIC_setup(void); 245bb898558SAl Viro extern void init_apic_mappings(void); 246c0104d38SYinghai Lu void register_lapic_address(unsigned long address); 247bb898558SAl Viro extern void setup_boot_APIC_clock(void); 248bb898558SAl Viro extern void setup_secondary_APIC_clock(void); 249bb898558SAl Viro extern int APIC_init_uniprocessor(void); 250a906fdaaSThomas Gleixner extern int apic_force_enable(unsigned long addr); 251bb898558SAl Viro 252bb898558SAl Viro /* 253bb898558SAl Viro * On 32bit this is mach-xxx local 254bb898558SAl Viro */ 255bb898558SAl Viro #ifdef CONFIG_X86_64 256bb898558SAl Viro extern int apic_is_clustered_box(void); 257bb898558SAl Viro #else 258bb898558SAl Viro static inline int apic_is_clustered_box(void) 259bb898558SAl Viro { 260bb898558SAl Viro return 0; 261bb898558SAl Viro } 262bb898558SAl Viro #endif 263bb898558SAl Viro 26427afdf20SRobert Richter extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 265bb898558SAl Viro 266bb898558SAl Viro #else /* !CONFIG_X86_LOCAL_APIC */ 267bb898558SAl Viro static inline void lapic_shutdown(void) { } 268bb898558SAl Viro #define local_apic_timer_c2_ok 1 269bb898558SAl Viro static inline void init_apic_mappings(void) { } 270d3ec5caeSIvan Vecera static inline void disable_local_APIC(void) { } 271736decacSThomas Gleixner # define setup_boot_APIC_clock x86_init_noop 272736decacSThomas Gleixner # define setup_secondary_APIC_clock x86_init_noop 273bb898558SAl Viro #endif /* !CONFIG_X86_LOCAL_APIC */ 274bb898558SAl Viro 2751f75ed0cSIngo Molnar #ifdef CONFIG_X86_64 2761f75ed0cSIngo Molnar #define SET_APIC_ID(x) (apic->set_apic_id(x)) 2771f75ed0cSIngo Molnar #else 2781f75ed0cSIngo Molnar 2791f75ed0cSIngo Molnar #endif 2801f75ed0cSIngo Molnar 281e2780a68SIngo Molnar /* 282e2780a68SIngo Molnar * Copyright 2004 James Cleverdon, IBM. 283e2780a68SIngo Molnar * Subject to the GNU Public License, v.2 284e2780a68SIngo Molnar * 285e2780a68SIngo Molnar * Generic APIC sub-arch data struct. 286e2780a68SIngo Molnar * 287e2780a68SIngo Molnar * Hacked for x86-64 by James Cleverdon from i386 architecture code by 288e2780a68SIngo Molnar * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 289e2780a68SIngo Molnar * James Cleverdon. 290e2780a68SIngo Molnar */ 291be163a15SIngo Molnar struct apic { 292e2780a68SIngo Molnar char *name; 293e2780a68SIngo Molnar 294e2780a68SIngo Molnar int (*probe)(void); 295e2780a68SIngo Molnar int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 296fa63030eSDaniel J Blueman int (*apic_id_valid)(int apicid); 297e2780a68SIngo Molnar int (*apic_id_registered)(void); 298e2780a68SIngo Molnar 299e2780a68SIngo Molnar u32 irq_delivery_mode; 300e2780a68SIngo Molnar u32 irq_dest_mode; 301e2780a68SIngo Molnar 302e2780a68SIngo Molnar const struct cpumask *(*target_cpus)(void); 303e2780a68SIngo Molnar 304e2780a68SIngo Molnar int disable_esr; 305e2780a68SIngo Molnar 306e2780a68SIngo Molnar int dest_logical; 3077abc0753SCyrill Gorcunov unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 308e2780a68SIngo Molnar unsigned long (*check_apicid_present)(int apicid); 309e2780a68SIngo Molnar 3101ac322d0SSuresh Siddha void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 3111ac322d0SSuresh Siddha const struct cpumask *mask); 312e2780a68SIngo Molnar void (*init_apic_ldr)(void); 313e2780a68SIngo Molnar 3147abc0753SCyrill Gorcunov void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 315e2780a68SIngo Molnar 316e2780a68SIngo Molnar void (*setup_apic_routing)(void); 317e2780a68SIngo Molnar int (*multi_timer_check)(int apic, int irq); 318e2780a68SIngo Molnar int (*cpu_present_to_apicid)(int mps_cpu); 3197abc0753SCyrill Gorcunov void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 320e2780a68SIngo Molnar void (*setup_portio_remap)(void); 321e11dadabSThomas Gleixner int (*check_phys_apicid_present)(int phys_apicid); 322e2780a68SIngo Molnar void (*enable_apic_mode)(void); 323e2780a68SIngo Molnar int (*phys_pkg_id)(int cpuid_apic, int index_msb); 324e2780a68SIngo Molnar 325e2780a68SIngo Molnar /* 326be163a15SIngo Molnar * When one of the next two hooks returns 1 the apic 327e2780a68SIngo Molnar * is switched to this. Essentially they are additional 328e2780a68SIngo Molnar * probe functions: 329e2780a68SIngo Molnar */ 330e2780a68SIngo Molnar int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 331e2780a68SIngo Molnar 332e2780a68SIngo Molnar unsigned int (*get_apic_id)(unsigned long x); 333e2780a68SIngo Molnar unsigned long (*set_apic_id)(unsigned int id); 334e2780a68SIngo Molnar unsigned long apic_id_mask; 335e2780a68SIngo Molnar 336ff164324SAlexander Gordeev int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 337ff164324SAlexander Gordeev const struct cpumask *andmask, 338ff164324SAlexander Gordeev unsigned int *apicid); 339e2780a68SIngo Molnar 340e2780a68SIngo Molnar /* ipi */ 341e2780a68SIngo Molnar void (*send_IPI_mask)(const struct cpumask *mask, int vector); 342e2780a68SIngo Molnar void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 343e2780a68SIngo Molnar int vector); 344e2780a68SIngo Molnar void (*send_IPI_allbutself)(int vector); 345e2780a68SIngo Molnar void (*send_IPI_all)(int vector); 346e2780a68SIngo Molnar void (*send_IPI_self)(int vector); 347e2780a68SIngo Molnar 348e2780a68SIngo Molnar /* wakeup_secondary_cpu */ 3491f5bcabfSIngo Molnar int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 350e2780a68SIngo Molnar 351e2780a68SIngo Molnar int trampoline_phys_low; 352e2780a68SIngo Molnar int trampoline_phys_high; 353e2780a68SIngo Molnar 354e2780a68SIngo Molnar void (*wait_for_init_deassert)(atomic_t *deassert); 355e2780a68SIngo Molnar void (*smp_callin_clear_local_apic)(void); 356e2780a68SIngo Molnar void (*inquire_remote_apic)(int apicid); 357e2780a68SIngo Molnar 358e2780a68SIngo Molnar /* apic ops */ 359e2780a68SIngo Molnar u32 (*read)(u32 reg); 360e2780a68SIngo Molnar void (*write)(u32 reg, u32 v); 3612a43195dSMichael S. Tsirkin /* 3622a43195dSMichael S. Tsirkin * ->eoi_write() has the same signature as ->write(). 3632a43195dSMichael S. Tsirkin * 3642a43195dSMichael S. Tsirkin * Drivers can support both ->eoi_write() and ->write() by passing the same 3652a43195dSMichael S. Tsirkin * callback value. Kernel can override ->eoi_write() and fall back 3662a43195dSMichael S. Tsirkin * on write for EOI. 3672a43195dSMichael S. Tsirkin */ 3682a43195dSMichael S. Tsirkin void (*eoi_write)(u32 reg, u32 v); 369e2780a68SIngo Molnar u64 (*icr_read)(void); 370e2780a68SIngo Molnar void (*icr_write)(u32 low, u32 high); 371e2780a68SIngo Molnar void (*wait_icr_idle)(void); 372e2780a68SIngo Molnar u32 (*safe_wait_icr_idle)(void); 373acb8bc09STejun Heo 374acb8bc09STejun Heo #ifdef CONFIG_X86_32 375acb8bc09STejun Heo /* 376acb8bc09STejun Heo * Called very early during boot from get_smp_config(). It should 377acb8bc09STejun Heo * return the logical apicid. x86_[bios]_cpu_to_apicid is 378acb8bc09STejun Heo * initialized before this function is called. 379acb8bc09STejun Heo * 380acb8bc09STejun Heo * If logical apicid can't be determined that early, the function 381acb8bc09STejun Heo * may return BAD_APICID. Logical apicid will be configured after 382acb8bc09STejun Heo * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 383acb8bc09STejun Heo * won't be applied properly during early boot in this case. 384acb8bc09STejun Heo */ 385acb8bc09STejun Heo int (*x86_32_early_logical_apicid)(int cpu); 38689e5dc21STejun Heo 38784914ed0STejun Heo /* 38884914ed0STejun Heo * Optional method called from setup_local_APIC() after logical 38984914ed0STejun Heo * apicid is guaranteed to be known to initialize apicid -> node 39084914ed0STejun Heo * mapping if NUMA initialization hasn't done so already. Don't 39184914ed0STejun Heo * add new users. 39284914ed0STejun Heo */ 39389e5dc21STejun Heo int (*x86_32_numa_cpu_node)(int cpu); 394acb8bc09STejun Heo #endif 395e2780a68SIngo Molnar }; 396e2780a68SIngo Molnar 3970917c01fSIngo Molnar /* 3980917c01fSIngo Molnar * Pointer to the local APIC driver in use on this system (there's 3990917c01fSIngo Molnar * always just one such driver in use - the kernel decides via an 4000917c01fSIngo Molnar * early probing process which one it picks - and then sticks to it): 4010917c01fSIngo Molnar */ 402be163a15SIngo Molnar extern struct apic *apic; 4030917c01fSIngo Molnar 4040917c01fSIngo Molnar /* 405107e0e0cSSuresh Siddha * APIC drivers are probed based on how they are listed in the .apicdrivers 406107e0e0cSSuresh Siddha * section. So the order is important and enforced by the ordering 407107e0e0cSSuresh Siddha * of different apic driver files in the Makefile. 408107e0e0cSSuresh Siddha * 409107e0e0cSSuresh Siddha * For the files having two apic drivers, we use apic_drivers() 410107e0e0cSSuresh Siddha * to enforce the order with in them. 411107e0e0cSSuresh Siddha */ 412107e0e0cSSuresh Siddha #define apic_driver(sym) \ 41375fdd155SAndi Kleen static const struct apic *__apicdrivers_##sym __used \ 414107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 415107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym } 416107e0e0cSSuresh Siddha 417107e0e0cSSuresh Siddha #define apic_drivers(sym1, sym2) \ 418107e0e0cSSuresh Siddha static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 419107e0e0cSSuresh Siddha __aligned(sizeof(struct apic *)) \ 420107e0e0cSSuresh Siddha __section(.apicdrivers) = { &sym1, &sym2 } 421107e0e0cSSuresh Siddha 422107e0e0cSSuresh Siddha extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 423107e0e0cSSuresh Siddha 424107e0e0cSSuresh Siddha /* 4250917c01fSIngo Molnar * APIC functionality to boot other CPUs - only used on SMP: 4260917c01fSIngo Molnar */ 4270917c01fSIngo Molnar #ifdef CONFIG_SMP 4282b6163bfSYinghai Lu extern atomic_t init_deasserted; 4292b6163bfSYinghai Lu extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 4300917c01fSIngo Molnar #endif 431e2780a68SIngo Molnar 432d674cd19SCyrill Gorcunov #ifdef CONFIG_X86_LOCAL_APIC 433346b46beSFernando Luis Vázquez Cao 434e2780a68SIngo Molnar static inline u32 apic_read(u32 reg) 435e2780a68SIngo Molnar { 436e2780a68SIngo Molnar return apic->read(reg); 437e2780a68SIngo Molnar } 438e2780a68SIngo Molnar 439e2780a68SIngo Molnar static inline void apic_write(u32 reg, u32 val) 440e2780a68SIngo Molnar { 441e2780a68SIngo Molnar apic->write(reg, val); 442e2780a68SIngo Molnar } 443e2780a68SIngo Molnar 4442a43195dSMichael S. Tsirkin static inline void apic_eoi(void) 4452a43195dSMichael S. Tsirkin { 4462a43195dSMichael S. Tsirkin apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 4472a43195dSMichael S. Tsirkin } 4482a43195dSMichael S. Tsirkin 449e2780a68SIngo Molnar static inline u64 apic_icr_read(void) 450e2780a68SIngo Molnar { 451e2780a68SIngo Molnar return apic->icr_read(); 452e2780a68SIngo Molnar } 453e2780a68SIngo Molnar 454e2780a68SIngo Molnar static inline void apic_icr_write(u32 low, u32 high) 455e2780a68SIngo Molnar { 456e2780a68SIngo Molnar apic->icr_write(low, high); 457e2780a68SIngo Molnar } 458e2780a68SIngo Molnar 459e2780a68SIngo Molnar static inline void apic_wait_icr_idle(void) 460e2780a68SIngo Molnar { 461e2780a68SIngo Molnar apic->wait_icr_idle(); 462e2780a68SIngo Molnar } 463e2780a68SIngo Molnar 464e2780a68SIngo Molnar static inline u32 safe_apic_wait_icr_idle(void) 465e2780a68SIngo Molnar { 466e2780a68SIngo Molnar return apic->safe_wait_icr_idle(); 467e2780a68SIngo Molnar } 468e2780a68SIngo Molnar 4691551df64SMichael S. Tsirkin extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 4701551df64SMichael S. Tsirkin 471d674cd19SCyrill Gorcunov #else /* CONFIG_X86_LOCAL_APIC */ 472d674cd19SCyrill Gorcunov 473d674cd19SCyrill Gorcunov static inline u32 apic_read(u32 reg) { return 0; } 474d674cd19SCyrill Gorcunov static inline void apic_write(u32 reg, u32 val) { } 4752a43195dSMichael S. Tsirkin static inline void apic_eoi(void) { } 476d674cd19SCyrill Gorcunov static inline u64 apic_icr_read(void) { return 0; } 477d674cd19SCyrill Gorcunov static inline void apic_icr_write(u32 low, u32 high) { } 478d674cd19SCyrill Gorcunov static inline void apic_wait_icr_idle(void) { } 479d674cd19SCyrill Gorcunov static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 4801551df64SMichael S. Tsirkin static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 481d674cd19SCyrill Gorcunov 482d674cd19SCyrill Gorcunov #endif /* CONFIG_X86_LOCAL_APIC */ 483e2780a68SIngo Molnar 484e2780a68SIngo Molnar static inline void ack_APIC_irq(void) 485e2780a68SIngo Molnar { 486e2780a68SIngo Molnar /* 487e2780a68SIngo Molnar * ack_APIC_irq() actually gets compiled as a single instruction 488e2780a68SIngo Molnar * ... yummie. 489e2780a68SIngo Molnar */ 4902a43195dSMichael S. Tsirkin apic_eoi(); 491e2780a68SIngo Molnar } 492e2780a68SIngo Molnar 493e2780a68SIngo Molnar static inline unsigned default_get_apic_id(unsigned long x) 494e2780a68SIngo Molnar { 495e2780a68SIngo Molnar unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 496e2780a68SIngo Molnar 49742937e81SAndreas Herrmann if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 498e2780a68SIngo Molnar return (x >> 24) & 0xFF; 499e2780a68SIngo Molnar else 500e2780a68SIngo Molnar return (x >> 24) & 0x0F; 501e2780a68SIngo Molnar } 502e2780a68SIngo Molnar 503e2780a68SIngo Molnar /* 504e2780a68SIngo Molnar * Warm reset vector default position: 505e2780a68SIngo Molnar */ 506e2780a68SIngo Molnar #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 507e2780a68SIngo Molnar #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 508e2780a68SIngo Molnar 5092b6163bfSYinghai Lu #ifdef CONFIG_X86_64 510e2780a68SIngo Molnar extern int default_acpi_madt_oem_check(char *, char *); 511e2780a68SIngo Molnar 512e2780a68SIngo Molnar extern void apic_send_IPI_self(int vector); 513e2780a68SIngo Molnar 514e2780a68SIngo Molnar DECLARE_PER_CPU(int, x2apic_extra_bits); 515e2780a68SIngo Molnar 516e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 517e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 518e2780a68SIngo Molnar #endif 519e2780a68SIngo Molnar 520e2780a68SIngo Molnar static inline void default_wait_for_init_deassert(atomic_t *deassert) 521e2780a68SIngo Molnar { 522e2780a68SIngo Molnar while (!atomic_read(deassert)) 523e2780a68SIngo Molnar cpu_relax(); 524e2780a68SIngo Molnar return; 525e2780a68SIngo Molnar } 526e2780a68SIngo Molnar 527838312beSJan Beulich extern void generic_bigsmp_probe(void); 528e2780a68SIngo Molnar 529e2780a68SIngo Molnar 530e2780a68SIngo Molnar #ifdef CONFIG_X86_LOCAL_APIC 531e2780a68SIngo Molnar 532e2780a68SIngo Molnar #include <asm/smp.h> 533e2780a68SIngo Molnar 534e2780a68SIngo Molnar #define APIC_DFR_VALUE (APIC_DFR_FLAT) 535e2780a68SIngo Molnar 536e2780a68SIngo Molnar static inline const struct cpumask *default_target_cpus(void) 537e2780a68SIngo Molnar { 538e2780a68SIngo Molnar #ifdef CONFIG_SMP 539e2780a68SIngo Molnar return cpu_online_mask; 540e2780a68SIngo Molnar #else 541e2780a68SIngo Molnar return cpumask_of(0); 542e2780a68SIngo Molnar #endif 543e2780a68SIngo Molnar } 544e2780a68SIngo Molnar 545bf721d3aSAlexander Gordeev static inline const struct cpumask *online_target_cpus(void) 546bf721d3aSAlexander Gordeev { 547bf721d3aSAlexander Gordeev return cpu_online_mask; 548bf721d3aSAlexander Gordeev } 549bf721d3aSAlexander Gordeev 5500816b0f0SVlad Zolotarov DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 551e2780a68SIngo Molnar 552e2780a68SIngo Molnar 553e2780a68SIngo Molnar static inline unsigned int read_apic_id(void) 554e2780a68SIngo Molnar { 555e2780a68SIngo Molnar unsigned int reg; 556e2780a68SIngo Molnar 557e2780a68SIngo Molnar reg = apic_read(APIC_ID); 558e2780a68SIngo Molnar 559e2780a68SIngo Molnar return apic->get_apic_id(reg); 560e2780a68SIngo Molnar } 561e2780a68SIngo Molnar 562fa63030eSDaniel J Blueman static inline int default_apic_id_valid(int apicid) 563fa63030eSDaniel J Blueman { 564b7157acfSSteffen Persvold return (apicid < 255); 565fa63030eSDaniel J Blueman } 566fa63030eSDaniel J Blueman 567e2780a68SIngo Molnar extern void default_setup_apic_routing(void); 568e2780a68SIngo Molnar 5699844ab11SCyrill Gorcunov extern struct apic apic_noop; 5709844ab11SCyrill Gorcunov 571e2780a68SIngo Molnar #ifdef CONFIG_X86_32 5722c1b284eSJaswinder Singh Rajput 573acb8bc09STejun Heo static inline int noop_x86_32_early_logical_apicid(int cpu) 574acb8bc09STejun Heo { 575acb8bc09STejun Heo return BAD_APICID; 576acb8bc09STejun Heo } 577acb8bc09STejun Heo 578e2780a68SIngo Molnar /* 579e2780a68SIngo Molnar * Set up the logical destination ID. 580e2780a68SIngo Molnar * 581e2780a68SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 582e2780a68SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 583e2780a68SIngo Molnar * document number 292116). So here it goes... 584e2780a68SIngo Molnar */ 585e2780a68SIngo Molnar extern void default_init_apic_ldr(void); 586e2780a68SIngo Molnar 587e2780a68SIngo Molnar static inline int default_apic_id_registered(void) 588e2780a68SIngo Molnar { 589e2780a68SIngo Molnar return physid_isset(read_apic_id(), phys_cpu_present_map); 590e2780a68SIngo Molnar } 591e2780a68SIngo Molnar 592f56e5034SYinghai Lu static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 593f56e5034SYinghai Lu { 594f56e5034SYinghai Lu return cpuid_apic >> index_msb; 595f56e5034SYinghai Lu } 596f56e5034SYinghai Lu 597f56e5034SYinghai Lu #endif 598f56e5034SYinghai Lu 599ff164324SAlexander Gordeev static inline int 600a5a39156SAlexander Gordeev flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 601a5a39156SAlexander Gordeev const struct cpumask *andmask, 602a5a39156SAlexander Gordeev unsigned int *apicid) 603e2780a68SIngo Molnar { 604a5a39156SAlexander Gordeev unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 605a5a39156SAlexander Gordeev cpumask_bits(andmask)[0] & 606a5a39156SAlexander Gordeev cpumask_bits(cpu_online_mask)[0] & 607a5a39156SAlexander Gordeev APIC_ALL_CPUS; 608a5a39156SAlexander Gordeev 609ff164324SAlexander Gordeev if (likely(cpu_mask)) { 610ff164324SAlexander Gordeev *apicid = (unsigned int)cpu_mask; 611ff164324SAlexander Gordeev return 0; 612ff164324SAlexander Gordeev } else { 613ff164324SAlexander Gordeev return -EINVAL; 614ff164324SAlexander Gordeev } 615e2780a68SIngo Molnar } 616e2780a68SIngo Molnar 617ff164324SAlexander Gordeev extern int 6186398268dSAlexander Gordeev default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 619ff164324SAlexander Gordeev const struct cpumask *andmask, 620ff164324SAlexander Gordeev unsigned int *apicid); 6216398268dSAlexander Gordeev 622b39f25a8SSuresh Siddha static inline void 6231ac322d0SSuresh Siddha flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 6241ac322d0SSuresh Siddha const struct cpumask *mask) 6259d8e1066SAlexander Gordeev { 6269d8e1066SAlexander Gordeev /* Careful. Some cpus do not strictly honor the set of cpus 6279d8e1066SAlexander Gordeev * specified in the interrupt destination when using lowest 6289d8e1066SAlexander Gordeev * priority interrupt delivery mode. 6299d8e1066SAlexander Gordeev * 6309d8e1066SAlexander Gordeev * In particular there was a hyperthreading cpu observed to 6319d8e1066SAlexander Gordeev * deliver interrupts to the wrong hyperthread when only one 6329d8e1066SAlexander Gordeev * hyperthread was specified in the interrupt desitination. 6339d8e1066SAlexander Gordeev */ 6349d8e1066SAlexander Gordeev cpumask_clear(retmask); 6359d8e1066SAlexander Gordeev cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 6369d8e1066SAlexander Gordeev } 6379d8e1066SAlexander Gordeev 638b39f25a8SSuresh Siddha static inline void 6391ac322d0SSuresh Siddha default_vector_allocation_domain(int cpu, struct cpumask *retmask, 6401ac322d0SSuresh Siddha const struct cpumask *mask) 6419d8e1066SAlexander Gordeev { 6429d8e1066SAlexander Gordeev cpumask_copy(retmask, cpumask_of(cpu)); 6439d8e1066SAlexander Gordeev } 6449d8e1066SAlexander Gordeev 6457abc0753SCyrill Gorcunov static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 646e2780a68SIngo Molnar { 6477abc0753SCyrill Gorcunov return physid_isset(apicid, *map); 648e2780a68SIngo Molnar } 649e2780a68SIngo Molnar 650e2780a68SIngo Molnar static inline unsigned long default_check_apicid_present(int bit) 651e2780a68SIngo Molnar { 652e2780a68SIngo Molnar return physid_isset(bit, phys_cpu_present_map); 653e2780a68SIngo Molnar } 654e2780a68SIngo Molnar 6557abc0753SCyrill Gorcunov static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 656e2780a68SIngo Molnar { 6577abc0753SCyrill Gorcunov *retmap = *phys_map; 658e2780a68SIngo Molnar } 659e2780a68SIngo Molnar 660e2780a68SIngo Molnar static inline int __default_cpu_present_to_apicid(int mps_cpu) 661e2780a68SIngo Molnar { 662e2780a68SIngo Molnar if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 663e2780a68SIngo Molnar return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 664e2780a68SIngo Molnar else 665e2780a68SIngo Molnar return BAD_APICID; 666e2780a68SIngo Molnar } 667e2780a68SIngo Molnar 668e2780a68SIngo Molnar static inline int 669e11dadabSThomas Gleixner __default_check_phys_apicid_present(int phys_apicid) 670e2780a68SIngo Molnar { 671e11dadabSThomas Gleixner return physid_isset(phys_apicid, phys_cpu_present_map); 672e2780a68SIngo Molnar } 673e2780a68SIngo Molnar 674e2780a68SIngo Molnar #ifdef CONFIG_X86_32 675e2780a68SIngo Molnar static inline int default_cpu_present_to_apicid(int mps_cpu) 676e2780a68SIngo Molnar { 677e2780a68SIngo Molnar return __default_cpu_present_to_apicid(mps_cpu); 678e2780a68SIngo Molnar } 679e2780a68SIngo Molnar 680e2780a68SIngo Molnar static inline int 681e11dadabSThomas Gleixner default_check_phys_apicid_present(int phys_apicid) 682e2780a68SIngo Molnar { 683e11dadabSThomas Gleixner return __default_check_phys_apicid_present(phys_apicid); 684e2780a68SIngo Molnar } 685e2780a68SIngo Molnar #else 686e2780a68SIngo Molnar extern int default_cpu_present_to_apicid(int mps_cpu); 687e11dadabSThomas Gleixner extern int default_check_phys_apicid_present(int phys_apicid); 688e2780a68SIngo Molnar #endif 689e2780a68SIngo Molnar 690e2780a68SIngo Molnar #endif /* CONFIG_X86_LOCAL_APIC */ 691eddc0e92SSeiji Aguchi extern void irq_enter(void); 692eddc0e92SSeiji Aguchi extern void irq_exit(void); 693eddc0e92SSeiji Aguchi 694eddc0e92SSeiji Aguchi static inline void entering_irq(void) 695eddc0e92SSeiji Aguchi { 696eddc0e92SSeiji Aguchi irq_enter(); 697eddc0e92SSeiji Aguchi exit_idle(); 698eddc0e92SSeiji Aguchi } 699eddc0e92SSeiji Aguchi 700eddc0e92SSeiji Aguchi static inline void entering_ack_irq(void) 701eddc0e92SSeiji Aguchi { 702eddc0e92SSeiji Aguchi ack_APIC_irq(); 703eddc0e92SSeiji Aguchi entering_irq(); 704eddc0e92SSeiji Aguchi } 705eddc0e92SSeiji Aguchi 706eddc0e92SSeiji Aguchi static inline void exiting_irq(void) 707eddc0e92SSeiji Aguchi { 708eddc0e92SSeiji Aguchi irq_exit(); 709eddc0e92SSeiji Aguchi } 710eddc0e92SSeiji Aguchi 711eddc0e92SSeiji Aguchi static inline void exiting_ack_irq(void) 712eddc0e92SSeiji Aguchi { 713eddc0e92SSeiji Aguchi irq_exit(); 714eddc0e92SSeiji Aguchi /* Ack only at the end to avoid potential reentry */ 715eddc0e92SSeiji Aguchi ack_APIC_irq(); 716eddc0e92SSeiji Aguchi } 717e2780a68SIngo Molnar 71817405453SYoshihiro YUNOMAE extern void ioapic_zap_locks(void); 71917405453SYoshihiro YUNOMAE 7201965aae3SH. Peter Anvin #endif /* _ASM_X86_APIC_H */ 721