1 #ifndef _ASM_X86_AMD_NB_H 2 #define _ASM_X86_AMD_NB_H 3 4 #include <linux/ioport.h> 5 #include <linux/pci.h> 6 7 struct amd_nb_bus_dev_range { 8 u8 bus; 9 u8 dev_base; 10 u8 dev_limit; 11 }; 12 13 extern const struct pci_device_id amd_nb_misc_ids[]; 14 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; 15 16 extern bool early_is_amd_nb(u32 value); 17 extern struct resource *amd_get_mmconfig_range(struct resource *res); 18 extern int amd_cache_northbridges(void); 19 extern void amd_flush_garts(void); 20 extern int amd_numa_init(void); 21 extern int amd_get_subcaches(int); 22 extern int amd_set_subcaches(int, unsigned long); 23 24 struct amd_l3_cache { 25 unsigned indices; 26 u8 subcaches[4]; 27 }; 28 29 struct threshold_block { 30 unsigned int block; /* Number within bank */ 31 unsigned int bank; /* MCA bank the block belongs to */ 32 unsigned int cpu; /* CPU which controls MCA bank */ 33 u32 address; /* MSR address for the block */ 34 u16 interrupt_enable; /* Enable/Disable APIC interrupt */ 35 bool interrupt_capable; /* Bank can generate an interrupt. */ 36 37 u16 threshold_limit; /* 38 * Value upon which threshold 39 * interrupt is generated. 40 */ 41 42 struct kobject kobj; /* sysfs object */ 43 struct list_head miscj; /* 44 * List of threshold blocks 45 * within a bank. 46 */ 47 }; 48 49 struct threshold_bank { 50 struct kobject *kobj; 51 struct threshold_block *blocks; 52 53 /* initialized to the number of CPUs on the node sharing this bank */ 54 atomic_t cpus; 55 }; 56 57 struct amd_northbridge { 58 struct pci_dev *misc; 59 struct pci_dev *link; 60 struct amd_l3_cache l3_cache; 61 struct threshold_bank *bank4; 62 }; 63 64 struct amd_northbridge_info { 65 u16 num; 66 u64 flags; 67 struct amd_northbridge *nb; 68 }; 69 extern struct amd_northbridge_info amd_northbridges; 70 71 #define AMD_NB_GART BIT(0) 72 #define AMD_NB_L3_INDEX_DISABLE BIT(1) 73 #define AMD_NB_L3_PARTITIONING BIT(2) 74 75 #ifdef CONFIG_AMD_NB 76 77 static inline u16 amd_nb_num(void) 78 { 79 return amd_northbridges.num; 80 } 81 82 static inline bool amd_nb_has_feature(unsigned feature) 83 { 84 return ((amd_northbridges.flags & feature) == feature); 85 } 86 87 static inline struct amd_northbridge *node_to_amd_nb(int node) 88 { 89 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL; 90 } 91 92 static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev) 93 { 94 struct pci_dev *misc; 95 int i; 96 97 for (i = 0; i != amd_nb_num(); i++) { 98 misc = node_to_amd_nb(i)->misc; 99 100 if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) && 101 PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn)) 102 return i; 103 } 104 105 WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev)); 106 return 0; 107 } 108 109 static inline bool amd_gart_present(void) 110 { 111 /* GART present only on Fam15h, upto model 0fh */ 112 if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || 113 (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) 114 return true; 115 116 return false; 117 } 118 119 #else 120 121 #define amd_nb_num(x) 0 122 #define amd_nb_has_feature(x) false 123 #define node_to_amd_nb(x) NULL 124 #define amd_gart_present(x) false 125 126 #endif 127 128 129 #endif /* _ASM_X86_AMD_NB_H */ 130