1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_AMD_NB_H 3 #define _ASM_X86_AMD_NB_H 4 5 #include <linux/ioport.h> 6 #include <linux/pci.h> 7 #include <linux/refcount.h> 8 9 struct amd_nb_bus_dev_range { 10 u8 bus; 11 u8 dev_base; 12 u8 dev_limit; 13 }; 14 15 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; 16 17 extern bool early_is_amd_nb(u32 value); 18 extern struct resource *amd_get_mmconfig_range(struct resource *res); 19 extern int amd_cache_northbridges(void); 20 extern void amd_flush_garts(void); 21 extern int amd_numa_init(void); 22 extern int amd_get_subcaches(int); 23 extern int amd_set_subcaches(int, unsigned long); 24 25 extern int amd_smn_read(u16 node, u32 address, u32 *value); 26 extern int amd_smn_write(u16 node, u32 address, u32 value); 27 extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo); 28 29 struct amd_l3_cache { 30 unsigned indices; 31 u8 subcaches[4]; 32 }; 33 34 struct threshold_block { 35 unsigned int block; /* Number within bank */ 36 unsigned int bank; /* MCA bank the block belongs to */ 37 unsigned int cpu; /* CPU which controls MCA bank */ 38 u32 address; /* MSR address for the block */ 39 u16 interrupt_enable; /* Enable/Disable APIC interrupt */ 40 bool interrupt_capable; /* Bank can generate an interrupt. */ 41 42 u16 threshold_limit; /* 43 * Value upon which threshold 44 * interrupt is generated. 45 */ 46 47 struct kobject kobj; /* sysfs object */ 48 struct list_head miscj; /* 49 * List of threshold blocks 50 * within a bank. 51 */ 52 }; 53 54 struct threshold_bank { 55 struct kobject *kobj; 56 struct threshold_block *blocks; 57 58 /* initialized to the number of CPUs on the node sharing this bank */ 59 refcount_t cpus; 60 }; 61 62 struct amd_northbridge { 63 struct pci_dev *root; 64 struct pci_dev *misc; 65 struct pci_dev *link; 66 struct amd_l3_cache l3_cache; 67 struct threshold_bank *bank4; 68 }; 69 70 struct amd_northbridge_info { 71 u16 num; 72 u64 flags; 73 struct amd_northbridge *nb; 74 }; 75 76 #define AMD_NB_GART BIT(0) 77 #define AMD_NB_L3_INDEX_DISABLE BIT(1) 78 #define AMD_NB_L3_PARTITIONING BIT(2) 79 80 #ifdef CONFIG_AMD_NB 81 82 u16 amd_nb_num(void); 83 bool amd_nb_has_feature(unsigned int feature); 84 struct amd_northbridge *node_to_amd_nb(int node); 85 86 static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev) 87 { 88 struct pci_dev *misc; 89 int i; 90 91 for (i = 0; i != amd_nb_num(); i++) { 92 misc = node_to_amd_nb(i)->misc; 93 94 if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) && 95 PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn)) 96 return i; 97 } 98 99 WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev)); 100 return 0; 101 } 102 103 static inline bool amd_gart_present(void) 104 { 105 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 106 return false; 107 108 /* GART present only on Fam15h, upto model 0fh */ 109 if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || 110 (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) 111 return true; 112 113 return false; 114 } 115 116 #else 117 118 #define amd_nb_num(x) 0 119 #define amd_nb_has_feature(x) false 120 #define node_to_amd_nb(x) NULL 121 #define amd_gart_present(x) false 122 123 #endif 124 125 126 #endif /* _ASM_X86_AMD_NB_H */ 127