1 #ifndef _ASM_X86_ACPI_H 2 #define _ASM_X86_ACPI_H 3 4 /* 5 * Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 6 * Copyright (C) 2001 Patrick Mochel <mochel@osdl.org> 7 * 8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 25 */ 26 #include <acpi/pdc_intel.h> 27 28 #include <asm/numa.h> 29 #include <asm/processor.h> 30 #include <asm/mmu.h> 31 #include <asm/mpspec.h> 32 33 #define COMPILER_DEPENDENT_INT64 long long 34 #define COMPILER_DEPENDENT_UINT64 unsigned long long 35 36 /* 37 * Calling conventions: 38 * 39 * ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads) 40 * ACPI_EXTERNAL_XFACE - External ACPI interfaces 41 * ACPI_INTERNAL_XFACE - Internal ACPI interfaces 42 * ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces 43 */ 44 #define ACPI_SYSTEM_XFACE 45 #define ACPI_EXTERNAL_XFACE 46 #define ACPI_INTERNAL_XFACE 47 #define ACPI_INTERNAL_VAR_XFACE 48 49 /* Asm macros */ 50 51 #define ACPI_ASM_MACROS 52 #define BREAKPOINT3 53 #define ACPI_DISABLE_IRQS() local_irq_disable() 54 #define ACPI_ENABLE_IRQS() local_irq_enable() 55 #define ACPI_FLUSH_CPU_CACHE() wbinvd() 56 57 int __acpi_acquire_global_lock(unsigned int *lock); 58 int __acpi_release_global_lock(unsigned int *lock); 59 60 #define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \ 61 ((Acq) = __acpi_acquire_global_lock(&facs->global_lock)) 62 63 #define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \ 64 ((Acq) = __acpi_release_global_lock(&facs->global_lock)) 65 66 /* 67 * Math helper asm macros 68 */ 69 #define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \ 70 asm("divl %2;" \ 71 : "=a"(q32), "=d"(r32) \ 72 : "r"(d32), \ 73 "0"(n_lo), "1"(n_hi)) 74 75 76 #define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \ 77 asm("shrl $1,%2 ;" \ 78 "rcrl $1,%3;" \ 79 : "=r"(n_hi), "=r"(n_lo) \ 80 : "0"(n_hi), "1"(n_lo)) 81 82 #ifdef CONFIG_ACPI 83 extern int acpi_lapic; 84 extern int acpi_ioapic; 85 extern int acpi_noirq; 86 extern int acpi_strict; 87 extern int acpi_disabled; 88 extern int acpi_ht; 89 extern int acpi_pci_disabled; 90 extern int acpi_skip_timer_override; 91 extern int acpi_use_timer_override; 92 93 extern u8 acpi_sci_flags; 94 extern int acpi_sci_override_gsi; 95 void acpi_pic_sci_set_trigger(unsigned int, u16); 96 97 static inline void disable_acpi(void) 98 { 99 acpi_disabled = 1; 100 acpi_ht = 0; 101 acpi_pci_disabled = 1; 102 acpi_noirq = 1; 103 } 104 105 extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq); 106 107 static inline void acpi_noirq_set(void) { acpi_noirq = 1; } 108 static inline void acpi_disable_pci(void) 109 { 110 acpi_pci_disabled = 1; 111 acpi_noirq_set(); 112 } 113 114 /* routines for saving/restoring kernel state */ 115 extern int acpi_save_state_mem(void); 116 extern void acpi_restore_state_mem(void); 117 118 extern unsigned long acpi_wakeup_address; 119 120 /* early initialization routine */ 121 extern void acpi_reserve_wakeup_memory(void); 122 123 /* 124 * Check if the CPU can handle C2 and deeper 125 */ 126 static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) 127 { 128 /* 129 * Early models (<=5) of AMD Opterons are not supposed to go into 130 * C2 state. 131 * 132 * Steppings 0x0A and later are good 133 */ 134 if (boot_cpu_data.x86 == 0x0F && 135 boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 136 boot_cpu_data.x86_model <= 0x05 && 137 boot_cpu_data.x86_mask < 0x0A) 138 return 1; 139 else if (boot_cpu_has(X86_FEATURE_AMDC1E)) 140 return 1; 141 else 142 return max_cstate; 143 } 144 145 static inline bool arch_has_acpi_pdc(void) 146 { 147 struct cpuinfo_x86 *c = &cpu_data(0); 148 return (c->x86_vendor == X86_VENDOR_INTEL || 149 c->x86_vendor == X86_VENDOR_CENTAUR); 150 } 151 152 static inline void arch_acpi_set_pdc_bits(u32 *buf) 153 { 154 struct cpuinfo_x86 *c = &cpu_data(0); 155 156 buf[2] |= ACPI_PDC_C_CAPABILITY_SMP; 157 158 if (cpu_has(c, X86_FEATURE_EST)) 159 buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP; 160 161 if (cpu_has(c, X86_FEATURE_ACPI)) 162 buf[2] |= ACPI_PDC_T_FFH; 163 164 /* 165 * If mwait/monitor is unsupported, C2/C3_FFH will be disabled 166 */ 167 if (!cpu_has(c, X86_FEATURE_MWAIT)) 168 buf[2] &= ~(ACPI_PDC_C_C2C3_FFH); 169 } 170 171 #else /* !CONFIG_ACPI */ 172 173 #define acpi_lapic 0 174 #define acpi_ioapic 0 175 static inline void acpi_noirq_set(void) { } 176 static inline void acpi_disable_pci(void) { } 177 static inline void disable_acpi(void) { } 178 179 #endif /* !CONFIG_ACPI */ 180 181 #define ARCH_HAS_POWER_INIT 1 182 183 struct bootnode; 184 185 #ifdef CONFIG_ACPI_NUMA 186 extern int acpi_numa; 187 extern int acpi_get_nodes(struct bootnode *physnodes); 188 extern int acpi_scan_nodes(unsigned long start, unsigned long end); 189 #define NR_NODE_MEMBLKS (MAX_NUMNODES*2) 190 extern void acpi_fake_nodes(const struct bootnode *fake_nodes, 191 int num_nodes); 192 #else 193 static inline void acpi_fake_nodes(const struct bootnode *fake_nodes, 194 int num_nodes) 195 { 196 } 197 #endif 198 199 #define acpi_unlazy_tlb(x) leave_mm(x) 200 201 #endif /* _ASM_X86_ACPI_H */ 202