1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * Hyper-V specific APIC code. 5 * 6 * Copyright (C) 2018, Microsoft, Inc. 7 * 8 * Author : K. Y. Srinivasan <kys@microsoft.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 17 * NON INFRINGEMENT. See the GNU General Public License for more 18 * details. 19 * 20 */ 21 22 #include <linux/types.h> 23 #include <linux/version.h> 24 #include <linux/vmalloc.h> 25 #include <linux/mm.h> 26 #include <linux/clockchips.h> 27 #include <linux/hyperv.h> 28 #include <linux/slab.h> 29 #include <linux/cpuhotplug.h> 30 #include <asm/hypervisor.h> 31 #include <asm/mshyperv.h> 32 #include <asm/apic.h> 33 34 static struct apic orig_apic; 35 36 static u64 hv_apic_icr_read(void) 37 { 38 u64 reg_val; 39 40 rdmsrl(HV_X64_MSR_ICR, reg_val); 41 return reg_val; 42 } 43 44 static void hv_apic_icr_write(u32 low, u32 id) 45 { 46 u64 reg_val; 47 48 reg_val = SET_APIC_DEST_FIELD(id); 49 reg_val = reg_val << 32; 50 reg_val |= low; 51 52 wrmsrl(HV_X64_MSR_ICR, reg_val); 53 } 54 55 static u32 hv_apic_read(u32 reg) 56 { 57 u32 reg_val, hi; 58 59 switch (reg) { 60 case APIC_EOI: 61 rdmsr(HV_X64_MSR_EOI, reg_val, hi); 62 return reg_val; 63 case APIC_TASKPRI: 64 rdmsr(HV_X64_MSR_TPR, reg_val, hi); 65 return reg_val; 66 67 default: 68 return native_apic_mem_read(reg); 69 } 70 } 71 72 static void hv_apic_write(u32 reg, u32 val) 73 { 74 switch (reg) { 75 case APIC_EOI: 76 wrmsr(HV_X64_MSR_EOI, val, 0); 77 break; 78 case APIC_TASKPRI: 79 wrmsr(HV_X64_MSR_TPR, val, 0); 80 break; 81 default: 82 native_apic_mem_write(reg, val); 83 } 84 } 85 86 static void hv_apic_eoi_write(u32 reg, u32 val) 87 { 88 wrmsr(HV_X64_MSR_EOI, val, 0); 89 } 90 91 /* 92 * IPI implementation on Hyper-V. 93 */ 94 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector) 95 { 96 struct ipi_arg_ex **arg; 97 struct ipi_arg_ex *ipi_arg; 98 unsigned long flags; 99 int nr_bank = 0; 100 int ret = 1; 101 102 local_irq_save(flags); 103 arg = (struct ipi_arg_ex **)this_cpu_ptr(hyperv_pcpu_input_arg); 104 105 ipi_arg = *arg; 106 if (unlikely(!ipi_arg)) 107 goto ipi_mask_ex_done; 108 109 ipi_arg->vector = vector; 110 ipi_arg->reserved = 0; 111 ipi_arg->vp_set.valid_bank_mask = 0; 112 113 if (!cpumask_equal(mask, cpu_present_mask)) { 114 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K; 115 nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask); 116 } 117 if (nr_bank < 0) 118 goto ipi_mask_ex_done; 119 if (!nr_bank) 120 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL; 121 122 ret = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank, 123 ipi_arg, NULL); 124 125 ipi_mask_ex_done: 126 local_irq_restore(flags); 127 return ((ret == 0) ? true : false); 128 } 129 130 static bool __send_ipi_mask(const struct cpumask *mask, int vector) 131 { 132 int cur_cpu, vcpu; 133 struct ipi_arg_non_ex **arg; 134 struct ipi_arg_non_ex *ipi_arg; 135 int ret = 1; 136 unsigned long flags; 137 138 if (cpumask_empty(mask)) 139 return true; 140 141 if (!hv_hypercall_pg) 142 return false; 143 144 if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR)) 145 return false; 146 147 if ((ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED)) 148 return __send_ipi_mask_ex(mask, vector); 149 150 local_irq_save(flags); 151 arg = (struct ipi_arg_non_ex **)this_cpu_ptr(hyperv_pcpu_input_arg); 152 153 ipi_arg = *arg; 154 if (unlikely(!ipi_arg)) 155 goto ipi_mask_done; 156 157 ipi_arg->vector = vector; 158 ipi_arg->reserved = 0; 159 ipi_arg->cpu_mask = 0; 160 161 for_each_cpu(cur_cpu, mask) { 162 vcpu = hv_cpu_number_to_vp_number(cur_cpu); 163 if (vcpu == VP_INVAL) 164 goto ipi_mask_done; 165 166 /* 167 * This particular version of the IPI hypercall can 168 * only target upto 64 CPUs. 169 */ 170 if (vcpu >= 64) 171 goto ipi_mask_done; 172 173 __set_bit(vcpu, (unsigned long *)&ipi_arg->cpu_mask); 174 } 175 176 ret = hv_do_hypercall(HVCALL_SEND_IPI, ipi_arg, NULL); 177 178 ipi_mask_done: 179 local_irq_restore(flags); 180 return ((ret == 0) ? true : false); 181 } 182 183 static bool __send_ipi_one(int cpu, int vector) 184 { 185 struct cpumask mask = CPU_MASK_NONE; 186 187 cpumask_set_cpu(cpu, &mask); 188 return __send_ipi_mask(&mask, vector); 189 } 190 191 static void hv_send_ipi(int cpu, int vector) 192 { 193 if (!__send_ipi_one(cpu, vector)) 194 orig_apic.send_IPI(cpu, vector); 195 } 196 197 static void hv_send_ipi_mask(const struct cpumask *mask, int vector) 198 { 199 if (!__send_ipi_mask(mask, vector)) 200 orig_apic.send_IPI_mask(mask, vector); 201 } 202 203 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector) 204 { 205 unsigned int this_cpu = smp_processor_id(); 206 struct cpumask new_mask; 207 const struct cpumask *local_mask; 208 209 cpumask_copy(&new_mask, mask); 210 cpumask_clear_cpu(this_cpu, &new_mask); 211 local_mask = &new_mask; 212 if (!__send_ipi_mask(local_mask, vector)) 213 orig_apic.send_IPI_mask_allbutself(mask, vector); 214 } 215 216 static void hv_send_ipi_allbutself(int vector) 217 { 218 hv_send_ipi_mask_allbutself(cpu_online_mask, vector); 219 } 220 221 static void hv_send_ipi_all(int vector) 222 { 223 if (!__send_ipi_mask(cpu_online_mask, vector)) 224 orig_apic.send_IPI_all(vector); 225 } 226 227 static void hv_send_ipi_self(int vector) 228 { 229 if (!__send_ipi_one(smp_processor_id(), vector)) 230 orig_apic.send_IPI_self(vector); 231 } 232 233 void __init hv_apic_init(void) 234 { 235 if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) { 236 if ((ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED)) 237 pr_info("Hyper-V: Using ext hypercalls for IPI\n"); 238 else 239 pr_info("Hyper-V: Using IPI hypercalls\n"); 240 /* 241 * Set the IPI entry points. 242 */ 243 orig_apic = *apic; 244 245 apic->send_IPI = hv_send_ipi; 246 apic->send_IPI_mask = hv_send_ipi_mask; 247 apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself; 248 apic->send_IPI_allbutself = hv_send_ipi_allbutself; 249 apic->send_IPI_all = hv_send_ipi_all; 250 apic->send_IPI_self = hv_send_ipi_self; 251 } 252 253 if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) { 254 pr_info("Hyper-V: Using MSR based APIC access\n"); 255 apic_set_eoi_write(hv_apic_eoi_write); 256 apic->read = hv_apic_read; 257 apic->write = hv_apic_write; 258 apic->icr_write = hv_apic_icr_write; 259 apic->icr_read = hv_apic_icr_read; 260 } 261 } 262