1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * Hyper-V specific APIC code. 5 * 6 * Copyright (C) 2018, Microsoft, Inc. 7 * 8 * Author : K. Y. Srinivasan <kys@microsoft.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 17 * NON INFRINGEMENT. See the GNU General Public License for more 18 * details. 19 * 20 */ 21 22 #include <linux/types.h> 23 #include <linux/vmalloc.h> 24 #include <linux/mm.h> 25 #include <linux/clockchips.h> 26 #include <linux/hyperv.h> 27 #include <linux/slab.h> 28 #include <linux/cpuhotplug.h> 29 #include <asm/hypervisor.h> 30 #include <asm/mshyperv.h> 31 #include <asm/apic.h> 32 33 #include <asm/trace/hyperv.h> 34 35 static struct apic orig_apic; 36 37 static u64 hv_apic_icr_read(void) 38 { 39 u64 reg_val; 40 41 rdmsrl(HV_X64_MSR_ICR, reg_val); 42 return reg_val; 43 } 44 45 static void hv_apic_icr_write(u32 low, u32 id) 46 { 47 u64 reg_val; 48 49 reg_val = SET_APIC_DEST_FIELD(id); 50 reg_val = reg_val << 32; 51 reg_val |= low; 52 53 wrmsrl(HV_X64_MSR_ICR, reg_val); 54 } 55 56 static u32 hv_apic_read(u32 reg) 57 { 58 u32 reg_val, hi; 59 60 switch (reg) { 61 case APIC_EOI: 62 rdmsr(HV_X64_MSR_EOI, reg_val, hi); 63 (void)hi; 64 return reg_val; 65 case APIC_TASKPRI: 66 rdmsr(HV_X64_MSR_TPR, reg_val, hi); 67 (void)hi; 68 return reg_val; 69 70 default: 71 return native_apic_mem_read(reg); 72 } 73 } 74 75 static void hv_apic_write(u32 reg, u32 val) 76 { 77 switch (reg) { 78 case APIC_EOI: 79 wrmsr(HV_X64_MSR_EOI, val, 0); 80 break; 81 case APIC_TASKPRI: 82 wrmsr(HV_X64_MSR_TPR, val, 0); 83 break; 84 default: 85 native_apic_mem_write(reg, val); 86 } 87 } 88 89 static void hv_apic_eoi_write(u32 reg, u32 val) 90 { 91 struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()]; 92 93 if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1)) 94 return; 95 96 wrmsr(HV_X64_MSR_EOI, val, 0); 97 } 98 99 /* 100 * IPI implementation on Hyper-V. 101 */ 102 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector, 103 bool exclude_self) 104 { 105 struct hv_send_ipi_ex **arg; 106 struct hv_send_ipi_ex *ipi_arg; 107 unsigned long flags; 108 int nr_bank = 0; 109 u64 status = HV_STATUS_INVALID_PARAMETER; 110 111 if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED)) 112 return false; 113 114 local_irq_save(flags); 115 arg = (struct hv_send_ipi_ex **)this_cpu_ptr(hyperv_pcpu_input_arg); 116 117 ipi_arg = *arg; 118 if (unlikely(!ipi_arg)) 119 goto ipi_mask_ex_done; 120 121 ipi_arg->vector = vector; 122 ipi_arg->reserved = 0; 123 ipi_arg->vp_set.valid_bank_mask = 0; 124 125 if (!cpumask_equal(mask, cpu_present_mask)) { 126 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K; 127 if (exclude_self) 128 nr_bank = cpumask_to_vpset_noself(&(ipi_arg->vp_set), mask); 129 else 130 nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask); 131 } 132 if (nr_bank < 0) 133 goto ipi_mask_ex_done; 134 if (!nr_bank) 135 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL; 136 137 status = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank, 138 ipi_arg, NULL); 139 140 ipi_mask_ex_done: 141 local_irq_restore(flags); 142 return hv_result_success(status); 143 } 144 145 static bool __send_ipi_mask(const struct cpumask *mask, int vector, 146 bool exclude_self) 147 { 148 int cur_cpu, vcpu, this_cpu = smp_processor_id(); 149 struct hv_send_ipi ipi_arg; 150 u64 status; 151 unsigned int weight; 152 153 trace_hyperv_send_ipi_mask(mask, vector); 154 155 weight = cpumask_weight(mask); 156 157 /* 158 * Do nothing if 159 * 1. the mask is empty 160 * 2. the mask only contains self when exclude_self is true 161 */ 162 if (weight == 0 || 163 (exclude_self && weight == 1 && cpumask_test_cpu(this_cpu, mask))) 164 return true; 165 166 if (!hv_hypercall_pg) 167 return false; 168 169 if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR)) 170 return false; 171 172 /* 173 * From the supplied CPU set we need to figure out if we can get away 174 * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the 175 * highest VP number in the set is < 64. As VP numbers are usually in 176 * ascending order and match Linux CPU ids, here is an optimization: 177 * we check the VP number for the highest bit in the supplied set first 178 * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is 179 * a must. We will also check all VP numbers when walking the supplied 180 * CPU set to remain correct in all cases. 181 */ 182 if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64) 183 goto do_ex_hypercall; 184 185 ipi_arg.vector = vector; 186 ipi_arg.cpu_mask = 0; 187 188 for_each_cpu(cur_cpu, mask) { 189 if (exclude_self && cur_cpu == this_cpu) 190 continue; 191 vcpu = hv_cpu_number_to_vp_number(cur_cpu); 192 if (vcpu == VP_INVAL) 193 return false; 194 195 /* 196 * This particular version of the IPI hypercall can 197 * only target upto 64 CPUs. 198 */ 199 if (vcpu >= 64) 200 goto do_ex_hypercall; 201 202 __set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask); 203 } 204 205 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector, 206 ipi_arg.cpu_mask); 207 return hv_result_success(status); 208 209 do_ex_hypercall: 210 return __send_ipi_mask_ex(mask, vector, exclude_self); 211 } 212 213 static bool __send_ipi_one(int cpu, int vector) 214 { 215 int vp = hv_cpu_number_to_vp_number(cpu); 216 u64 status; 217 218 trace_hyperv_send_ipi_one(cpu, vector); 219 220 if (!hv_hypercall_pg || (vp == VP_INVAL)) 221 return false; 222 223 if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR)) 224 return false; 225 226 if (vp >= 64) 227 return __send_ipi_mask_ex(cpumask_of(cpu), vector, false); 228 229 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp)); 230 return hv_result_success(status); 231 } 232 233 static void hv_send_ipi(int cpu, int vector) 234 { 235 if (!__send_ipi_one(cpu, vector)) 236 orig_apic.send_IPI(cpu, vector); 237 } 238 239 static void hv_send_ipi_mask(const struct cpumask *mask, int vector) 240 { 241 if (!__send_ipi_mask(mask, vector, false)) 242 orig_apic.send_IPI_mask(mask, vector); 243 } 244 245 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector) 246 { 247 if (!__send_ipi_mask(mask, vector, true)) 248 orig_apic.send_IPI_mask_allbutself(mask, vector); 249 } 250 251 static void hv_send_ipi_allbutself(int vector) 252 { 253 hv_send_ipi_mask_allbutself(cpu_online_mask, vector); 254 } 255 256 static void hv_send_ipi_all(int vector) 257 { 258 if (!__send_ipi_mask(cpu_online_mask, vector, false)) 259 orig_apic.send_IPI_all(vector); 260 } 261 262 static void hv_send_ipi_self(int vector) 263 { 264 if (!__send_ipi_one(smp_processor_id(), vector)) 265 orig_apic.send_IPI_self(vector); 266 } 267 268 void __init hv_apic_init(void) 269 { 270 if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) { 271 pr_info("Hyper-V: Using IPI hypercalls\n"); 272 /* 273 * Set the IPI entry points. 274 */ 275 orig_apic = *apic; 276 277 apic->send_IPI = hv_send_ipi; 278 apic->send_IPI_mask = hv_send_ipi_mask; 279 apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself; 280 apic->send_IPI_allbutself = hv_send_ipi_allbutself; 281 apic->send_IPI_all = hv_send_ipi_all; 282 apic->send_IPI_self = hv_send_ipi_self; 283 } 284 285 if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) { 286 pr_info("Hyper-V: Using enlightened APIC (%s mode)", 287 x2apic_enabled() ? "x2apic" : "xapic"); 288 /* 289 * When in x2apic mode, don't use the Hyper-V specific APIC 290 * accessors since the field layout in the ICR register is 291 * different in x2apic mode. Furthermore, the architectural 292 * x2apic MSRs function just as well as the Hyper-V 293 * synthetic APIC MSRs, so there's no benefit in having 294 * separate Hyper-V accessors for x2apic mode. The only 295 * exception is hv_apic_eoi_write, because it benefits from 296 * lazy EOI when available, but the same accessor works for 297 * both xapic and x2apic because the field layout is the same. 298 */ 299 apic_set_eoi_write(hv_apic_eoi_write); 300 if (!x2apic_enabled()) { 301 apic->read = hv_apic_read; 302 apic->write = hv_apic_write; 303 apic->icr_write = hv_apic_icr_write; 304 apic->icr_read = hv_apic_icr_read; 305 } 306 } 307 } 308