1 /* 2 * Performance events x86 architecture header 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 17 #include <asm/fpu/xstate.h> 18 #include <asm/intel_ds.h> 19 #include <asm/cpu.h> 20 21 /* To enable MSR tracing please use the generic trace points. */ 22 23 /* 24 * | NHM/WSM | SNB | 25 * register ------------------------------- 26 * | HT | no HT | HT | no HT | 27 *----------------------------------------- 28 * offcore | core | core | cpu | core | 29 * lbr_sel | core | core | cpu | core | 30 * ld_lat | cpu | core | cpu | core | 31 *----------------------------------------- 32 * 33 * Given that there is a small number of shared regs, 34 * we can pre-allocate their slot in the per-cpu 35 * per-core reg tables. 36 */ 37 enum extra_reg_type { 38 EXTRA_REG_NONE = -1, /* not used */ 39 40 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 41 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 42 EXTRA_REG_LBR = 2, /* lbr_select */ 43 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 44 EXTRA_REG_FE = 4, /* fe_* */ 45 46 EXTRA_REG_MAX /* number of entries needed */ 47 }; 48 49 struct event_constraint { 50 union { 51 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 52 u64 idxmsk64; 53 }; 54 u64 code; 55 u64 cmask; 56 int weight; 57 int overlap; 58 int flags; 59 unsigned int size; 60 }; 61 62 static inline bool constraint_match(struct event_constraint *c, u64 ecode) 63 { 64 return ((ecode & c->cmask) - c->code) <= (u64)c->size; 65 } 66 67 /* 68 * struct hw_perf_event.flags flags 69 */ 70 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ 71 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ 72 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ 73 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */ 74 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */ 75 #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */ 76 #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */ 77 78 #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */ 79 #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */ 80 #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */ 81 #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */ 82 #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */ 83 #define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */ 84 #define PERF_X86_EVENT_TOPDOWN 0x4000 /* Count Topdown slots/metrics events */ 85 #define PERF_X86_EVENT_PEBS_STLAT 0x8000 /* st+stlat data address sampling */ 86 87 static inline bool is_topdown_count(struct perf_event *event) 88 { 89 return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 90 } 91 92 static inline bool is_metric_event(struct perf_event *event) 93 { 94 u64 config = event->attr.config; 95 96 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 97 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 98 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 99 } 100 101 static inline bool is_slots_event(struct perf_event *event) 102 { 103 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 104 } 105 106 static inline bool is_topdown_event(struct perf_event *event) 107 { 108 return is_metric_event(event) || is_slots_event(event); 109 } 110 111 struct amd_nb { 112 int nb_id; /* NorthBridge id */ 113 int refcnt; /* reference count */ 114 struct perf_event *owners[X86_PMC_IDX_MAX]; 115 struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 116 }; 117 118 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 119 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 120 #define PEBS_OUTPUT_OFFSET 61 121 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 122 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 123 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 124 125 /* 126 * Flags PEBS can handle without an PMI. 127 * 128 * TID can only be handled by flushing at context switch. 129 * REGS_USER can be handled for events limited to ring 3. 130 * 131 */ 132 #define LARGE_PEBS_FLAGS \ 133 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 134 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 135 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 136 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 137 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 138 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE) 139 140 #define PEBS_GP_REGS \ 141 ((1ULL << PERF_REG_X86_AX) | \ 142 (1ULL << PERF_REG_X86_BX) | \ 143 (1ULL << PERF_REG_X86_CX) | \ 144 (1ULL << PERF_REG_X86_DX) | \ 145 (1ULL << PERF_REG_X86_DI) | \ 146 (1ULL << PERF_REG_X86_SI) | \ 147 (1ULL << PERF_REG_X86_SP) | \ 148 (1ULL << PERF_REG_X86_BP) | \ 149 (1ULL << PERF_REG_X86_IP) | \ 150 (1ULL << PERF_REG_X86_FLAGS) | \ 151 (1ULL << PERF_REG_X86_R8) | \ 152 (1ULL << PERF_REG_X86_R9) | \ 153 (1ULL << PERF_REG_X86_R10) | \ 154 (1ULL << PERF_REG_X86_R11) | \ 155 (1ULL << PERF_REG_X86_R12) | \ 156 (1ULL << PERF_REG_X86_R13) | \ 157 (1ULL << PERF_REG_X86_R14) | \ 158 (1ULL << PERF_REG_X86_R15)) 159 160 /* 161 * Per register state. 162 */ 163 struct er_account { 164 raw_spinlock_t lock; /* per-core: protect structure */ 165 u64 config; /* extra MSR config */ 166 u64 reg; /* extra MSR number */ 167 atomic_t ref; /* reference count */ 168 }; 169 170 /* 171 * Per core/cpu state 172 * 173 * Used to coordinate shared registers between HT threads or 174 * among events on a single PMU. 175 */ 176 struct intel_shared_regs { 177 struct er_account regs[EXTRA_REG_MAX]; 178 int refcnt; /* per-core: #HT threads */ 179 unsigned core_id; /* per-core: core id */ 180 }; 181 182 enum intel_excl_state_type { 183 INTEL_EXCL_UNUSED = 0, /* counter is unused */ 184 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 185 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 186 }; 187 188 struct intel_excl_states { 189 enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 190 bool sched_started; /* true if scheduling has started */ 191 }; 192 193 struct intel_excl_cntrs { 194 raw_spinlock_t lock; 195 196 struct intel_excl_states states[2]; 197 198 union { 199 u16 has_exclusive[2]; 200 u32 exclusive_present; 201 }; 202 203 int refcnt; /* per-core: #HT threads */ 204 unsigned core_id; /* per-core: core id */ 205 }; 206 207 struct x86_perf_task_context; 208 #define MAX_LBR_ENTRIES 32 209 210 enum { 211 LBR_FORMAT_32 = 0x00, 212 LBR_FORMAT_LIP = 0x01, 213 LBR_FORMAT_EIP = 0x02, 214 LBR_FORMAT_EIP_FLAGS = 0x03, 215 LBR_FORMAT_EIP_FLAGS2 = 0x04, 216 LBR_FORMAT_INFO = 0x05, 217 LBR_FORMAT_TIME = 0x06, 218 LBR_FORMAT_INFO2 = 0x07, 219 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2, 220 }; 221 222 enum { 223 X86_PERF_KFREE_SHARED = 0, 224 X86_PERF_KFREE_EXCL = 1, 225 X86_PERF_KFREE_MAX 226 }; 227 228 struct cpu_hw_events { 229 /* 230 * Generic x86 PMC bits 231 */ 232 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 233 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 234 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 235 int enabled; 236 237 int n_events; /* the # of events in the below arrays */ 238 int n_added; /* the # last events in the below arrays; 239 they've never been enabled yet */ 240 int n_txn; /* the # last events in the below arrays; 241 added in the current transaction */ 242 int n_txn_pair; 243 int n_txn_metric; 244 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 245 u64 tags[X86_PMC_IDX_MAX]; 246 247 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 248 struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 249 250 int n_excl; /* the number of exclusive events */ 251 252 unsigned int txn_flags; 253 int is_fake; 254 255 /* 256 * Intel DebugStore bits 257 */ 258 struct debug_store *ds; 259 void *ds_pebs_vaddr; 260 void *ds_bts_vaddr; 261 u64 pebs_enabled; 262 int n_pebs; 263 int n_large_pebs; 264 int n_pebs_via_pt; 265 int pebs_output; 266 267 /* Current super set of events hardware configuration */ 268 u64 pebs_data_cfg; 269 u64 active_pebs_data_cfg; 270 int pebs_record_size; 271 272 /* 273 * Intel LBR bits 274 */ 275 int lbr_users; 276 int lbr_pebs_users; 277 struct perf_branch_stack lbr_stack; 278 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 279 union { 280 struct er_account *lbr_sel; 281 struct er_account *lbr_ctl; 282 }; 283 u64 br_sel; 284 void *last_task_ctx; 285 int last_log_id; 286 int lbr_select; 287 void *lbr_xsave; 288 289 /* 290 * Intel host/guest exclude bits 291 */ 292 u64 intel_ctrl_guest_mask; 293 u64 intel_ctrl_host_mask; 294 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 295 296 /* 297 * Intel checkpoint mask 298 */ 299 u64 intel_cp_status; 300 301 /* 302 * manage shared (per-core, per-cpu) registers 303 * used on Intel NHM/WSM/SNB 304 */ 305 struct intel_shared_regs *shared_regs; 306 /* 307 * manage exclusive counter access between hyperthread 308 */ 309 struct event_constraint *constraint_list; /* in enable order */ 310 struct intel_excl_cntrs *excl_cntrs; 311 int excl_thread_id; /* 0 or 1 */ 312 313 /* 314 * SKL TSX_FORCE_ABORT shadow 315 */ 316 u64 tfa_shadow; 317 318 /* 319 * Perf Metrics 320 */ 321 /* number of accepted metrics events */ 322 int n_metric; 323 324 /* 325 * AMD specific bits 326 */ 327 struct amd_nb *amd_nb; 328 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 329 u64 perf_ctr_virt_mask; 330 int n_pair; /* Large increment events */ 331 332 void *kfree_on_online[X86_PERF_KFREE_MAX]; 333 334 struct pmu *pmu; 335 }; 336 337 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 338 { .idxmsk64 = (n) }, \ 339 .code = (c), \ 340 .size = (e) - (c), \ 341 .cmask = (m), \ 342 .weight = (w), \ 343 .overlap = (o), \ 344 .flags = f, \ 345 } 346 347 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 348 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 349 350 #define EVENT_CONSTRAINT(c, n, m) \ 351 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 352 353 /* 354 * The constraint_match() function only works for 'simple' event codes 355 * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 356 */ 357 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 358 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 359 360 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 361 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 362 0, PERF_X86_EVENT_EXCL) 363 364 /* 365 * The overlap flag marks event constraints with overlapping counter 366 * masks. This is the case if the counter mask of such an event is not 367 * a subset of any other counter mask of a constraint with an equal or 368 * higher weight, e.g.: 369 * 370 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 371 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 372 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 373 * 374 * The event scheduler may not select the correct counter in the first 375 * cycle because it needs to know which subsequent events will be 376 * scheduled. It may fail to schedule the events then. So we set the 377 * overlap flag for such constraints to give the scheduler a hint which 378 * events to select for counter rescheduling. 379 * 380 * Care must be taken as the rescheduling algorithm is O(n!) which 381 * will increase scheduling cycles for an over-committed system 382 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 383 * and its counter masks must be kept at a minimum. 384 */ 385 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 386 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 387 388 /* 389 * Constraint on the Event code. 390 */ 391 #define INTEL_EVENT_CONSTRAINT(c, n) \ 392 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 393 394 /* 395 * Constraint on a range of Event codes 396 */ 397 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 398 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 399 400 /* 401 * Constraint on the Event code + UMask + fixed-mask 402 * 403 * filter mask to validate fixed counter events. 404 * the following filters disqualify for fixed counters: 405 * - inv 406 * - edge 407 * - cnt-mask 408 * - in_tx 409 * - in_tx_checkpointed 410 * The other filters are supported by fixed counters. 411 * The any-thread option is supported starting with v3. 412 */ 413 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 414 #define FIXED_EVENT_CONSTRAINT(c, n) \ 415 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 416 417 /* 418 * The special metric counters do not actually exist. They are calculated from 419 * the combination of the FxCtr3 + MSR_PERF_METRICS. 420 * 421 * The special metric counters are mapped to a dummy offset for the scheduler. 422 * The sharing between multiple users of the same metric without multiplexing 423 * is not allowed, even though the hardware supports that in principle. 424 */ 425 426 #define METRIC_EVENT_CONSTRAINT(c, n) \ 427 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 428 INTEL_ARCH_EVENT_MASK) 429 430 /* 431 * Constraint on the Event code + UMask 432 */ 433 #define INTEL_UEVENT_CONSTRAINT(c, n) \ 434 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 435 436 /* Constraint on specific umask bit only + event */ 437 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 438 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 439 440 /* Like UEVENT_CONSTRAINT, but match flags too */ 441 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 442 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 443 444 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 445 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 446 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 447 448 #define INTEL_PLD_CONSTRAINT(c, n) \ 449 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 450 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 451 452 #define INTEL_PSD_CONSTRAINT(c, n) \ 453 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 454 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT) 455 456 #define INTEL_PST_CONSTRAINT(c, n) \ 457 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 458 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 459 460 /* Event constraint, but match on all event flags too. */ 461 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 462 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 463 464 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 465 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 466 467 /* Check only flags, but allow all event/umask */ 468 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 469 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 470 471 /* Check flags and event code, and set the HSW store flag */ 472 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 473 __EVENT_CONSTRAINT(code, n, \ 474 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 475 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 476 477 /* Check flags and event code, and set the HSW load flag */ 478 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 479 __EVENT_CONSTRAINT(code, n, \ 480 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 481 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 482 483 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 484 __EVENT_CONSTRAINT_RANGE(code, end, n, \ 485 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 486 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 487 488 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 489 __EVENT_CONSTRAINT(code, n, \ 490 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 491 HWEIGHT(n), 0, \ 492 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 493 494 /* Check flags and event code/umask, and set the HSW store flag */ 495 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 496 __EVENT_CONSTRAINT(code, n, \ 497 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 498 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 499 500 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 501 __EVENT_CONSTRAINT(code, n, \ 502 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 503 HWEIGHT(n), 0, \ 504 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 505 506 /* Check flags and event code/umask, and set the HSW load flag */ 507 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 508 __EVENT_CONSTRAINT(code, n, \ 509 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 510 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 511 512 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 513 __EVENT_CONSTRAINT(code, n, \ 514 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 515 HWEIGHT(n), 0, \ 516 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 517 518 /* Check flags and event code/umask, and set the HSW N/A flag */ 519 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 520 __EVENT_CONSTRAINT(code, n, \ 521 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 522 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 523 524 525 /* 526 * We define the end marker as having a weight of -1 527 * to enable blacklisting of events using a counter bitmask 528 * of zero and thus a weight of zero. 529 * The end marker has a weight that cannot possibly be 530 * obtained from counting the bits in the bitmask. 531 */ 532 #define EVENT_CONSTRAINT_END { .weight = -1 } 533 534 /* 535 * Check for end marker with weight == -1 536 */ 537 #define for_each_event_constraint(e, c) \ 538 for ((e) = (c); (e)->weight != -1; (e)++) 539 540 /* 541 * Extra registers for specific events. 542 * 543 * Some events need large masks and require external MSRs. 544 * Those extra MSRs end up being shared for all events on 545 * a PMU and sometimes between PMU of sibling HT threads. 546 * In either case, the kernel needs to handle conflicting 547 * accesses to those extra, shared, regs. The data structure 548 * to manage those registers is stored in cpu_hw_event. 549 */ 550 struct extra_reg { 551 unsigned int event; 552 unsigned int msr; 553 u64 config_mask; 554 u64 valid_mask; 555 int idx; /* per_xxx->regs[] reg index */ 556 bool extra_msr_access; 557 }; 558 559 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 560 .event = (e), \ 561 .msr = (ms), \ 562 .config_mask = (m), \ 563 .valid_mask = (vm), \ 564 .idx = EXTRA_REG_##i, \ 565 .extra_msr_access = true, \ 566 } 567 568 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 569 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 570 571 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 572 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 573 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 574 575 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 576 INTEL_UEVENT_EXTRA_REG(c, \ 577 MSR_PEBS_LD_LAT_THRESHOLD, \ 578 0xffff, \ 579 LDLAT) 580 581 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 582 583 union perf_capabilities { 584 struct { 585 u64 lbr_format:6; 586 u64 pebs_trap:1; 587 u64 pebs_arch_reg:1; 588 u64 pebs_format:4; 589 u64 smm_freeze:1; 590 /* 591 * PMU supports separate counter range for writing 592 * values > 32bit. 593 */ 594 u64 full_width_write:1; 595 u64 pebs_baseline:1; 596 u64 perf_metrics:1; 597 u64 pebs_output_pt_available:1; 598 u64 anythread_deprecated:1; 599 }; 600 u64 capabilities; 601 }; 602 603 struct x86_pmu_quirk { 604 struct x86_pmu_quirk *next; 605 void (*func)(void); 606 }; 607 608 union x86_pmu_config { 609 struct { 610 u64 event:8, 611 umask:8, 612 usr:1, 613 os:1, 614 edge:1, 615 pc:1, 616 interrupt:1, 617 __reserved1:1, 618 en:1, 619 inv:1, 620 cmask:8, 621 event2:4, 622 __reserved2:4, 623 go:1, 624 ho:1; 625 } bits; 626 u64 value; 627 }; 628 629 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 630 631 enum { 632 x86_lbr_exclusive_lbr, 633 x86_lbr_exclusive_bts, 634 x86_lbr_exclusive_pt, 635 x86_lbr_exclusive_max, 636 }; 637 638 struct x86_hybrid_pmu { 639 struct pmu pmu; 640 const char *name; 641 u8 cpu_type; 642 cpumask_t supported_cpus; 643 union perf_capabilities intel_cap; 644 u64 intel_ctrl; 645 int max_pebs_events; 646 int num_counters; 647 int num_counters_fixed; 648 struct event_constraint unconstrained; 649 650 u64 hw_cache_event_ids 651 [PERF_COUNT_HW_CACHE_MAX] 652 [PERF_COUNT_HW_CACHE_OP_MAX] 653 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 654 u64 hw_cache_extra_regs 655 [PERF_COUNT_HW_CACHE_MAX] 656 [PERF_COUNT_HW_CACHE_OP_MAX] 657 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 658 struct event_constraint *event_constraints; 659 struct event_constraint *pebs_constraints; 660 struct extra_reg *extra_regs; 661 662 unsigned int late_ack :1, 663 mid_ack :1, 664 enabled_ack :1; 665 }; 666 667 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) 668 { 669 return container_of(pmu, struct x86_hybrid_pmu, pmu); 670 } 671 672 extern struct static_key_false perf_is_hybrid; 673 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid) 674 675 #define hybrid(_pmu, _field) \ 676 (*({ \ 677 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \ 678 \ 679 if (is_hybrid() && (_pmu)) \ 680 __Fp = &hybrid_pmu(_pmu)->_field; \ 681 \ 682 __Fp; \ 683 })) 684 685 #define hybrid_var(_pmu, _var) \ 686 (*({ \ 687 typeof(&_var) __Fp = &_var; \ 688 \ 689 if (is_hybrid() && (_pmu)) \ 690 __Fp = &hybrid_pmu(_pmu)->_var; \ 691 \ 692 __Fp; \ 693 })) 694 695 #define hybrid_bit(_pmu, _field) \ 696 ({ \ 697 bool __Fp = x86_pmu._field; \ 698 \ 699 if (is_hybrid() && (_pmu)) \ 700 __Fp = hybrid_pmu(_pmu)->_field; \ 701 \ 702 __Fp; \ 703 }) 704 705 enum hybrid_pmu_type { 706 hybrid_big = 0x40, 707 hybrid_small = 0x20, 708 709 hybrid_big_small = hybrid_big | hybrid_small, 710 }; 711 712 #define X86_HYBRID_PMU_ATOM_IDX 0 713 #define X86_HYBRID_PMU_CORE_IDX 1 714 715 #define X86_HYBRID_NUM_PMUS 2 716 717 /* 718 * struct x86_pmu - generic x86 pmu 719 */ 720 struct x86_pmu { 721 /* 722 * Generic x86 PMC bits 723 */ 724 const char *name; 725 int version; 726 int (*handle_irq)(struct pt_regs *); 727 void (*disable_all)(void); 728 void (*enable_all)(int added); 729 void (*enable)(struct perf_event *); 730 void (*disable)(struct perf_event *); 731 void (*assign)(struct perf_event *event, int idx); 732 void (*add)(struct perf_event *); 733 void (*del)(struct perf_event *); 734 void (*read)(struct perf_event *event); 735 int (*hw_config)(struct perf_event *event); 736 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 737 unsigned eventsel; 738 unsigned perfctr; 739 int (*addr_offset)(int index, bool eventsel); 740 int (*rdpmc_index)(int index); 741 u64 (*event_map)(int); 742 int max_events; 743 int num_counters; 744 int num_counters_fixed; 745 int cntval_bits; 746 u64 cntval_mask; 747 union { 748 unsigned long events_maskl; 749 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 750 }; 751 int events_mask_len; 752 int apic; 753 u64 max_period; 754 struct event_constraint * 755 (*get_event_constraints)(struct cpu_hw_events *cpuc, 756 int idx, 757 struct perf_event *event); 758 759 void (*put_event_constraints)(struct cpu_hw_events *cpuc, 760 struct perf_event *event); 761 762 void (*start_scheduling)(struct cpu_hw_events *cpuc); 763 764 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 765 766 void (*stop_scheduling)(struct cpu_hw_events *cpuc); 767 768 struct event_constraint *event_constraints; 769 struct x86_pmu_quirk *quirks; 770 int perfctr_second_write; 771 u64 (*limit_period)(struct perf_event *event, u64 l); 772 773 /* PMI handler bits */ 774 unsigned int late_ack :1, 775 mid_ack :1, 776 enabled_ack :1; 777 /* 778 * sysfs attrs 779 */ 780 int attr_rdpmc_broken; 781 int attr_rdpmc; 782 struct attribute **format_attrs; 783 784 ssize_t (*events_sysfs_show)(char *page, u64 config); 785 const struct attribute_group **attr_update; 786 787 unsigned long attr_freeze_on_smi; 788 789 /* 790 * CPU Hotplug hooks 791 */ 792 int (*cpu_prepare)(int cpu); 793 void (*cpu_starting)(int cpu); 794 void (*cpu_dying)(int cpu); 795 void (*cpu_dead)(int cpu); 796 797 void (*check_microcode)(void); 798 void (*sched_task)(struct perf_event_context *ctx, 799 bool sched_in); 800 801 /* 802 * Intel Arch Perfmon v2+ 803 */ 804 u64 intel_ctrl; 805 union perf_capabilities intel_cap; 806 807 /* 808 * Intel DebugStore bits 809 */ 810 unsigned int bts :1, 811 bts_active :1, 812 pebs :1, 813 pebs_active :1, 814 pebs_broken :1, 815 pebs_prec_dist :1, 816 pebs_no_tlb :1, 817 pebs_no_isolation :1, 818 pebs_block :1; 819 int pebs_record_size; 820 int pebs_buffer_size; 821 int max_pebs_events; 822 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 823 struct event_constraint *pebs_constraints; 824 void (*pebs_aliases)(struct perf_event *event); 825 unsigned long large_pebs_flags; 826 u64 rtm_abort_event; 827 828 /* 829 * Intel LBR 830 */ 831 unsigned int lbr_tos, lbr_from, lbr_to, 832 lbr_info, lbr_nr; /* LBR base regs and size */ 833 union { 834 u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 835 u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 836 }; 837 union { 838 const int *lbr_sel_map; /* lbr_select mappings */ 839 int *lbr_ctl_map; /* LBR_CTL mappings */ 840 }; 841 bool lbr_double_abort; /* duplicated lbr aborts */ 842 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 843 844 unsigned int lbr_has_info:1; 845 unsigned int lbr_has_tsx:1; 846 unsigned int lbr_from_flags:1; 847 unsigned int lbr_to_cycles:1; 848 849 /* 850 * Intel Architectural LBR CPUID Enumeration 851 */ 852 unsigned int lbr_depth_mask:8; 853 unsigned int lbr_deep_c_reset:1; 854 unsigned int lbr_lip:1; 855 unsigned int lbr_cpl:1; 856 unsigned int lbr_filter:1; 857 unsigned int lbr_call_stack:1; 858 unsigned int lbr_mispred:1; 859 unsigned int lbr_timed_lbr:1; 860 unsigned int lbr_br_type:1; 861 862 void (*lbr_reset)(void); 863 void (*lbr_read)(struct cpu_hw_events *cpuc); 864 void (*lbr_save)(void *ctx); 865 void (*lbr_restore)(void *ctx); 866 867 /* 868 * Intel PT/LBR/BTS are exclusive 869 */ 870 atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 871 872 /* 873 * Intel perf metrics 874 */ 875 int num_topdown_events; 876 u64 (*update_topdown_event)(struct perf_event *event); 877 int (*set_topdown_event_period)(struct perf_event *event); 878 879 /* 880 * perf task context (i.e. struct perf_event_context::task_ctx_data) 881 * switch helper to bridge calls from perf/core to perf/x86. 882 * See struct pmu::swap_task_ctx() usage for examples; 883 */ 884 void (*swap_task_ctx)(struct perf_event_context *prev, 885 struct perf_event_context *next); 886 887 /* 888 * AMD bits 889 */ 890 unsigned int amd_nb_constraints : 1; 891 u64 perf_ctr_pair_en; 892 893 /* 894 * Extra registers for events 895 */ 896 struct extra_reg *extra_regs; 897 unsigned int flags; 898 899 /* 900 * Intel host/guest support (KVM) 901 */ 902 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); 903 904 /* 905 * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 906 */ 907 int (*check_period) (struct perf_event *event, u64 period); 908 909 int (*aux_output_match) (struct perf_event *event); 910 911 int (*filter_match)(struct perf_event *event); 912 /* 913 * Hybrid support 914 * 915 * Most PMU capabilities are the same among different hybrid PMUs. 916 * The global x86_pmu saves the architecture capabilities, which 917 * are available for all PMUs. The hybrid_pmu only includes the 918 * unique capabilities. 919 */ 920 int num_hybrid_pmus; 921 struct x86_hybrid_pmu *hybrid_pmu; 922 u8 (*get_hybrid_cpu_type) (void); 923 }; 924 925 struct x86_perf_task_context_opt { 926 int lbr_callstack_users; 927 int lbr_stack_state; 928 int log_id; 929 }; 930 931 struct x86_perf_task_context { 932 u64 lbr_sel; 933 int tos; 934 int valid_lbrs; 935 struct x86_perf_task_context_opt opt; 936 struct lbr_entry lbr[MAX_LBR_ENTRIES]; 937 }; 938 939 struct x86_perf_task_context_arch_lbr { 940 struct x86_perf_task_context_opt opt; 941 struct lbr_entry entries[]; 942 }; 943 944 /* 945 * Add padding to guarantee the 64-byte alignment of the state buffer. 946 * 947 * The structure is dynamically allocated. The size of the LBR state may vary 948 * based on the number of LBR registers. 949 * 950 * Do not put anything after the LBR state. 951 */ 952 struct x86_perf_task_context_arch_lbr_xsave { 953 struct x86_perf_task_context_opt opt; 954 955 union { 956 struct xregs_state xsave; 957 struct { 958 struct fxregs_state i387; 959 struct xstate_header header; 960 struct arch_lbr_state lbr; 961 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 962 }; 963 }; 964 965 #define x86_add_quirk(func_) \ 966 do { \ 967 static struct x86_pmu_quirk __quirk __initdata = { \ 968 .func = func_, \ 969 }; \ 970 __quirk.next = x86_pmu.quirks; \ 971 x86_pmu.quirks = &__quirk; \ 972 } while (0) 973 974 /* 975 * x86_pmu flags 976 */ 977 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 978 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 979 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 980 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 981 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 982 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 983 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 984 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ 985 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ 986 987 #define EVENT_VAR(_id) event_attr_##_id 988 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 989 990 #define EVENT_ATTR(_name, _id) \ 991 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 992 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 993 .id = PERF_COUNT_HW_##_id, \ 994 .event_str = NULL, \ 995 }; 996 997 #define EVENT_ATTR_STR(_name, v, str) \ 998 static struct perf_pmu_events_attr event_attr_##v = { \ 999 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1000 .id = 0, \ 1001 .event_str = str, \ 1002 }; 1003 1004 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 1005 static struct perf_pmu_events_ht_attr event_attr_##v = { \ 1006 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 1007 .id = 0, \ 1008 .event_str_noht = noht, \ 1009 .event_str_ht = ht, \ 1010 } 1011 1012 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \ 1013 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \ 1014 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\ 1015 .id = 0, \ 1016 .event_str = str, \ 1017 .pmu_type = _pmu, \ 1018 } 1019 1020 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr) 1021 1022 #define FORMAT_ATTR_HYBRID(_name, _pmu) \ 1023 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\ 1024 .attr = __ATTR_RO(_name), \ 1025 .pmu_type = _pmu, \ 1026 } 1027 1028 struct pmu *x86_get_pmu(unsigned int cpu); 1029 extern struct x86_pmu x86_pmu __read_mostly; 1030 1031 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 1032 { 1033 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 1034 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 1035 1036 return &((struct x86_perf_task_context *)ctx)->opt; 1037 } 1038 1039 static inline bool x86_pmu_has_lbr_callstack(void) 1040 { 1041 return x86_pmu.lbr_sel_map && 1042 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 1043 } 1044 1045 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 1046 1047 int x86_perf_event_set_period(struct perf_event *event); 1048 1049 /* 1050 * Generalized hw caching related hw_event table, filled 1051 * in on a per model basis. A value of 0 means 1052 * 'not supported', -1 means 'hw_event makes no sense on 1053 * this CPU', any other value means the raw hw_event 1054 * ID. 1055 */ 1056 1057 #define C(x) PERF_COUNT_HW_CACHE_##x 1058 1059 extern u64 __read_mostly hw_cache_event_ids 1060 [PERF_COUNT_HW_CACHE_MAX] 1061 [PERF_COUNT_HW_CACHE_OP_MAX] 1062 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1063 extern u64 __read_mostly hw_cache_extra_regs 1064 [PERF_COUNT_HW_CACHE_MAX] 1065 [PERF_COUNT_HW_CACHE_OP_MAX] 1066 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1067 1068 u64 x86_perf_event_update(struct perf_event *event); 1069 1070 static inline unsigned int x86_pmu_config_addr(int index) 1071 { 1072 return x86_pmu.eventsel + (x86_pmu.addr_offset ? 1073 x86_pmu.addr_offset(index, true) : index); 1074 } 1075 1076 static inline unsigned int x86_pmu_event_addr(int index) 1077 { 1078 return x86_pmu.perfctr + (x86_pmu.addr_offset ? 1079 x86_pmu.addr_offset(index, false) : index); 1080 } 1081 1082 static inline int x86_pmu_rdpmc_index(int index) 1083 { 1084 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 1085 } 1086 1087 bool check_hw_exists(struct pmu *pmu, int num_counters, 1088 int num_counters_fixed); 1089 1090 int x86_add_exclusive(unsigned int what); 1091 1092 void x86_del_exclusive(unsigned int what); 1093 1094 int x86_reserve_hardware(void); 1095 1096 void x86_release_hardware(void); 1097 1098 int x86_pmu_max_precise(void); 1099 1100 void hw_perf_lbr_event_destroy(struct perf_event *event); 1101 1102 int x86_setup_perfctr(struct perf_event *event); 1103 1104 int x86_pmu_hw_config(struct perf_event *event); 1105 1106 void x86_pmu_disable_all(void); 1107 1108 static inline bool is_counter_pair(struct hw_perf_event *hwc) 1109 { 1110 return hwc->flags & PERF_X86_EVENT_PAIR; 1111 } 1112 1113 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 1114 u64 enable_mask) 1115 { 1116 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1117 1118 if (hwc->extra_reg.reg) 1119 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 1120 1121 /* 1122 * Add enabled Merge event on next counter 1123 * if large increment event being enabled on this counter 1124 */ 1125 if (is_counter_pair(hwc)) 1126 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 1127 1128 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 1129 } 1130 1131 void x86_pmu_enable_all(int added); 1132 1133 int perf_assign_events(struct event_constraint **constraints, int n, 1134 int wmin, int wmax, int gpmax, int *assign); 1135 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 1136 1137 void x86_pmu_stop(struct perf_event *event, int flags); 1138 1139 static inline void x86_pmu_disable_event(struct perf_event *event) 1140 { 1141 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1142 struct hw_perf_event *hwc = &event->hw; 1143 1144 wrmsrl(hwc->config_base, hwc->config & ~disable_mask); 1145 1146 if (is_counter_pair(hwc)) 1147 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 1148 } 1149 1150 void x86_pmu_enable_event(struct perf_event *event); 1151 1152 int x86_pmu_handle_irq(struct pt_regs *regs); 1153 1154 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed, 1155 u64 intel_ctrl); 1156 1157 void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu); 1158 1159 extern struct event_constraint emptyconstraint; 1160 1161 extern struct event_constraint unconstrained; 1162 1163 static inline bool kernel_ip(unsigned long ip) 1164 { 1165 #ifdef CONFIG_X86_32 1166 return ip > PAGE_OFFSET; 1167 #else 1168 return (long)ip < 0; 1169 #endif 1170 } 1171 1172 /* 1173 * Not all PMUs provide the right context information to place the reported IP 1174 * into full context. Specifically segment registers are typically not 1175 * supplied. 1176 * 1177 * Assuming the address is a linear address (it is for IBS), we fake the CS and 1178 * vm86 mode using the known zero-based code segment and 'fix up' the registers 1179 * to reflect this. 1180 * 1181 * Intel PEBS/LBR appear to typically provide the effective address, nothing 1182 * much we can do about that but pray and treat it like a linear address. 1183 */ 1184 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 1185 { 1186 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 1187 if (regs->flags & X86_VM_MASK) 1188 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 1189 regs->ip = ip; 1190 } 1191 1192 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 1193 ssize_t intel_event_sysfs_show(char *page, u64 config); 1194 1195 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1196 char *page); 1197 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1198 char *page); 1199 ssize_t events_hybrid_sysfs_show(struct device *dev, 1200 struct device_attribute *attr, 1201 char *page); 1202 1203 static inline bool fixed_counter_disabled(int i, struct pmu *pmu) 1204 { 1205 u64 intel_ctrl = hybrid(pmu, intel_ctrl); 1206 1207 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); 1208 } 1209 1210 #ifdef CONFIG_CPU_SUP_AMD 1211 1212 int amd_pmu_init(void); 1213 1214 #else /* CONFIG_CPU_SUP_AMD */ 1215 1216 static inline int amd_pmu_init(void) 1217 { 1218 return 0; 1219 } 1220 1221 #endif /* CONFIG_CPU_SUP_AMD */ 1222 1223 static inline int is_pebs_pt(struct perf_event *event) 1224 { 1225 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 1226 } 1227 1228 #ifdef CONFIG_CPU_SUP_INTEL 1229 1230 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 1231 { 1232 struct hw_perf_event *hwc = &event->hw; 1233 unsigned int hw_event, bts_event; 1234 1235 if (event->attr.freq) 1236 return false; 1237 1238 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 1239 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 1240 1241 return hw_event == bts_event && period == 1; 1242 } 1243 1244 static inline bool intel_pmu_has_bts(struct perf_event *event) 1245 { 1246 struct hw_perf_event *hwc = &event->hw; 1247 1248 return intel_pmu_has_bts_period(event, hwc->sample_period); 1249 } 1250 1251 static __always_inline void __intel_pmu_pebs_disable_all(void) 1252 { 1253 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 1254 } 1255 1256 static __always_inline void __intel_pmu_arch_lbr_disable(void) 1257 { 1258 wrmsrl(MSR_ARCH_LBR_CTL, 0); 1259 } 1260 1261 static __always_inline void __intel_pmu_lbr_disable(void) 1262 { 1263 u64 debugctl; 1264 1265 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1266 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1267 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1268 } 1269 1270 int intel_pmu_save_and_restart(struct perf_event *event); 1271 1272 struct event_constraint * 1273 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 1274 struct perf_event *event); 1275 1276 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1277 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 1278 1279 int intel_pmu_init(void); 1280 1281 void init_debug_store_on_cpu(int cpu); 1282 1283 void fini_debug_store_on_cpu(int cpu); 1284 1285 void release_ds_buffers(void); 1286 1287 void reserve_ds_buffers(void); 1288 1289 void release_lbr_buffers(void); 1290 1291 void reserve_lbr_buffers(void); 1292 1293 extern struct event_constraint bts_constraint; 1294 extern struct event_constraint vlbr_constraint; 1295 1296 void intel_pmu_enable_bts(u64 config); 1297 1298 void intel_pmu_disable_bts(void); 1299 1300 int intel_pmu_drain_bts_buffer(void); 1301 1302 extern struct event_constraint intel_core2_pebs_event_constraints[]; 1303 1304 extern struct event_constraint intel_atom_pebs_event_constraints[]; 1305 1306 extern struct event_constraint intel_slm_pebs_event_constraints[]; 1307 1308 extern struct event_constraint intel_glm_pebs_event_constraints[]; 1309 1310 extern struct event_constraint intel_glp_pebs_event_constraints[]; 1311 1312 extern struct event_constraint intel_grt_pebs_event_constraints[]; 1313 1314 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1315 1316 extern struct event_constraint intel_westmere_pebs_event_constraints[]; 1317 1318 extern struct event_constraint intel_snb_pebs_event_constraints[]; 1319 1320 extern struct event_constraint intel_ivb_pebs_event_constraints[]; 1321 1322 extern struct event_constraint intel_hsw_pebs_event_constraints[]; 1323 1324 extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1325 1326 extern struct event_constraint intel_skl_pebs_event_constraints[]; 1327 1328 extern struct event_constraint intel_icl_pebs_event_constraints[]; 1329 1330 extern struct event_constraint intel_spr_pebs_event_constraints[]; 1331 1332 struct event_constraint *intel_pebs_constraints(struct perf_event *event); 1333 1334 void intel_pmu_pebs_add(struct perf_event *event); 1335 1336 void intel_pmu_pebs_del(struct perf_event *event); 1337 1338 void intel_pmu_pebs_enable(struct perf_event *event); 1339 1340 void intel_pmu_pebs_disable(struct perf_event *event); 1341 1342 void intel_pmu_pebs_enable_all(void); 1343 1344 void intel_pmu_pebs_disable_all(void); 1345 1346 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); 1347 1348 void intel_pmu_auto_reload_read(struct perf_event *event); 1349 1350 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1351 1352 void intel_ds_init(void); 1353 1354 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 1355 struct perf_event_context *next); 1356 1357 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); 1358 1359 u64 lbr_from_signext_quirk_wr(u64 val); 1360 1361 void intel_pmu_lbr_reset(void); 1362 1363 void intel_pmu_lbr_reset_32(void); 1364 1365 void intel_pmu_lbr_reset_64(void); 1366 1367 void intel_pmu_lbr_add(struct perf_event *event); 1368 1369 void intel_pmu_lbr_del(struct perf_event *event); 1370 1371 void intel_pmu_lbr_enable_all(bool pmi); 1372 1373 void intel_pmu_lbr_disable_all(void); 1374 1375 void intel_pmu_lbr_read(void); 1376 1377 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1378 1379 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1380 1381 void intel_pmu_lbr_save(void *ctx); 1382 1383 void intel_pmu_lbr_restore(void *ctx); 1384 1385 void intel_pmu_lbr_init_core(void); 1386 1387 void intel_pmu_lbr_init_nhm(void); 1388 1389 void intel_pmu_lbr_init_atom(void); 1390 1391 void intel_pmu_lbr_init_slm(void); 1392 1393 void intel_pmu_lbr_init_snb(void); 1394 1395 void intel_pmu_lbr_init_hsw(void); 1396 1397 void intel_pmu_lbr_init_skl(void); 1398 1399 void intel_pmu_lbr_init_knl(void); 1400 1401 void intel_pmu_lbr_init(void); 1402 1403 void intel_pmu_arch_lbr_init(void); 1404 1405 void intel_pmu_pebs_data_source_nhm(void); 1406 1407 void intel_pmu_pebs_data_source_skl(bool pmem); 1408 1409 int intel_pmu_setup_lbr_filter(struct perf_event *event); 1410 1411 void intel_pt_interrupt(void); 1412 1413 int intel_bts_interrupt(void); 1414 1415 void intel_bts_enable_local(void); 1416 1417 void intel_bts_disable_local(void); 1418 1419 int p4_pmu_init(void); 1420 1421 int p6_pmu_init(void); 1422 1423 int knc_pmu_init(void); 1424 1425 static inline int is_ht_workaround_enabled(void) 1426 { 1427 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 1428 } 1429 1430 #else /* CONFIG_CPU_SUP_INTEL */ 1431 1432 static inline void reserve_ds_buffers(void) 1433 { 1434 } 1435 1436 static inline void release_ds_buffers(void) 1437 { 1438 } 1439 1440 static inline void release_lbr_buffers(void) 1441 { 1442 } 1443 1444 static inline void reserve_lbr_buffers(void) 1445 { 1446 } 1447 1448 static inline int intel_pmu_init(void) 1449 { 1450 return 0; 1451 } 1452 1453 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 1454 { 1455 return 0; 1456 } 1457 1458 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1459 { 1460 } 1461 1462 static inline int is_ht_workaround_enabled(void) 1463 { 1464 return 0; 1465 } 1466 #endif /* CONFIG_CPU_SUP_INTEL */ 1467 1468 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 1469 int zhaoxin_pmu_init(void); 1470 #else 1471 static inline int zhaoxin_pmu_init(void) 1472 { 1473 return 0; 1474 } 1475 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1476