1 /* 2 * Performance events x86 architecture header 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 17 #include <asm/intel_ds.h> 18 19 /* To enable MSR tracing please use the generic trace points. */ 20 21 /* 22 * | NHM/WSM | SNB | 23 * register ------------------------------- 24 * | HT | no HT | HT | no HT | 25 *----------------------------------------- 26 * offcore | core | core | cpu | core | 27 * lbr_sel | core | core | cpu | core | 28 * ld_lat | cpu | core | cpu | core | 29 *----------------------------------------- 30 * 31 * Given that there is a small number of shared regs, 32 * we can pre-allocate their slot in the per-cpu 33 * per-core reg tables. 34 */ 35 enum extra_reg_type { 36 EXTRA_REG_NONE = -1, /* not used */ 37 38 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 39 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 40 EXTRA_REG_LBR = 2, /* lbr_select */ 41 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 42 EXTRA_REG_FE = 4, /* fe_* */ 43 44 EXTRA_REG_MAX /* number of entries needed */ 45 }; 46 47 struct event_constraint { 48 union { 49 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 50 u64 idxmsk64; 51 }; 52 u64 code; 53 u64 cmask; 54 int weight; 55 int overlap; 56 int flags; 57 unsigned int size; 58 }; 59 60 static inline bool constraint_match(struct event_constraint *c, u64 ecode) 61 { 62 return ((ecode & c->cmask) - c->code) <= (u64)c->size; 63 } 64 65 /* 66 * struct hw_perf_event.flags flags 67 */ 68 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ 69 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ 70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ 71 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */ 72 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */ 73 #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */ 74 #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */ 75 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */ 76 #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */ 77 #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */ 78 #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */ 79 #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */ 80 #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */ 81 #define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */ 82 #define PERF_X86_EVENT_TOPDOWN 0x4000 /* Count Topdown slots/metrics events */ 83 84 static inline bool is_topdown_count(struct perf_event *event) 85 { 86 return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 87 } 88 89 static inline bool is_metric_event(struct perf_event *event) 90 { 91 u64 config = event->attr.config; 92 93 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 94 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 95 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 96 } 97 98 static inline bool is_slots_event(struct perf_event *event) 99 { 100 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 101 } 102 103 static inline bool is_topdown_event(struct perf_event *event) 104 { 105 return is_metric_event(event) || is_slots_event(event); 106 } 107 108 struct amd_nb { 109 int nb_id; /* NorthBridge id */ 110 int refcnt; /* reference count */ 111 struct perf_event *owners[X86_PMC_IDX_MAX]; 112 struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 113 }; 114 115 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 116 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 117 #define PEBS_OUTPUT_OFFSET 61 118 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 119 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 120 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 121 122 /* 123 * Flags PEBS can handle without an PMI. 124 * 125 * TID can only be handled by flushing at context switch. 126 * REGS_USER can be handled for events limited to ring 3. 127 * 128 */ 129 #define LARGE_PEBS_FLAGS \ 130 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 131 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 132 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 133 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 134 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 135 PERF_SAMPLE_PERIOD) 136 137 #define PEBS_GP_REGS \ 138 ((1ULL << PERF_REG_X86_AX) | \ 139 (1ULL << PERF_REG_X86_BX) | \ 140 (1ULL << PERF_REG_X86_CX) | \ 141 (1ULL << PERF_REG_X86_DX) | \ 142 (1ULL << PERF_REG_X86_DI) | \ 143 (1ULL << PERF_REG_X86_SI) | \ 144 (1ULL << PERF_REG_X86_SP) | \ 145 (1ULL << PERF_REG_X86_BP) | \ 146 (1ULL << PERF_REG_X86_IP) | \ 147 (1ULL << PERF_REG_X86_FLAGS) | \ 148 (1ULL << PERF_REG_X86_R8) | \ 149 (1ULL << PERF_REG_X86_R9) | \ 150 (1ULL << PERF_REG_X86_R10) | \ 151 (1ULL << PERF_REG_X86_R11) | \ 152 (1ULL << PERF_REG_X86_R12) | \ 153 (1ULL << PERF_REG_X86_R13) | \ 154 (1ULL << PERF_REG_X86_R14) | \ 155 (1ULL << PERF_REG_X86_R15)) 156 157 /* 158 * Per register state. 159 */ 160 struct er_account { 161 raw_spinlock_t lock; /* per-core: protect structure */ 162 u64 config; /* extra MSR config */ 163 u64 reg; /* extra MSR number */ 164 atomic_t ref; /* reference count */ 165 }; 166 167 /* 168 * Per core/cpu state 169 * 170 * Used to coordinate shared registers between HT threads or 171 * among events on a single PMU. 172 */ 173 struct intel_shared_regs { 174 struct er_account regs[EXTRA_REG_MAX]; 175 int refcnt; /* per-core: #HT threads */ 176 unsigned core_id; /* per-core: core id */ 177 }; 178 179 enum intel_excl_state_type { 180 INTEL_EXCL_UNUSED = 0, /* counter is unused */ 181 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 182 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 183 }; 184 185 struct intel_excl_states { 186 enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 187 bool sched_started; /* true if scheduling has started */ 188 }; 189 190 struct intel_excl_cntrs { 191 raw_spinlock_t lock; 192 193 struct intel_excl_states states[2]; 194 195 union { 196 u16 has_exclusive[2]; 197 u32 exclusive_present; 198 }; 199 200 int refcnt; /* per-core: #HT threads */ 201 unsigned core_id; /* per-core: core id */ 202 }; 203 204 struct x86_perf_task_context; 205 #define MAX_LBR_ENTRIES 32 206 207 enum { 208 LBR_FORMAT_32 = 0x00, 209 LBR_FORMAT_LIP = 0x01, 210 LBR_FORMAT_EIP = 0x02, 211 LBR_FORMAT_EIP_FLAGS = 0x03, 212 LBR_FORMAT_EIP_FLAGS2 = 0x04, 213 LBR_FORMAT_INFO = 0x05, 214 LBR_FORMAT_TIME = 0x06, 215 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME, 216 }; 217 218 enum { 219 X86_PERF_KFREE_SHARED = 0, 220 X86_PERF_KFREE_EXCL = 1, 221 X86_PERF_KFREE_MAX 222 }; 223 224 struct cpu_hw_events { 225 /* 226 * Generic x86 PMC bits 227 */ 228 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 229 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 230 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 231 int enabled; 232 233 int n_events; /* the # of events in the below arrays */ 234 int n_added; /* the # last events in the below arrays; 235 they've never been enabled yet */ 236 int n_txn; /* the # last events in the below arrays; 237 added in the current transaction */ 238 int n_txn_pair; 239 int n_txn_metric; 240 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 241 u64 tags[X86_PMC_IDX_MAX]; 242 243 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 244 struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 245 246 int n_excl; /* the number of exclusive events */ 247 248 unsigned int txn_flags; 249 int is_fake; 250 251 /* 252 * Intel DebugStore bits 253 */ 254 struct debug_store *ds; 255 void *ds_pebs_vaddr; 256 void *ds_bts_vaddr; 257 u64 pebs_enabled; 258 int n_pebs; 259 int n_large_pebs; 260 int n_pebs_via_pt; 261 int pebs_output; 262 263 /* Current super set of events hardware configuration */ 264 u64 pebs_data_cfg; 265 u64 active_pebs_data_cfg; 266 int pebs_record_size; 267 268 /* 269 * Intel LBR bits 270 */ 271 int lbr_users; 272 int lbr_pebs_users; 273 struct perf_branch_stack lbr_stack; 274 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 275 union { 276 struct er_account *lbr_sel; 277 struct er_account *lbr_ctl; 278 }; 279 u64 br_sel; 280 void *last_task_ctx; 281 int last_log_id; 282 int lbr_select; 283 void *lbr_xsave; 284 285 /* 286 * Intel host/guest exclude bits 287 */ 288 u64 intel_ctrl_guest_mask; 289 u64 intel_ctrl_host_mask; 290 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 291 292 /* 293 * Intel checkpoint mask 294 */ 295 u64 intel_cp_status; 296 297 /* 298 * manage shared (per-core, per-cpu) registers 299 * used on Intel NHM/WSM/SNB 300 */ 301 struct intel_shared_regs *shared_regs; 302 /* 303 * manage exclusive counter access between hyperthread 304 */ 305 struct event_constraint *constraint_list; /* in enable order */ 306 struct intel_excl_cntrs *excl_cntrs; 307 int excl_thread_id; /* 0 or 1 */ 308 309 /* 310 * SKL TSX_FORCE_ABORT shadow 311 */ 312 u64 tfa_shadow; 313 314 /* 315 * Perf Metrics 316 */ 317 /* number of accepted metrics events */ 318 int n_metric; 319 320 /* 321 * AMD specific bits 322 */ 323 struct amd_nb *amd_nb; 324 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 325 u64 perf_ctr_virt_mask; 326 int n_pair; /* Large increment events */ 327 328 void *kfree_on_online[X86_PERF_KFREE_MAX]; 329 }; 330 331 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 332 { .idxmsk64 = (n) }, \ 333 .code = (c), \ 334 .size = (e) - (c), \ 335 .cmask = (m), \ 336 .weight = (w), \ 337 .overlap = (o), \ 338 .flags = f, \ 339 } 340 341 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 342 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 343 344 #define EVENT_CONSTRAINT(c, n, m) \ 345 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 346 347 /* 348 * The constraint_match() function only works for 'simple' event codes 349 * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 350 */ 351 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 352 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 353 354 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 355 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 356 0, PERF_X86_EVENT_EXCL) 357 358 /* 359 * The overlap flag marks event constraints with overlapping counter 360 * masks. This is the case if the counter mask of such an event is not 361 * a subset of any other counter mask of a constraint with an equal or 362 * higher weight, e.g.: 363 * 364 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 365 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 366 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 367 * 368 * The event scheduler may not select the correct counter in the first 369 * cycle because it needs to know which subsequent events will be 370 * scheduled. It may fail to schedule the events then. So we set the 371 * overlap flag for such constraints to give the scheduler a hint which 372 * events to select for counter rescheduling. 373 * 374 * Care must be taken as the rescheduling algorithm is O(n!) which 375 * will increase scheduling cycles for an over-committed system 376 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 377 * and its counter masks must be kept at a minimum. 378 */ 379 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 380 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 381 382 /* 383 * Constraint on the Event code. 384 */ 385 #define INTEL_EVENT_CONSTRAINT(c, n) \ 386 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 387 388 /* 389 * Constraint on a range of Event codes 390 */ 391 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 392 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 393 394 /* 395 * Constraint on the Event code + UMask + fixed-mask 396 * 397 * filter mask to validate fixed counter events. 398 * the following filters disqualify for fixed counters: 399 * - inv 400 * - edge 401 * - cnt-mask 402 * - in_tx 403 * - in_tx_checkpointed 404 * The other filters are supported by fixed counters. 405 * The any-thread option is supported starting with v3. 406 */ 407 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 408 #define FIXED_EVENT_CONSTRAINT(c, n) \ 409 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 410 411 /* 412 * The special metric counters do not actually exist. They are calculated from 413 * the combination of the FxCtr3 + MSR_PERF_METRICS. 414 * 415 * The special metric counters are mapped to a dummy offset for the scheduler. 416 * The sharing between multiple users of the same metric without multiplexing 417 * is not allowed, even though the hardware supports that in principle. 418 */ 419 420 #define METRIC_EVENT_CONSTRAINT(c, n) \ 421 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 422 INTEL_ARCH_EVENT_MASK) 423 424 /* 425 * Constraint on the Event code + UMask 426 */ 427 #define INTEL_UEVENT_CONSTRAINT(c, n) \ 428 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 429 430 /* Constraint on specific umask bit only + event */ 431 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 432 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 433 434 /* Like UEVENT_CONSTRAINT, but match flags too */ 435 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 436 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 437 438 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 439 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 440 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 441 442 #define INTEL_PLD_CONSTRAINT(c, n) \ 443 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 444 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 445 446 #define INTEL_PST_CONSTRAINT(c, n) \ 447 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 448 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 449 450 /* Event constraint, but match on all event flags too. */ 451 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 452 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 453 454 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 455 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 456 457 /* Check only flags, but allow all event/umask */ 458 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 459 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 460 461 /* Check flags and event code, and set the HSW store flag */ 462 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 463 __EVENT_CONSTRAINT(code, n, \ 464 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 465 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 466 467 /* Check flags and event code, and set the HSW load flag */ 468 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 469 __EVENT_CONSTRAINT(code, n, \ 470 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 471 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 472 473 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 474 __EVENT_CONSTRAINT_RANGE(code, end, n, \ 475 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 476 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 477 478 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 479 __EVENT_CONSTRAINT(code, n, \ 480 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 481 HWEIGHT(n), 0, \ 482 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 483 484 /* Check flags and event code/umask, and set the HSW store flag */ 485 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 486 __EVENT_CONSTRAINT(code, n, \ 487 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 488 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 489 490 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 491 __EVENT_CONSTRAINT(code, n, \ 492 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 493 HWEIGHT(n), 0, \ 494 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 495 496 /* Check flags and event code/umask, and set the HSW load flag */ 497 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 498 __EVENT_CONSTRAINT(code, n, \ 499 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 500 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 501 502 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 503 __EVENT_CONSTRAINT(code, n, \ 504 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 505 HWEIGHT(n), 0, \ 506 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 507 508 /* Check flags and event code/umask, and set the HSW N/A flag */ 509 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 510 __EVENT_CONSTRAINT(code, n, \ 511 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 512 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 513 514 515 /* 516 * We define the end marker as having a weight of -1 517 * to enable blacklisting of events using a counter bitmask 518 * of zero and thus a weight of zero. 519 * The end marker has a weight that cannot possibly be 520 * obtained from counting the bits in the bitmask. 521 */ 522 #define EVENT_CONSTRAINT_END { .weight = -1 } 523 524 /* 525 * Check for end marker with weight == -1 526 */ 527 #define for_each_event_constraint(e, c) \ 528 for ((e) = (c); (e)->weight != -1; (e)++) 529 530 /* 531 * Extra registers for specific events. 532 * 533 * Some events need large masks and require external MSRs. 534 * Those extra MSRs end up being shared for all events on 535 * a PMU and sometimes between PMU of sibling HT threads. 536 * In either case, the kernel needs to handle conflicting 537 * accesses to those extra, shared, regs. The data structure 538 * to manage those registers is stored in cpu_hw_event. 539 */ 540 struct extra_reg { 541 unsigned int event; 542 unsigned int msr; 543 u64 config_mask; 544 u64 valid_mask; 545 int idx; /* per_xxx->regs[] reg index */ 546 bool extra_msr_access; 547 }; 548 549 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 550 .event = (e), \ 551 .msr = (ms), \ 552 .config_mask = (m), \ 553 .valid_mask = (vm), \ 554 .idx = EXTRA_REG_##i, \ 555 .extra_msr_access = true, \ 556 } 557 558 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 559 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 560 561 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 562 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 563 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 564 565 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 566 INTEL_UEVENT_EXTRA_REG(c, \ 567 MSR_PEBS_LD_LAT_THRESHOLD, \ 568 0xffff, \ 569 LDLAT) 570 571 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 572 573 union perf_capabilities { 574 struct { 575 u64 lbr_format:6; 576 u64 pebs_trap:1; 577 u64 pebs_arch_reg:1; 578 u64 pebs_format:4; 579 u64 smm_freeze:1; 580 /* 581 * PMU supports separate counter range for writing 582 * values > 32bit. 583 */ 584 u64 full_width_write:1; 585 u64 pebs_baseline:1; 586 u64 perf_metrics:1; 587 u64 pebs_output_pt_available:1; 588 }; 589 u64 capabilities; 590 }; 591 592 struct x86_pmu_quirk { 593 struct x86_pmu_quirk *next; 594 void (*func)(void); 595 }; 596 597 union x86_pmu_config { 598 struct { 599 u64 event:8, 600 umask:8, 601 usr:1, 602 os:1, 603 edge:1, 604 pc:1, 605 interrupt:1, 606 __reserved1:1, 607 en:1, 608 inv:1, 609 cmask:8, 610 event2:4, 611 __reserved2:4, 612 go:1, 613 ho:1; 614 } bits; 615 u64 value; 616 }; 617 618 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 619 620 enum { 621 x86_lbr_exclusive_lbr, 622 x86_lbr_exclusive_bts, 623 x86_lbr_exclusive_pt, 624 x86_lbr_exclusive_max, 625 }; 626 627 /* 628 * struct x86_pmu - generic x86 pmu 629 */ 630 struct x86_pmu { 631 /* 632 * Generic x86 PMC bits 633 */ 634 const char *name; 635 int version; 636 int (*handle_irq)(struct pt_regs *); 637 void (*disable_all)(void); 638 void (*enable_all)(int added); 639 void (*enable)(struct perf_event *); 640 void (*disable)(struct perf_event *); 641 void (*add)(struct perf_event *); 642 void (*del)(struct perf_event *); 643 void (*read)(struct perf_event *event); 644 int (*hw_config)(struct perf_event *event); 645 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 646 unsigned eventsel; 647 unsigned perfctr; 648 int (*addr_offset)(int index, bool eventsel); 649 int (*rdpmc_index)(int index); 650 u64 (*event_map)(int); 651 int max_events; 652 int num_counters; 653 int num_counters_fixed; 654 int cntval_bits; 655 u64 cntval_mask; 656 union { 657 unsigned long events_maskl; 658 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 659 }; 660 int events_mask_len; 661 int apic; 662 u64 max_period; 663 struct event_constraint * 664 (*get_event_constraints)(struct cpu_hw_events *cpuc, 665 int idx, 666 struct perf_event *event); 667 668 void (*put_event_constraints)(struct cpu_hw_events *cpuc, 669 struct perf_event *event); 670 671 void (*start_scheduling)(struct cpu_hw_events *cpuc); 672 673 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 674 675 void (*stop_scheduling)(struct cpu_hw_events *cpuc); 676 677 struct event_constraint *event_constraints; 678 struct x86_pmu_quirk *quirks; 679 int perfctr_second_write; 680 u64 (*limit_period)(struct perf_event *event, u64 l); 681 682 /* PMI handler bits */ 683 unsigned int late_ack :1, 684 enabled_ack :1, 685 counter_freezing :1; 686 /* 687 * sysfs attrs 688 */ 689 int attr_rdpmc_broken; 690 int attr_rdpmc; 691 struct attribute **format_attrs; 692 693 ssize_t (*events_sysfs_show)(char *page, u64 config); 694 const struct attribute_group **attr_update; 695 696 unsigned long attr_freeze_on_smi; 697 698 /* 699 * CPU Hotplug hooks 700 */ 701 int (*cpu_prepare)(int cpu); 702 void (*cpu_starting)(int cpu); 703 void (*cpu_dying)(int cpu); 704 void (*cpu_dead)(int cpu); 705 706 void (*check_microcode)(void); 707 void (*sched_task)(struct perf_event_context *ctx, 708 bool sched_in); 709 710 /* 711 * Intel Arch Perfmon v2+ 712 */ 713 u64 intel_ctrl; 714 union perf_capabilities intel_cap; 715 716 /* 717 * Intel DebugStore bits 718 */ 719 unsigned int bts :1, 720 bts_active :1, 721 pebs :1, 722 pebs_active :1, 723 pebs_broken :1, 724 pebs_prec_dist :1, 725 pebs_no_tlb :1, 726 pebs_no_isolation :1; 727 int pebs_record_size; 728 int pebs_buffer_size; 729 int max_pebs_events; 730 void (*drain_pebs)(struct pt_regs *regs); 731 struct event_constraint *pebs_constraints; 732 void (*pebs_aliases)(struct perf_event *event); 733 unsigned long large_pebs_flags; 734 u64 rtm_abort_event; 735 736 /* 737 * Intel LBR 738 */ 739 unsigned int lbr_tos, lbr_from, lbr_to, 740 lbr_info, lbr_nr; /* LBR base regs and size */ 741 union { 742 u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 743 u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 744 }; 745 union { 746 const int *lbr_sel_map; /* lbr_select mappings */ 747 int *lbr_ctl_map; /* LBR_CTL mappings */ 748 }; 749 bool lbr_double_abort; /* duplicated lbr aborts */ 750 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 751 752 /* 753 * Intel Architectural LBR CPUID Enumeration 754 */ 755 unsigned int lbr_depth_mask:8; 756 unsigned int lbr_deep_c_reset:1; 757 unsigned int lbr_lip:1; 758 unsigned int lbr_cpl:1; 759 unsigned int lbr_filter:1; 760 unsigned int lbr_call_stack:1; 761 unsigned int lbr_mispred:1; 762 unsigned int lbr_timed_lbr:1; 763 unsigned int lbr_br_type:1; 764 765 void (*lbr_reset)(void); 766 void (*lbr_read)(struct cpu_hw_events *cpuc); 767 void (*lbr_save)(void *ctx); 768 void (*lbr_restore)(void *ctx); 769 770 /* 771 * Intel PT/LBR/BTS are exclusive 772 */ 773 atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 774 775 /* 776 * Intel perf metrics 777 */ 778 u64 (*update_topdown_event)(struct perf_event *event); 779 int (*set_topdown_event_period)(struct perf_event *event); 780 781 /* 782 * perf task context (i.e. struct perf_event_context::task_ctx_data) 783 * switch helper to bridge calls from perf/core to perf/x86. 784 * See struct pmu::swap_task_ctx() usage for examples; 785 */ 786 void (*swap_task_ctx)(struct perf_event_context *prev, 787 struct perf_event_context *next); 788 789 /* 790 * AMD bits 791 */ 792 unsigned int amd_nb_constraints : 1; 793 u64 perf_ctr_pair_en; 794 795 /* 796 * Extra registers for events 797 */ 798 struct extra_reg *extra_regs; 799 unsigned int flags; 800 801 /* 802 * Intel host/guest support (KVM) 803 */ 804 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); 805 806 /* 807 * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 808 */ 809 int (*check_period) (struct perf_event *event, u64 period); 810 811 int (*aux_output_match) (struct perf_event *event); 812 }; 813 814 struct x86_perf_task_context_opt { 815 int lbr_callstack_users; 816 int lbr_stack_state; 817 int log_id; 818 }; 819 820 struct x86_perf_task_context { 821 u64 lbr_sel; 822 int tos; 823 int valid_lbrs; 824 struct x86_perf_task_context_opt opt; 825 struct lbr_entry lbr[MAX_LBR_ENTRIES]; 826 }; 827 828 struct x86_perf_task_context_arch_lbr { 829 struct x86_perf_task_context_opt opt; 830 struct lbr_entry entries[]; 831 }; 832 833 /* 834 * Add padding to guarantee the 64-byte alignment of the state buffer. 835 * 836 * The structure is dynamically allocated. The size of the LBR state may vary 837 * based on the number of LBR registers. 838 * 839 * Do not put anything after the LBR state. 840 */ 841 struct x86_perf_task_context_arch_lbr_xsave { 842 struct x86_perf_task_context_opt opt; 843 844 union { 845 struct xregs_state xsave; 846 struct { 847 struct fxregs_state i387; 848 struct xstate_header header; 849 struct arch_lbr_state lbr; 850 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 851 }; 852 }; 853 854 #define x86_add_quirk(func_) \ 855 do { \ 856 static struct x86_pmu_quirk __quirk __initdata = { \ 857 .func = func_, \ 858 }; \ 859 __quirk.next = x86_pmu.quirks; \ 860 x86_pmu.quirks = &__quirk; \ 861 } while (0) 862 863 /* 864 * x86_pmu flags 865 */ 866 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 867 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 868 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 869 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 870 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 871 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 872 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 873 874 #define EVENT_VAR(_id) event_attr_##_id 875 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 876 877 #define EVENT_ATTR(_name, _id) \ 878 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 879 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 880 .id = PERF_COUNT_HW_##_id, \ 881 .event_str = NULL, \ 882 }; 883 884 #define EVENT_ATTR_STR(_name, v, str) \ 885 static struct perf_pmu_events_attr event_attr_##v = { \ 886 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 887 .id = 0, \ 888 .event_str = str, \ 889 }; 890 891 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 892 static struct perf_pmu_events_ht_attr event_attr_##v = { \ 893 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 894 .id = 0, \ 895 .event_str_noht = noht, \ 896 .event_str_ht = ht, \ 897 } 898 899 struct pmu *x86_get_pmu(void); 900 extern struct x86_pmu x86_pmu __read_mostly; 901 902 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 903 { 904 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 905 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 906 907 return &((struct x86_perf_task_context *)ctx)->opt; 908 } 909 910 static inline bool x86_pmu_has_lbr_callstack(void) 911 { 912 return x86_pmu.lbr_sel_map && 913 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 914 } 915 916 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 917 918 int x86_perf_event_set_period(struct perf_event *event); 919 920 /* 921 * Generalized hw caching related hw_event table, filled 922 * in on a per model basis. A value of 0 means 923 * 'not supported', -1 means 'hw_event makes no sense on 924 * this CPU', any other value means the raw hw_event 925 * ID. 926 */ 927 928 #define C(x) PERF_COUNT_HW_CACHE_##x 929 930 extern u64 __read_mostly hw_cache_event_ids 931 [PERF_COUNT_HW_CACHE_MAX] 932 [PERF_COUNT_HW_CACHE_OP_MAX] 933 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 934 extern u64 __read_mostly hw_cache_extra_regs 935 [PERF_COUNT_HW_CACHE_MAX] 936 [PERF_COUNT_HW_CACHE_OP_MAX] 937 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 938 939 u64 x86_perf_event_update(struct perf_event *event); 940 941 static inline unsigned int x86_pmu_config_addr(int index) 942 { 943 return x86_pmu.eventsel + (x86_pmu.addr_offset ? 944 x86_pmu.addr_offset(index, true) : index); 945 } 946 947 static inline unsigned int x86_pmu_event_addr(int index) 948 { 949 return x86_pmu.perfctr + (x86_pmu.addr_offset ? 950 x86_pmu.addr_offset(index, false) : index); 951 } 952 953 static inline int x86_pmu_rdpmc_index(int index) 954 { 955 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 956 } 957 958 int x86_add_exclusive(unsigned int what); 959 960 void x86_del_exclusive(unsigned int what); 961 962 int x86_reserve_hardware(void); 963 964 void x86_release_hardware(void); 965 966 int x86_pmu_max_precise(void); 967 968 void hw_perf_lbr_event_destroy(struct perf_event *event); 969 970 int x86_setup_perfctr(struct perf_event *event); 971 972 int x86_pmu_hw_config(struct perf_event *event); 973 974 void x86_pmu_disable_all(void); 975 976 static inline bool is_counter_pair(struct hw_perf_event *hwc) 977 { 978 return hwc->flags & PERF_X86_EVENT_PAIR; 979 } 980 981 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 982 u64 enable_mask) 983 { 984 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 985 986 if (hwc->extra_reg.reg) 987 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 988 989 /* 990 * Add enabled Merge event on next counter 991 * if large increment event being enabled on this counter 992 */ 993 if (is_counter_pair(hwc)) 994 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 995 996 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 997 } 998 999 void x86_pmu_enable_all(int added); 1000 1001 int perf_assign_events(struct event_constraint **constraints, int n, 1002 int wmin, int wmax, int gpmax, int *assign); 1003 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 1004 1005 void x86_pmu_stop(struct perf_event *event, int flags); 1006 1007 static inline void x86_pmu_disable_event(struct perf_event *event) 1008 { 1009 struct hw_perf_event *hwc = &event->hw; 1010 1011 wrmsrl(hwc->config_base, hwc->config); 1012 1013 if (is_counter_pair(hwc)) 1014 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 1015 } 1016 1017 void x86_pmu_enable_event(struct perf_event *event); 1018 1019 int x86_pmu_handle_irq(struct pt_regs *regs); 1020 1021 extern struct event_constraint emptyconstraint; 1022 1023 extern struct event_constraint unconstrained; 1024 1025 static inline bool kernel_ip(unsigned long ip) 1026 { 1027 #ifdef CONFIG_X86_32 1028 return ip > PAGE_OFFSET; 1029 #else 1030 return (long)ip < 0; 1031 #endif 1032 } 1033 1034 /* 1035 * Not all PMUs provide the right context information to place the reported IP 1036 * into full context. Specifically segment registers are typically not 1037 * supplied. 1038 * 1039 * Assuming the address is a linear address (it is for IBS), we fake the CS and 1040 * vm86 mode using the known zero-based code segment and 'fix up' the registers 1041 * to reflect this. 1042 * 1043 * Intel PEBS/LBR appear to typically provide the effective address, nothing 1044 * much we can do about that but pray and treat it like a linear address. 1045 */ 1046 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 1047 { 1048 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 1049 if (regs->flags & X86_VM_MASK) 1050 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 1051 regs->ip = ip; 1052 } 1053 1054 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 1055 ssize_t intel_event_sysfs_show(char *page, u64 config); 1056 1057 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1058 char *page); 1059 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1060 char *page); 1061 1062 #ifdef CONFIG_CPU_SUP_AMD 1063 1064 int amd_pmu_init(void); 1065 1066 #else /* CONFIG_CPU_SUP_AMD */ 1067 1068 static inline int amd_pmu_init(void) 1069 { 1070 return 0; 1071 } 1072 1073 #endif /* CONFIG_CPU_SUP_AMD */ 1074 1075 static inline int is_pebs_pt(struct perf_event *event) 1076 { 1077 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 1078 } 1079 1080 #ifdef CONFIG_CPU_SUP_INTEL 1081 1082 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 1083 { 1084 struct hw_perf_event *hwc = &event->hw; 1085 unsigned int hw_event, bts_event; 1086 1087 if (event->attr.freq) 1088 return false; 1089 1090 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 1091 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 1092 1093 return hw_event == bts_event && period == 1; 1094 } 1095 1096 static inline bool intel_pmu_has_bts(struct perf_event *event) 1097 { 1098 struct hw_perf_event *hwc = &event->hw; 1099 1100 return intel_pmu_has_bts_period(event, hwc->sample_period); 1101 } 1102 1103 int intel_pmu_save_and_restart(struct perf_event *event); 1104 1105 struct event_constraint * 1106 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 1107 struct perf_event *event); 1108 1109 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1110 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 1111 1112 int intel_pmu_init(void); 1113 1114 void init_debug_store_on_cpu(int cpu); 1115 1116 void fini_debug_store_on_cpu(int cpu); 1117 1118 void release_ds_buffers(void); 1119 1120 void reserve_ds_buffers(void); 1121 1122 void release_lbr_buffers(void); 1123 1124 extern struct event_constraint bts_constraint; 1125 extern struct event_constraint vlbr_constraint; 1126 1127 void intel_pmu_enable_bts(u64 config); 1128 1129 void intel_pmu_disable_bts(void); 1130 1131 int intel_pmu_drain_bts_buffer(void); 1132 1133 extern struct event_constraint intel_core2_pebs_event_constraints[]; 1134 1135 extern struct event_constraint intel_atom_pebs_event_constraints[]; 1136 1137 extern struct event_constraint intel_slm_pebs_event_constraints[]; 1138 1139 extern struct event_constraint intel_glm_pebs_event_constraints[]; 1140 1141 extern struct event_constraint intel_glp_pebs_event_constraints[]; 1142 1143 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1144 1145 extern struct event_constraint intel_westmere_pebs_event_constraints[]; 1146 1147 extern struct event_constraint intel_snb_pebs_event_constraints[]; 1148 1149 extern struct event_constraint intel_ivb_pebs_event_constraints[]; 1150 1151 extern struct event_constraint intel_hsw_pebs_event_constraints[]; 1152 1153 extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1154 1155 extern struct event_constraint intel_skl_pebs_event_constraints[]; 1156 1157 extern struct event_constraint intel_icl_pebs_event_constraints[]; 1158 1159 struct event_constraint *intel_pebs_constraints(struct perf_event *event); 1160 1161 void intel_pmu_pebs_add(struct perf_event *event); 1162 1163 void intel_pmu_pebs_del(struct perf_event *event); 1164 1165 void intel_pmu_pebs_enable(struct perf_event *event); 1166 1167 void intel_pmu_pebs_disable(struct perf_event *event); 1168 1169 void intel_pmu_pebs_enable_all(void); 1170 1171 void intel_pmu_pebs_disable_all(void); 1172 1173 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); 1174 1175 void intel_pmu_auto_reload_read(struct perf_event *event); 1176 1177 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1178 1179 void intel_ds_init(void); 1180 1181 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 1182 struct perf_event_context *next); 1183 1184 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); 1185 1186 u64 lbr_from_signext_quirk_wr(u64 val); 1187 1188 void intel_pmu_lbr_reset(void); 1189 1190 void intel_pmu_lbr_reset_32(void); 1191 1192 void intel_pmu_lbr_reset_64(void); 1193 1194 void intel_pmu_lbr_add(struct perf_event *event); 1195 1196 void intel_pmu_lbr_del(struct perf_event *event); 1197 1198 void intel_pmu_lbr_enable_all(bool pmi); 1199 1200 void intel_pmu_lbr_disable_all(void); 1201 1202 void intel_pmu_lbr_read(void); 1203 1204 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1205 1206 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1207 1208 void intel_pmu_lbr_save(void *ctx); 1209 1210 void intel_pmu_lbr_restore(void *ctx); 1211 1212 void intel_pmu_lbr_init_core(void); 1213 1214 void intel_pmu_lbr_init_nhm(void); 1215 1216 void intel_pmu_lbr_init_atom(void); 1217 1218 void intel_pmu_lbr_init_slm(void); 1219 1220 void intel_pmu_lbr_init_snb(void); 1221 1222 void intel_pmu_lbr_init_hsw(void); 1223 1224 void intel_pmu_lbr_init_skl(void); 1225 1226 void intel_pmu_lbr_init_knl(void); 1227 1228 void intel_pmu_arch_lbr_init(void); 1229 1230 void intel_pmu_pebs_data_source_nhm(void); 1231 1232 void intel_pmu_pebs_data_source_skl(bool pmem); 1233 1234 int intel_pmu_setup_lbr_filter(struct perf_event *event); 1235 1236 void intel_pt_interrupt(void); 1237 1238 int intel_bts_interrupt(void); 1239 1240 void intel_bts_enable_local(void); 1241 1242 void intel_bts_disable_local(void); 1243 1244 int p4_pmu_init(void); 1245 1246 int p6_pmu_init(void); 1247 1248 int knc_pmu_init(void); 1249 1250 static inline int is_ht_workaround_enabled(void) 1251 { 1252 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 1253 } 1254 1255 #else /* CONFIG_CPU_SUP_INTEL */ 1256 1257 static inline void reserve_ds_buffers(void) 1258 { 1259 } 1260 1261 static inline void release_ds_buffers(void) 1262 { 1263 } 1264 1265 static inline void release_lbr_buffers(void) 1266 { 1267 } 1268 1269 static inline int intel_pmu_init(void) 1270 { 1271 return 0; 1272 } 1273 1274 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 1275 { 1276 return 0; 1277 } 1278 1279 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1280 { 1281 } 1282 1283 static inline int is_ht_workaround_enabled(void) 1284 { 1285 return 0; 1286 } 1287 #endif /* CONFIG_CPU_SUP_INTEL */ 1288 1289 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 1290 int zhaoxin_pmu_init(void); 1291 #else 1292 static inline int zhaoxin_pmu_init(void) 1293 { 1294 return 0; 1295 } 1296 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1297