1 /* 2 * Performance events x86 architecture header 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 17 #include <asm/fpu/xstate.h> 18 #include <asm/intel_ds.h> 19 #include <asm/cpu.h> 20 21 /* To enable MSR tracing please use the generic trace points. */ 22 23 /* 24 * | NHM/WSM | SNB | 25 * register ------------------------------- 26 * | HT | no HT | HT | no HT | 27 *----------------------------------------- 28 * offcore | core | core | cpu | core | 29 * lbr_sel | core | core | cpu | core | 30 * ld_lat | cpu | core | cpu | core | 31 *----------------------------------------- 32 * 33 * Given that there is a small number of shared regs, 34 * we can pre-allocate their slot in the per-cpu 35 * per-core reg tables. 36 */ 37 enum extra_reg_type { 38 EXTRA_REG_NONE = -1, /* not used */ 39 40 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 41 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 42 EXTRA_REG_LBR = 2, /* lbr_select */ 43 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 44 EXTRA_REG_FE = 4, /* fe_* */ 45 46 EXTRA_REG_MAX /* number of entries needed */ 47 }; 48 49 struct event_constraint { 50 union { 51 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 52 u64 idxmsk64; 53 }; 54 u64 code; 55 u64 cmask; 56 int weight; 57 int overlap; 58 int flags; 59 unsigned int size; 60 }; 61 62 static inline bool constraint_match(struct event_constraint *c, u64 ecode) 63 { 64 return ((ecode & c->cmask) - c->code) <= (u64)c->size; 65 } 66 67 /* 68 * struct hw_perf_event.flags flags 69 */ 70 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ 71 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ 72 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ 73 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */ 74 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */ 75 #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */ 76 #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */ 77 78 #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */ 79 #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */ 80 #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */ 81 #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */ 82 #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */ 83 #define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */ 84 #define PERF_X86_EVENT_TOPDOWN 0x4000 /* Count Topdown slots/metrics events */ 85 #define PERF_X86_EVENT_PEBS_STLAT 0x8000 /* st+stlat data address sampling */ 86 87 static inline bool is_topdown_count(struct perf_event *event) 88 { 89 return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 90 } 91 92 static inline bool is_metric_event(struct perf_event *event) 93 { 94 u64 config = event->attr.config; 95 96 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 97 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 98 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 99 } 100 101 static inline bool is_slots_event(struct perf_event *event) 102 { 103 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 104 } 105 106 static inline bool is_topdown_event(struct perf_event *event) 107 { 108 return is_metric_event(event) || is_slots_event(event); 109 } 110 111 struct amd_nb { 112 int nb_id; /* NorthBridge id */ 113 int refcnt; /* reference count */ 114 struct perf_event *owners[X86_PMC_IDX_MAX]; 115 struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 116 }; 117 118 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 119 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 120 #define PEBS_OUTPUT_OFFSET 61 121 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 122 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 123 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 124 125 /* 126 * Flags PEBS can handle without an PMI. 127 * 128 * TID can only be handled by flushing at context switch. 129 * REGS_USER can be handled for events limited to ring 3. 130 * 131 */ 132 #define LARGE_PEBS_FLAGS \ 133 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 134 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 135 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 136 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 137 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 138 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE) 139 140 #define PEBS_GP_REGS \ 141 ((1ULL << PERF_REG_X86_AX) | \ 142 (1ULL << PERF_REG_X86_BX) | \ 143 (1ULL << PERF_REG_X86_CX) | \ 144 (1ULL << PERF_REG_X86_DX) | \ 145 (1ULL << PERF_REG_X86_DI) | \ 146 (1ULL << PERF_REG_X86_SI) | \ 147 (1ULL << PERF_REG_X86_SP) | \ 148 (1ULL << PERF_REG_X86_BP) | \ 149 (1ULL << PERF_REG_X86_IP) | \ 150 (1ULL << PERF_REG_X86_FLAGS) | \ 151 (1ULL << PERF_REG_X86_R8) | \ 152 (1ULL << PERF_REG_X86_R9) | \ 153 (1ULL << PERF_REG_X86_R10) | \ 154 (1ULL << PERF_REG_X86_R11) | \ 155 (1ULL << PERF_REG_X86_R12) | \ 156 (1ULL << PERF_REG_X86_R13) | \ 157 (1ULL << PERF_REG_X86_R14) | \ 158 (1ULL << PERF_REG_X86_R15)) 159 160 /* 161 * Per register state. 162 */ 163 struct er_account { 164 raw_spinlock_t lock; /* per-core: protect structure */ 165 u64 config; /* extra MSR config */ 166 u64 reg; /* extra MSR number */ 167 atomic_t ref; /* reference count */ 168 }; 169 170 /* 171 * Per core/cpu state 172 * 173 * Used to coordinate shared registers between HT threads or 174 * among events on a single PMU. 175 */ 176 struct intel_shared_regs { 177 struct er_account regs[EXTRA_REG_MAX]; 178 int refcnt; /* per-core: #HT threads */ 179 unsigned core_id; /* per-core: core id */ 180 }; 181 182 enum intel_excl_state_type { 183 INTEL_EXCL_UNUSED = 0, /* counter is unused */ 184 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 185 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 186 }; 187 188 struct intel_excl_states { 189 enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 190 bool sched_started; /* true if scheduling has started */ 191 }; 192 193 struct intel_excl_cntrs { 194 raw_spinlock_t lock; 195 196 struct intel_excl_states states[2]; 197 198 union { 199 u16 has_exclusive[2]; 200 u32 exclusive_present; 201 }; 202 203 int refcnt; /* per-core: #HT threads */ 204 unsigned core_id; /* per-core: core id */ 205 }; 206 207 struct x86_perf_task_context; 208 #define MAX_LBR_ENTRIES 32 209 210 enum { 211 LBR_FORMAT_32 = 0x00, 212 LBR_FORMAT_LIP = 0x01, 213 LBR_FORMAT_EIP = 0x02, 214 LBR_FORMAT_EIP_FLAGS = 0x03, 215 LBR_FORMAT_EIP_FLAGS2 = 0x04, 216 LBR_FORMAT_INFO = 0x05, 217 LBR_FORMAT_TIME = 0x06, 218 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME, 219 }; 220 221 enum { 222 X86_PERF_KFREE_SHARED = 0, 223 X86_PERF_KFREE_EXCL = 1, 224 X86_PERF_KFREE_MAX 225 }; 226 227 struct cpu_hw_events { 228 /* 229 * Generic x86 PMC bits 230 */ 231 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 232 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 233 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 234 int enabled; 235 236 int n_events; /* the # of events in the below arrays */ 237 int n_added; /* the # last events in the below arrays; 238 they've never been enabled yet */ 239 int n_txn; /* the # last events in the below arrays; 240 added in the current transaction */ 241 int n_txn_pair; 242 int n_txn_metric; 243 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 244 u64 tags[X86_PMC_IDX_MAX]; 245 246 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 247 struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 248 249 int n_excl; /* the number of exclusive events */ 250 251 unsigned int txn_flags; 252 int is_fake; 253 254 /* 255 * Intel DebugStore bits 256 */ 257 struct debug_store *ds; 258 void *ds_pebs_vaddr; 259 void *ds_bts_vaddr; 260 u64 pebs_enabled; 261 int n_pebs; 262 int n_large_pebs; 263 int n_pebs_via_pt; 264 int pebs_output; 265 266 /* Current super set of events hardware configuration */ 267 u64 pebs_data_cfg; 268 u64 active_pebs_data_cfg; 269 int pebs_record_size; 270 271 /* 272 * Intel LBR bits 273 */ 274 int lbr_users; 275 int lbr_pebs_users; 276 struct perf_branch_stack lbr_stack; 277 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 278 union { 279 struct er_account *lbr_sel; 280 struct er_account *lbr_ctl; 281 }; 282 u64 br_sel; 283 void *last_task_ctx; 284 int last_log_id; 285 int lbr_select; 286 void *lbr_xsave; 287 288 /* 289 * Intel host/guest exclude bits 290 */ 291 u64 intel_ctrl_guest_mask; 292 u64 intel_ctrl_host_mask; 293 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 294 295 /* 296 * Intel checkpoint mask 297 */ 298 u64 intel_cp_status; 299 300 /* 301 * manage shared (per-core, per-cpu) registers 302 * used on Intel NHM/WSM/SNB 303 */ 304 struct intel_shared_regs *shared_regs; 305 /* 306 * manage exclusive counter access between hyperthread 307 */ 308 struct event_constraint *constraint_list; /* in enable order */ 309 struct intel_excl_cntrs *excl_cntrs; 310 int excl_thread_id; /* 0 or 1 */ 311 312 /* 313 * SKL TSX_FORCE_ABORT shadow 314 */ 315 u64 tfa_shadow; 316 317 /* 318 * Perf Metrics 319 */ 320 /* number of accepted metrics events */ 321 int n_metric; 322 323 /* 324 * AMD specific bits 325 */ 326 struct amd_nb *amd_nb; 327 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 328 u64 perf_ctr_virt_mask; 329 int n_pair; /* Large increment events */ 330 331 void *kfree_on_online[X86_PERF_KFREE_MAX]; 332 333 struct pmu *pmu; 334 }; 335 336 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 337 { .idxmsk64 = (n) }, \ 338 .code = (c), \ 339 .size = (e) - (c), \ 340 .cmask = (m), \ 341 .weight = (w), \ 342 .overlap = (o), \ 343 .flags = f, \ 344 } 345 346 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 347 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 348 349 #define EVENT_CONSTRAINT(c, n, m) \ 350 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 351 352 /* 353 * The constraint_match() function only works for 'simple' event codes 354 * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 355 */ 356 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 357 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 358 359 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 360 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 361 0, PERF_X86_EVENT_EXCL) 362 363 /* 364 * The overlap flag marks event constraints with overlapping counter 365 * masks. This is the case if the counter mask of such an event is not 366 * a subset of any other counter mask of a constraint with an equal or 367 * higher weight, e.g.: 368 * 369 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 370 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 371 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 372 * 373 * The event scheduler may not select the correct counter in the first 374 * cycle because it needs to know which subsequent events will be 375 * scheduled. It may fail to schedule the events then. So we set the 376 * overlap flag for such constraints to give the scheduler a hint which 377 * events to select for counter rescheduling. 378 * 379 * Care must be taken as the rescheduling algorithm is O(n!) which 380 * will increase scheduling cycles for an over-committed system 381 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 382 * and its counter masks must be kept at a minimum. 383 */ 384 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 385 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 386 387 /* 388 * Constraint on the Event code. 389 */ 390 #define INTEL_EVENT_CONSTRAINT(c, n) \ 391 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 392 393 /* 394 * Constraint on a range of Event codes 395 */ 396 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 397 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 398 399 /* 400 * Constraint on the Event code + UMask + fixed-mask 401 * 402 * filter mask to validate fixed counter events. 403 * the following filters disqualify for fixed counters: 404 * - inv 405 * - edge 406 * - cnt-mask 407 * - in_tx 408 * - in_tx_checkpointed 409 * The other filters are supported by fixed counters. 410 * The any-thread option is supported starting with v3. 411 */ 412 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 413 #define FIXED_EVENT_CONSTRAINT(c, n) \ 414 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 415 416 /* 417 * The special metric counters do not actually exist. They are calculated from 418 * the combination of the FxCtr3 + MSR_PERF_METRICS. 419 * 420 * The special metric counters are mapped to a dummy offset for the scheduler. 421 * The sharing between multiple users of the same metric without multiplexing 422 * is not allowed, even though the hardware supports that in principle. 423 */ 424 425 #define METRIC_EVENT_CONSTRAINT(c, n) \ 426 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 427 INTEL_ARCH_EVENT_MASK) 428 429 /* 430 * Constraint on the Event code + UMask 431 */ 432 #define INTEL_UEVENT_CONSTRAINT(c, n) \ 433 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 434 435 /* Constraint on specific umask bit only + event */ 436 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 437 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 438 439 /* Like UEVENT_CONSTRAINT, but match flags too */ 440 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 441 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 442 443 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 444 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 445 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 446 447 #define INTEL_PLD_CONSTRAINT(c, n) \ 448 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 449 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 450 451 #define INTEL_PSD_CONSTRAINT(c, n) \ 452 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 453 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT) 454 455 #define INTEL_PST_CONSTRAINT(c, n) \ 456 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 457 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 458 459 /* Event constraint, but match on all event flags too. */ 460 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 461 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 462 463 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 464 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 465 466 /* Check only flags, but allow all event/umask */ 467 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 468 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 469 470 /* Check flags and event code, and set the HSW store flag */ 471 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 472 __EVENT_CONSTRAINT(code, n, \ 473 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 474 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 475 476 /* Check flags and event code, and set the HSW load flag */ 477 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 478 __EVENT_CONSTRAINT(code, n, \ 479 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 480 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 481 482 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 483 __EVENT_CONSTRAINT_RANGE(code, end, n, \ 484 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 485 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 486 487 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 488 __EVENT_CONSTRAINT(code, n, \ 489 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 490 HWEIGHT(n), 0, \ 491 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 492 493 /* Check flags and event code/umask, and set the HSW store flag */ 494 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 495 __EVENT_CONSTRAINT(code, n, \ 496 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 497 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 498 499 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 500 __EVENT_CONSTRAINT(code, n, \ 501 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 502 HWEIGHT(n), 0, \ 503 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 504 505 /* Check flags and event code/umask, and set the HSW load flag */ 506 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 507 __EVENT_CONSTRAINT(code, n, \ 508 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 509 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 510 511 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 512 __EVENT_CONSTRAINT(code, n, \ 513 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 514 HWEIGHT(n), 0, \ 515 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 516 517 /* Check flags and event code/umask, and set the HSW N/A flag */ 518 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 519 __EVENT_CONSTRAINT(code, n, \ 520 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 521 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 522 523 524 /* 525 * We define the end marker as having a weight of -1 526 * to enable blacklisting of events using a counter bitmask 527 * of zero and thus a weight of zero. 528 * The end marker has a weight that cannot possibly be 529 * obtained from counting the bits in the bitmask. 530 */ 531 #define EVENT_CONSTRAINT_END { .weight = -1 } 532 533 /* 534 * Check for end marker with weight == -1 535 */ 536 #define for_each_event_constraint(e, c) \ 537 for ((e) = (c); (e)->weight != -1; (e)++) 538 539 /* 540 * Extra registers for specific events. 541 * 542 * Some events need large masks and require external MSRs. 543 * Those extra MSRs end up being shared for all events on 544 * a PMU and sometimes between PMU of sibling HT threads. 545 * In either case, the kernel needs to handle conflicting 546 * accesses to those extra, shared, regs. The data structure 547 * to manage those registers is stored in cpu_hw_event. 548 */ 549 struct extra_reg { 550 unsigned int event; 551 unsigned int msr; 552 u64 config_mask; 553 u64 valid_mask; 554 int idx; /* per_xxx->regs[] reg index */ 555 bool extra_msr_access; 556 }; 557 558 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 559 .event = (e), \ 560 .msr = (ms), \ 561 .config_mask = (m), \ 562 .valid_mask = (vm), \ 563 .idx = EXTRA_REG_##i, \ 564 .extra_msr_access = true, \ 565 } 566 567 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 568 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 569 570 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 571 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 572 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 573 574 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 575 INTEL_UEVENT_EXTRA_REG(c, \ 576 MSR_PEBS_LD_LAT_THRESHOLD, \ 577 0xffff, \ 578 LDLAT) 579 580 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 581 582 union perf_capabilities { 583 struct { 584 u64 lbr_format:6; 585 u64 pebs_trap:1; 586 u64 pebs_arch_reg:1; 587 u64 pebs_format:4; 588 u64 smm_freeze:1; 589 /* 590 * PMU supports separate counter range for writing 591 * values > 32bit. 592 */ 593 u64 full_width_write:1; 594 u64 pebs_baseline:1; 595 u64 perf_metrics:1; 596 u64 pebs_output_pt_available:1; 597 u64 anythread_deprecated:1; 598 }; 599 u64 capabilities; 600 }; 601 602 struct x86_pmu_quirk { 603 struct x86_pmu_quirk *next; 604 void (*func)(void); 605 }; 606 607 union x86_pmu_config { 608 struct { 609 u64 event:8, 610 umask:8, 611 usr:1, 612 os:1, 613 edge:1, 614 pc:1, 615 interrupt:1, 616 __reserved1:1, 617 en:1, 618 inv:1, 619 cmask:8, 620 event2:4, 621 __reserved2:4, 622 go:1, 623 ho:1; 624 } bits; 625 u64 value; 626 }; 627 628 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 629 630 enum { 631 x86_lbr_exclusive_lbr, 632 x86_lbr_exclusive_bts, 633 x86_lbr_exclusive_pt, 634 x86_lbr_exclusive_max, 635 }; 636 637 struct x86_hybrid_pmu { 638 struct pmu pmu; 639 const char *name; 640 u8 cpu_type; 641 cpumask_t supported_cpus; 642 union perf_capabilities intel_cap; 643 u64 intel_ctrl; 644 int max_pebs_events; 645 int num_counters; 646 int num_counters_fixed; 647 struct event_constraint unconstrained; 648 649 u64 hw_cache_event_ids 650 [PERF_COUNT_HW_CACHE_MAX] 651 [PERF_COUNT_HW_CACHE_OP_MAX] 652 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 653 u64 hw_cache_extra_regs 654 [PERF_COUNT_HW_CACHE_MAX] 655 [PERF_COUNT_HW_CACHE_OP_MAX] 656 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 657 struct event_constraint *event_constraints; 658 struct event_constraint *pebs_constraints; 659 struct extra_reg *extra_regs; 660 661 unsigned int late_ack :1, 662 mid_ack :1, 663 enabled_ack :1; 664 }; 665 666 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) 667 { 668 return container_of(pmu, struct x86_hybrid_pmu, pmu); 669 } 670 671 extern struct static_key_false perf_is_hybrid; 672 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid) 673 674 #define hybrid(_pmu, _field) \ 675 (*({ \ 676 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \ 677 \ 678 if (is_hybrid() && (_pmu)) \ 679 __Fp = &hybrid_pmu(_pmu)->_field; \ 680 \ 681 __Fp; \ 682 })) 683 684 #define hybrid_var(_pmu, _var) \ 685 (*({ \ 686 typeof(&_var) __Fp = &_var; \ 687 \ 688 if (is_hybrid() && (_pmu)) \ 689 __Fp = &hybrid_pmu(_pmu)->_var; \ 690 \ 691 __Fp; \ 692 })) 693 694 #define hybrid_bit(_pmu, _field) \ 695 ({ \ 696 bool __Fp = x86_pmu._field; \ 697 \ 698 if (is_hybrid() && (_pmu)) \ 699 __Fp = hybrid_pmu(_pmu)->_field; \ 700 \ 701 __Fp; \ 702 }) 703 704 enum hybrid_pmu_type { 705 hybrid_big = 0x40, 706 hybrid_small = 0x20, 707 708 hybrid_big_small = hybrid_big | hybrid_small, 709 }; 710 711 #define X86_HYBRID_PMU_ATOM_IDX 0 712 #define X86_HYBRID_PMU_CORE_IDX 1 713 714 #define X86_HYBRID_NUM_PMUS 2 715 716 /* 717 * struct x86_pmu - generic x86 pmu 718 */ 719 struct x86_pmu { 720 /* 721 * Generic x86 PMC bits 722 */ 723 const char *name; 724 int version; 725 int (*handle_irq)(struct pt_regs *); 726 void (*disable_all)(void); 727 void (*enable_all)(int added); 728 void (*enable)(struct perf_event *); 729 void (*disable)(struct perf_event *); 730 void (*assign)(struct perf_event *event, int idx); 731 void (*add)(struct perf_event *); 732 void (*del)(struct perf_event *); 733 void (*read)(struct perf_event *event); 734 int (*hw_config)(struct perf_event *event); 735 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 736 unsigned eventsel; 737 unsigned perfctr; 738 int (*addr_offset)(int index, bool eventsel); 739 int (*rdpmc_index)(int index); 740 u64 (*event_map)(int); 741 int max_events; 742 int num_counters; 743 int num_counters_fixed; 744 int cntval_bits; 745 u64 cntval_mask; 746 union { 747 unsigned long events_maskl; 748 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 749 }; 750 int events_mask_len; 751 int apic; 752 u64 max_period; 753 struct event_constraint * 754 (*get_event_constraints)(struct cpu_hw_events *cpuc, 755 int idx, 756 struct perf_event *event); 757 758 void (*put_event_constraints)(struct cpu_hw_events *cpuc, 759 struct perf_event *event); 760 761 void (*start_scheduling)(struct cpu_hw_events *cpuc); 762 763 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 764 765 void (*stop_scheduling)(struct cpu_hw_events *cpuc); 766 767 struct event_constraint *event_constraints; 768 struct x86_pmu_quirk *quirks; 769 int perfctr_second_write; 770 u64 (*limit_period)(struct perf_event *event, u64 l); 771 772 /* PMI handler bits */ 773 unsigned int late_ack :1, 774 mid_ack :1, 775 enabled_ack :1; 776 /* 777 * sysfs attrs 778 */ 779 int attr_rdpmc_broken; 780 int attr_rdpmc; 781 struct attribute **format_attrs; 782 783 ssize_t (*events_sysfs_show)(char *page, u64 config); 784 const struct attribute_group **attr_update; 785 786 unsigned long attr_freeze_on_smi; 787 788 /* 789 * CPU Hotplug hooks 790 */ 791 int (*cpu_prepare)(int cpu); 792 void (*cpu_starting)(int cpu); 793 void (*cpu_dying)(int cpu); 794 void (*cpu_dead)(int cpu); 795 796 void (*check_microcode)(void); 797 void (*sched_task)(struct perf_event_context *ctx, 798 bool sched_in); 799 800 /* 801 * Intel Arch Perfmon v2+ 802 */ 803 u64 intel_ctrl; 804 union perf_capabilities intel_cap; 805 806 /* 807 * Intel DebugStore bits 808 */ 809 unsigned int bts :1, 810 bts_active :1, 811 pebs :1, 812 pebs_active :1, 813 pebs_broken :1, 814 pebs_prec_dist :1, 815 pebs_no_tlb :1, 816 pebs_no_isolation :1, 817 pebs_block :1; 818 int pebs_record_size; 819 int pebs_buffer_size; 820 int max_pebs_events; 821 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 822 struct event_constraint *pebs_constraints; 823 void (*pebs_aliases)(struct perf_event *event); 824 unsigned long large_pebs_flags; 825 u64 rtm_abort_event; 826 827 /* 828 * Intel LBR 829 */ 830 unsigned int lbr_tos, lbr_from, lbr_to, 831 lbr_info, lbr_nr; /* LBR base regs and size */ 832 union { 833 u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 834 u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 835 }; 836 union { 837 const int *lbr_sel_map; /* lbr_select mappings */ 838 int *lbr_ctl_map; /* LBR_CTL mappings */ 839 }; 840 bool lbr_double_abort; /* duplicated lbr aborts */ 841 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 842 843 /* 844 * Intel Architectural LBR CPUID Enumeration 845 */ 846 unsigned int lbr_depth_mask:8; 847 unsigned int lbr_deep_c_reset:1; 848 unsigned int lbr_lip:1; 849 unsigned int lbr_cpl:1; 850 unsigned int lbr_filter:1; 851 unsigned int lbr_call_stack:1; 852 unsigned int lbr_mispred:1; 853 unsigned int lbr_timed_lbr:1; 854 unsigned int lbr_br_type:1; 855 856 void (*lbr_reset)(void); 857 void (*lbr_read)(struct cpu_hw_events *cpuc); 858 void (*lbr_save)(void *ctx); 859 void (*lbr_restore)(void *ctx); 860 861 /* 862 * Intel PT/LBR/BTS are exclusive 863 */ 864 atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 865 866 /* 867 * Intel perf metrics 868 */ 869 int num_topdown_events; 870 u64 (*update_topdown_event)(struct perf_event *event); 871 int (*set_topdown_event_period)(struct perf_event *event); 872 873 /* 874 * perf task context (i.e. struct perf_event_context::task_ctx_data) 875 * switch helper to bridge calls from perf/core to perf/x86. 876 * See struct pmu::swap_task_ctx() usage for examples; 877 */ 878 void (*swap_task_ctx)(struct perf_event_context *prev, 879 struct perf_event_context *next); 880 881 /* 882 * AMD bits 883 */ 884 unsigned int amd_nb_constraints : 1; 885 u64 perf_ctr_pair_en; 886 887 /* 888 * Extra registers for events 889 */ 890 struct extra_reg *extra_regs; 891 unsigned int flags; 892 893 /* 894 * Intel host/guest support (KVM) 895 */ 896 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); 897 898 /* 899 * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 900 */ 901 int (*check_period) (struct perf_event *event, u64 period); 902 903 int (*aux_output_match) (struct perf_event *event); 904 905 int (*filter_match)(struct perf_event *event); 906 /* 907 * Hybrid support 908 * 909 * Most PMU capabilities are the same among different hybrid PMUs. 910 * The global x86_pmu saves the architecture capabilities, which 911 * are available for all PMUs. The hybrid_pmu only includes the 912 * unique capabilities. 913 */ 914 int num_hybrid_pmus; 915 struct x86_hybrid_pmu *hybrid_pmu; 916 u8 (*get_hybrid_cpu_type) (void); 917 }; 918 919 struct x86_perf_task_context_opt { 920 int lbr_callstack_users; 921 int lbr_stack_state; 922 int log_id; 923 }; 924 925 struct x86_perf_task_context { 926 u64 lbr_sel; 927 int tos; 928 int valid_lbrs; 929 struct x86_perf_task_context_opt opt; 930 struct lbr_entry lbr[MAX_LBR_ENTRIES]; 931 }; 932 933 struct x86_perf_task_context_arch_lbr { 934 struct x86_perf_task_context_opt opt; 935 struct lbr_entry entries[]; 936 }; 937 938 /* 939 * Add padding to guarantee the 64-byte alignment of the state buffer. 940 * 941 * The structure is dynamically allocated. The size of the LBR state may vary 942 * based on the number of LBR registers. 943 * 944 * Do not put anything after the LBR state. 945 */ 946 struct x86_perf_task_context_arch_lbr_xsave { 947 struct x86_perf_task_context_opt opt; 948 949 union { 950 struct xregs_state xsave; 951 struct { 952 struct fxregs_state i387; 953 struct xstate_header header; 954 struct arch_lbr_state lbr; 955 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 956 }; 957 }; 958 959 #define x86_add_quirk(func_) \ 960 do { \ 961 static struct x86_pmu_quirk __quirk __initdata = { \ 962 .func = func_, \ 963 }; \ 964 __quirk.next = x86_pmu.quirks; \ 965 x86_pmu.quirks = &__quirk; \ 966 } while (0) 967 968 /* 969 * x86_pmu flags 970 */ 971 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 972 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 973 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 974 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 975 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 976 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 977 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 978 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ 979 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ 980 981 #define EVENT_VAR(_id) event_attr_##_id 982 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 983 984 #define EVENT_ATTR(_name, _id) \ 985 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 986 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 987 .id = PERF_COUNT_HW_##_id, \ 988 .event_str = NULL, \ 989 }; 990 991 #define EVENT_ATTR_STR(_name, v, str) \ 992 static struct perf_pmu_events_attr event_attr_##v = { \ 993 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 994 .id = 0, \ 995 .event_str = str, \ 996 }; 997 998 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 999 static struct perf_pmu_events_ht_attr event_attr_##v = { \ 1000 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 1001 .id = 0, \ 1002 .event_str_noht = noht, \ 1003 .event_str_ht = ht, \ 1004 } 1005 1006 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \ 1007 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \ 1008 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\ 1009 .id = 0, \ 1010 .event_str = str, \ 1011 .pmu_type = _pmu, \ 1012 } 1013 1014 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr) 1015 1016 #define FORMAT_ATTR_HYBRID(_name, _pmu) \ 1017 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\ 1018 .attr = __ATTR_RO(_name), \ 1019 .pmu_type = _pmu, \ 1020 } 1021 1022 struct pmu *x86_get_pmu(unsigned int cpu); 1023 extern struct x86_pmu x86_pmu __read_mostly; 1024 1025 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 1026 { 1027 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 1028 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 1029 1030 return &((struct x86_perf_task_context *)ctx)->opt; 1031 } 1032 1033 static inline bool x86_pmu_has_lbr_callstack(void) 1034 { 1035 return x86_pmu.lbr_sel_map && 1036 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 1037 } 1038 1039 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 1040 1041 int x86_perf_event_set_period(struct perf_event *event); 1042 1043 /* 1044 * Generalized hw caching related hw_event table, filled 1045 * in on a per model basis. A value of 0 means 1046 * 'not supported', -1 means 'hw_event makes no sense on 1047 * this CPU', any other value means the raw hw_event 1048 * ID. 1049 */ 1050 1051 #define C(x) PERF_COUNT_HW_CACHE_##x 1052 1053 extern u64 __read_mostly hw_cache_event_ids 1054 [PERF_COUNT_HW_CACHE_MAX] 1055 [PERF_COUNT_HW_CACHE_OP_MAX] 1056 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1057 extern u64 __read_mostly hw_cache_extra_regs 1058 [PERF_COUNT_HW_CACHE_MAX] 1059 [PERF_COUNT_HW_CACHE_OP_MAX] 1060 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1061 1062 u64 x86_perf_event_update(struct perf_event *event); 1063 1064 static inline unsigned int x86_pmu_config_addr(int index) 1065 { 1066 return x86_pmu.eventsel + (x86_pmu.addr_offset ? 1067 x86_pmu.addr_offset(index, true) : index); 1068 } 1069 1070 static inline unsigned int x86_pmu_event_addr(int index) 1071 { 1072 return x86_pmu.perfctr + (x86_pmu.addr_offset ? 1073 x86_pmu.addr_offset(index, false) : index); 1074 } 1075 1076 static inline int x86_pmu_rdpmc_index(int index) 1077 { 1078 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 1079 } 1080 1081 bool check_hw_exists(struct pmu *pmu, int num_counters, 1082 int num_counters_fixed); 1083 1084 int x86_add_exclusive(unsigned int what); 1085 1086 void x86_del_exclusive(unsigned int what); 1087 1088 int x86_reserve_hardware(void); 1089 1090 void x86_release_hardware(void); 1091 1092 int x86_pmu_max_precise(void); 1093 1094 void hw_perf_lbr_event_destroy(struct perf_event *event); 1095 1096 int x86_setup_perfctr(struct perf_event *event); 1097 1098 int x86_pmu_hw_config(struct perf_event *event); 1099 1100 void x86_pmu_disable_all(void); 1101 1102 static inline bool is_counter_pair(struct hw_perf_event *hwc) 1103 { 1104 return hwc->flags & PERF_X86_EVENT_PAIR; 1105 } 1106 1107 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 1108 u64 enable_mask) 1109 { 1110 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1111 1112 if (hwc->extra_reg.reg) 1113 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 1114 1115 /* 1116 * Add enabled Merge event on next counter 1117 * if large increment event being enabled on this counter 1118 */ 1119 if (is_counter_pair(hwc)) 1120 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 1121 1122 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 1123 } 1124 1125 void x86_pmu_enable_all(int added); 1126 1127 int perf_assign_events(struct event_constraint **constraints, int n, 1128 int wmin, int wmax, int gpmax, int *assign); 1129 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 1130 1131 void x86_pmu_stop(struct perf_event *event, int flags); 1132 1133 static inline void x86_pmu_disable_event(struct perf_event *event) 1134 { 1135 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1136 struct hw_perf_event *hwc = &event->hw; 1137 1138 wrmsrl(hwc->config_base, hwc->config & ~disable_mask); 1139 1140 if (is_counter_pair(hwc)) 1141 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 1142 } 1143 1144 void x86_pmu_enable_event(struct perf_event *event); 1145 1146 int x86_pmu_handle_irq(struct pt_regs *regs); 1147 1148 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed, 1149 u64 intel_ctrl); 1150 1151 void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu); 1152 1153 extern struct event_constraint emptyconstraint; 1154 1155 extern struct event_constraint unconstrained; 1156 1157 static inline bool kernel_ip(unsigned long ip) 1158 { 1159 #ifdef CONFIG_X86_32 1160 return ip > PAGE_OFFSET; 1161 #else 1162 return (long)ip < 0; 1163 #endif 1164 } 1165 1166 /* 1167 * Not all PMUs provide the right context information to place the reported IP 1168 * into full context. Specifically segment registers are typically not 1169 * supplied. 1170 * 1171 * Assuming the address is a linear address (it is for IBS), we fake the CS and 1172 * vm86 mode using the known zero-based code segment and 'fix up' the registers 1173 * to reflect this. 1174 * 1175 * Intel PEBS/LBR appear to typically provide the effective address, nothing 1176 * much we can do about that but pray and treat it like a linear address. 1177 */ 1178 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 1179 { 1180 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 1181 if (regs->flags & X86_VM_MASK) 1182 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 1183 regs->ip = ip; 1184 } 1185 1186 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 1187 ssize_t intel_event_sysfs_show(char *page, u64 config); 1188 1189 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1190 char *page); 1191 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1192 char *page); 1193 ssize_t events_hybrid_sysfs_show(struct device *dev, 1194 struct device_attribute *attr, 1195 char *page); 1196 1197 static inline bool fixed_counter_disabled(int i, struct pmu *pmu) 1198 { 1199 u64 intel_ctrl = hybrid(pmu, intel_ctrl); 1200 1201 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); 1202 } 1203 1204 #ifdef CONFIG_CPU_SUP_AMD 1205 1206 int amd_pmu_init(void); 1207 1208 #else /* CONFIG_CPU_SUP_AMD */ 1209 1210 static inline int amd_pmu_init(void) 1211 { 1212 return 0; 1213 } 1214 1215 #endif /* CONFIG_CPU_SUP_AMD */ 1216 1217 static inline int is_pebs_pt(struct perf_event *event) 1218 { 1219 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 1220 } 1221 1222 #ifdef CONFIG_CPU_SUP_INTEL 1223 1224 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 1225 { 1226 struct hw_perf_event *hwc = &event->hw; 1227 unsigned int hw_event, bts_event; 1228 1229 if (event->attr.freq) 1230 return false; 1231 1232 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 1233 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 1234 1235 return hw_event == bts_event && period == 1; 1236 } 1237 1238 static inline bool intel_pmu_has_bts(struct perf_event *event) 1239 { 1240 struct hw_perf_event *hwc = &event->hw; 1241 1242 return intel_pmu_has_bts_period(event, hwc->sample_period); 1243 } 1244 1245 static __always_inline void __intel_pmu_pebs_disable_all(void) 1246 { 1247 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 1248 } 1249 1250 static __always_inline void __intel_pmu_arch_lbr_disable(void) 1251 { 1252 wrmsrl(MSR_ARCH_LBR_CTL, 0); 1253 } 1254 1255 static __always_inline void __intel_pmu_lbr_disable(void) 1256 { 1257 u64 debugctl; 1258 1259 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1260 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1261 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1262 } 1263 1264 int intel_pmu_save_and_restart(struct perf_event *event); 1265 1266 struct event_constraint * 1267 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 1268 struct perf_event *event); 1269 1270 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1271 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 1272 1273 int intel_pmu_init(void); 1274 1275 void init_debug_store_on_cpu(int cpu); 1276 1277 void fini_debug_store_on_cpu(int cpu); 1278 1279 void release_ds_buffers(void); 1280 1281 void reserve_ds_buffers(void); 1282 1283 void release_lbr_buffers(void); 1284 1285 void reserve_lbr_buffers(void); 1286 1287 extern struct event_constraint bts_constraint; 1288 extern struct event_constraint vlbr_constraint; 1289 1290 void intel_pmu_enable_bts(u64 config); 1291 1292 void intel_pmu_disable_bts(void); 1293 1294 int intel_pmu_drain_bts_buffer(void); 1295 1296 extern struct event_constraint intel_core2_pebs_event_constraints[]; 1297 1298 extern struct event_constraint intel_atom_pebs_event_constraints[]; 1299 1300 extern struct event_constraint intel_slm_pebs_event_constraints[]; 1301 1302 extern struct event_constraint intel_glm_pebs_event_constraints[]; 1303 1304 extern struct event_constraint intel_glp_pebs_event_constraints[]; 1305 1306 extern struct event_constraint intel_grt_pebs_event_constraints[]; 1307 1308 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1309 1310 extern struct event_constraint intel_westmere_pebs_event_constraints[]; 1311 1312 extern struct event_constraint intel_snb_pebs_event_constraints[]; 1313 1314 extern struct event_constraint intel_ivb_pebs_event_constraints[]; 1315 1316 extern struct event_constraint intel_hsw_pebs_event_constraints[]; 1317 1318 extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1319 1320 extern struct event_constraint intel_skl_pebs_event_constraints[]; 1321 1322 extern struct event_constraint intel_icl_pebs_event_constraints[]; 1323 1324 extern struct event_constraint intel_spr_pebs_event_constraints[]; 1325 1326 struct event_constraint *intel_pebs_constraints(struct perf_event *event); 1327 1328 void intel_pmu_pebs_add(struct perf_event *event); 1329 1330 void intel_pmu_pebs_del(struct perf_event *event); 1331 1332 void intel_pmu_pebs_enable(struct perf_event *event); 1333 1334 void intel_pmu_pebs_disable(struct perf_event *event); 1335 1336 void intel_pmu_pebs_enable_all(void); 1337 1338 void intel_pmu_pebs_disable_all(void); 1339 1340 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); 1341 1342 void intel_pmu_auto_reload_read(struct perf_event *event); 1343 1344 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1345 1346 void intel_ds_init(void); 1347 1348 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 1349 struct perf_event_context *next); 1350 1351 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); 1352 1353 u64 lbr_from_signext_quirk_wr(u64 val); 1354 1355 void intel_pmu_lbr_reset(void); 1356 1357 void intel_pmu_lbr_reset_32(void); 1358 1359 void intel_pmu_lbr_reset_64(void); 1360 1361 void intel_pmu_lbr_add(struct perf_event *event); 1362 1363 void intel_pmu_lbr_del(struct perf_event *event); 1364 1365 void intel_pmu_lbr_enable_all(bool pmi); 1366 1367 void intel_pmu_lbr_disable_all(void); 1368 1369 void intel_pmu_lbr_read(void); 1370 1371 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1372 1373 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1374 1375 void intel_pmu_lbr_save(void *ctx); 1376 1377 void intel_pmu_lbr_restore(void *ctx); 1378 1379 void intel_pmu_lbr_init_core(void); 1380 1381 void intel_pmu_lbr_init_nhm(void); 1382 1383 void intel_pmu_lbr_init_atom(void); 1384 1385 void intel_pmu_lbr_init_slm(void); 1386 1387 void intel_pmu_lbr_init_snb(void); 1388 1389 void intel_pmu_lbr_init_hsw(void); 1390 1391 void intel_pmu_lbr_init_skl(void); 1392 1393 void intel_pmu_lbr_init_knl(void); 1394 1395 void intel_pmu_arch_lbr_init(void); 1396 1397 void intel_pmu_pebs_data_source_nhm(void); 1398 1399 void intel_pmu_pebs_data_source_skl(bool pmem); 1400 1401 int intel_pmu_setup_lbr_filter(struct perf_event *event); 1402 1403 void intel_pt_interrupt(void); 1404 1405 int intel_bts_interrupt(void); 1406 1407 void intel_bts_enable_local(void); 1408 1409 void intel_bts_disable_local(void); 1410 1411 int p4_pmu_init(void); 1412 1413 int p6_pmu_init(void); 1414 1415 int knc_pmu_init(void); 1416 1417 static inline int is_ht_workaround_enabled(void) 1418 { 1419 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 1420 } 1421 1422 #else /* CONFIG_CPU_SUP_INTEL */ 1423 1424 static inline void reserve_ds_buffers(void) 1425 { 1426 } 1427 1428 static inline void release_ds_buffers(void) 1429 { 1430 } 1431 1432 static inline void release_lbr_buffers(void) 1433 { 1434 } 1435 1436 static inline void reserve_lbr_buffers(void) 1437 { 1438 } 1439 1440 static inline int intel_pmu_init(void) 1441 { 1442 return 0; 1443 } 1444 1445 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 1446 { 1447 return 0; 1448 } 1449 1450 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1451 { 1452 } 1453 1454 static inline int is_ht_workaround_enabled(void) 1455 { 1456 return 0; 1457 } 1458 #endif /* CONFIG_CPU_SUP_INTEL */ 1459 1460 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 1461 int zhaoxin_pmu_init(void); 1462 #else 1463 static inline int zhaoxin_pmu_init(void) 1464 { 1465 return 0; 1466 } 1467 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1468