1 /* 2 * Performance events x86 architecture header 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 17 #include <asm/intel_ds.h> 18 19 /* To enable MSR tracing please use the generic trace points. */ 20 21 /* 22 * | NHM/WSM | SNB | 23 * register ------------------------------- 24 * | HT | no HT | HT | no HT | 25 *----------------------------------------- 26 * offcore | core | core | cpu | core | 27 * lbr_sel | core | core | cpu | core | 28 * ld_lat | cpu | core | cpu | core | 29 *----------------------------------------- 30 * 31 * Given that there is a small number of shared regs, 32 * we can pre-allocate their slot in the per-cpu 33 * per-core reg tables. 34 */ 35 enum extra_reg_type { 36 EXTRA_REG_NONE = -1, /* not used */ 37 38 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 39 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 40 EXTRA_REG_LBR = 2, /* lbr_select */ 41 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 42 EXTRA_REG_FE = 4, /* fe_* */ 43 44 EXTRA_REG_MAX /* number of entries needed */ 45 }; 46 47 struct event_constraint { 48 union { 49 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 50 u64 idxmsk64; 51 }; 52 u64 code; 53 u64 cmask; 54 int weight; 55 int overlap; 56 int flags; 57 unsigned int size; 58 }; 59 60 static inline bool constraint_match(struct event_constraint *c, u64 ecode) 61 { 62 return ((ecode & c->cmask) - c->code) <= (u64)c->size; 63 } 64 65 /* 66 * struct hw_perf_event.flags flags 67 */ 68 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ 69 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ 70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ 71 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */ 72 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */ 73 #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */ 74 #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */ 75 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */ 76 #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */ 77 #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */ 78 #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */ 79 #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */ 80 #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */ 81 82 struct amd_nb { 83 int nb_id; /* NorthBridge id */ 84 int refcnt; /* reference count */ 85 struct perf_event *owners[X86_PMC_IDX_MAX]; 86 struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 87 }; 88 89 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 90 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 91 #define PEBS_OUTPUT_OFFSET 61 92 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 93 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 94 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 95 96 /* 97 * Flags PEBS can handle without an PMI. 98 * 99 * TID can only be handled by flushing at context switch. 100 * REGS_USER can be handled for events limited to ring 3. 101 * 102 */ 103 #define LARGE_PEBS_FLAGS \ 104 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 105 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 106 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 107 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 108 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 109 PERF_SAMPLE_PERIOD) 110 111 #define PEBS_GP_REGS \ 112 ((1ULL << PERF_REG_X86_AX) | \ 113 (1ULL << PERF_REG_X86_BX) | \ 114 (1ULL << PERF_REG_X86_CX) | \ 115 (1ULL << PERF_REG_X86_DX) | \ 116 (1ULL << PERF_REG_X86_DI) | \ 117 (1ULL << PERF_REG_X86_SI) | \ 118 (1ULL << PERF_REG_X86_SP) | \ 119 (1ULL << PERF_REG_X86_BP) | \ 120 (1ULL << PERF_REG_X86_IP) | \ 121 (1ULL << PERF_REG_X86_FLAGS) | \ 122 (1ULL << PERF_REG_X86_R8) | \ 123 (1ULL << PERF_REG_X86_R9) | \ 124 (1ULL << PERF_REG_X86_R10) | \ 125 (1ULL << PERF_REG_X86_R11) | \ 126 (1ULL << PERF_REG_X86_R12) | \ 127 (1ULL << PERF_REG_X86_R13) | \ 128 (1ULL << PERF_REG_X86_R14) | \ 129 (1ULL << PERF_REG_X86_R15)) 130 131 /* 132 * Per register state. 133 */ 134 struct er_account { 135 raw_spinlock_t lock; /* per-core: protect structure */ 136 u64 config; /* extra MSR config */ 137 u64 reg; /* extra MSR number */ 138 atomic_t ref; /* reference count */ 139 }; 140 141 /* 142 * Per core/cpu state 143 * 144 * Used to coordinate shared registers between HT threads or 145 * among events on a single PMU. 146 */ 147 struct intel_shared_regs { 148 struct er_account regs[EXTRA_REG_MAX]; 149 int refcnt; /* per-core: #HT threads */ 150 unsigned core_id; /* per-core: core id */ 151 }; 152 153 enum intel_excl_state_type { 154 INTEL_EXCL_UNUSED = 0, /* counter is unused */ 155 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 156 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 157 }; 158 159 struct intel_excl_states { 160 enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 161 bool sched_started; /* true if scheduling has started */ 162 }; 163 164 struct intel_excl_cntrs { 165 raw_spinlock_t lock; 166 167 struct intel_excl_states states[2]; 168 169 union { 170 u16 has_exclusive[2]; 171 u32 exclusive_present; 172 }; 173 174 int refcnt; /* per-core: #HT threads */ 175 unsigned core_id; /* per-core: core id */ 176 }; 177 178 struct x86_perf_task_context; 179 #define MAX_LBR_ENTRIES 32 180 181 enum { 182 X86_PERF_KFREE_SHARED = 0, 183 X86_PERF_KFREE_EXCL = 1, 184 X86_PERF_KFREE_MAX 185 }; 186 187 struct cpu_hw_events { 188 /* 189 * Generic x86 PMC bits 190 */ 191 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 192 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 193 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 194 int enabled; 195 196 int n_events; /* the # of events in the below arrays */ 197 int n_added; /* the # last events in the below arrays; 198 they've never been enabled yet */ 199 int n_txn; /* the # last events in the below arrays; 200 added in the current transaction */ 201 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 202 u64 tags[X86_PMC_IDX_MAX]; 203 204 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 205 struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 206 207 int n_excl; /* the number of exclusive events */ 208 209 unsigned int txn_flags; 210 int is_fake; 211 212 /* 213 * Intel DebugStore bits 214 */ 215 struct debug_store *ds; 216 void *ds_pebs_vaddr; 217 void *ds_bts_vaddr; 218 u64 pebs_enabled; 219 int n_pebs; 220 int n_large_pebs; 221 int n_pebs_via_pt; 222 int pebs_output; 223 224 /* Current super set of events hardware configuration */ 225 u64 pebs_data_cfg; 226 u64 active_pebs_data_cfg; 227 int pebs_record_size; 228 229 /* 230 * Intel LBR bits 231 */ 232 int lbr_users; 233 int lbr_pebs_users; 234 struct perf_branch_stack lbr_stack; 235 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 236 struct er_account *lbr_sel; 237 u64 br_sel; 238 struct x86_perf_task_context *last_task_ctx; 239 int last_log_id; 240 241 /* 242 * Intel host/guest exclude bits 243 */ 244 u64 intel_ctrl_guest_mask; 245 u64 intel_ctrl_host_mask; 246 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 247 248 /* 249 * Intel checkpoint mask 250 */ 251 u64 intel_cp_status; 252 253 /* 254 * manage shared (per-core, per-cpu) registers 255 * used on Intel NHM/WSM/SNB 256 */ 257 struct intel_shared_regs *shared_regs; 258 /* 259 * manage exclusive counter access between hyperthread 260 */ 261 struct event_constraint *constraint_list; /* in enable order */ 262 struct intel_excl_cntrs *excl_cntrs; 263 int excl_thread_id; /* 0 or 1 */ 264 265 /* 266 * SKL TSX_FORCE_ABORT shadow 267 */ 268 u64 tfa_shadow; 269 270 /* 271 * AMD specific bits 272 */ 273 struct amd_nb *amd_nb; 274 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 275 u64 perf_ctr_virt_mask; 276 int n_pair; /* Large increment events */ 277 278 void *kfree_on_online[X86_PERF_KFREE_MAX]; 279 }; 280 281 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 282 { .idxmsk64 = (n) }, \ 283 .code = (c), \ 284 .size = (e) - (c), \ 285 .cmask = (m), \ 286 .weight = (w), \ 287 .overlap = (o), \ 288 .flags = f, \ 289 } 290 291 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 292 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 293 294 #define EVENT_CONSTRAINT(c, n, m) \ 295 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 296 297 /* 298 * The constraint_match() function only works for 'simple' event codes 299 * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 300 */ 301 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 302 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 303 304 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 305 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 306 0, PERF_X86_EVENT_EXCL) 307 308 /* 309 * The overlap flag marks event constraints with overlapping counter 310 * masks. This is the case if the counter mask of such an event is not 311 * a subset of any other counter mask of a constraint with an equal or 312 * higher weight, e.g.: 313 * 314 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 315 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 316 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 317 * 318 * The event scheduler may not select the correct counter in the first 319 * cycle because it needs to know which subsequent events will be 320 * scheduled. It may fail to schedule the events then. So we set the 321 * overlap flag for such constraints to give the scheduler a hint which 322 * events to select for counter rescheduling. 323 * 324 * Care must be taken as the rescheduling algorithm is O(n!) which 325 * will increase scheduling cycles for an over-committed system 326 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 327 * and its counter masks must be kept at a minimum. 328 */ 329 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 330 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 331 332 /* 333 * Constraint on the Event code. 334 */ 335 #define INTEL_EVENT_CONSTRAINT(c, n) \ 336 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 337 338 /* 339 * Constraint on a range of Event codes 340 */ 341 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 342 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 343 344 /* 345 * Constraint on the Event code + UMask + fixed-mask 346 * 347 * filter mask to validate fixed counter events. 348 * the following filters disqualify for fixed counters: 349 * - inv 350 * - edge 351 * - cnt-mask 352 * - in_tx 353 * - in_tx_checkpointed 354 * The other filters are supported by fixed counters. 355 * The any-thread option is supported starting with v3. 356 */ 357 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 358 #define FIXED_EVENT_CONSTRAINT(c, n) \ 359 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 360 361 /* 362 * Constraint on the Event code + UMask 363 */ 364 #define INTEL_UEVENT_CONSTRAINT(c, n) \ 365 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 366 367 /* Constraint on specific umask bit only + event */ 368 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 369 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 370 371 /* Like UEVENT_CONSTRAINT, but match flags too */ 372 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 373 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 374 375 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 376 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 377 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 378 379 #define INTEL_PLD_CONSTRAINT(c, n) \ 380 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 381 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 382 383 #define INTEL_PST_CONSTRAINT(c, n) \ 384 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 385 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 386 387 /* Event constraint, but match on all event flags too. */ 388 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 389 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 390 391 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 392 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 393 394 /* Check only flags, but allow all event/umask */ 395 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 396 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 397 398 /* Check flags and event code, and set the HSW store flag */ 399 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 400 __EVENT_CONSTRAINT(code, n, \ 401 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 402 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 403 404 /* Check flags and event code, and set the HSW load flag */ 405 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 406 __EVENT_CONSTRAINT(code, n, \ 407 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 408 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 409 410 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 411 __EVENT_CONSTRAINT_RANGE(code, end, n, \ 412 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 413 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 414 415 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 416 __EVENT_CONSTRAINT(code, n, \ 417 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 418 HWEIGHT(n), 0, \ 419 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 420 421 /* Check flags and event code/umask, and set the HSW store flag */ 422 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 423 __EVENT_CONSTRAINT(code, n, \ 424 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 425 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 426 427 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 428 __EVENT_CONSTRAINT(code, n, \ 429 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 430 HWEIGHT(n), 0, \ 431 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 432 433 /* Check flags and event code/umask, and set the HSW load flag */ 434 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 435 __EVENT_CONSTRAINT(code, n, \ 436 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 437 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 438 439 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 440 __EVENT_CONSTRAINT(code, n, \ 441 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 442 HWEIGHT(n), 0, \ 443 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 444 445 /* Check flags and event code/umask, and set the HSW N/A flag */ 446 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 447 __EVENT_CONSTRAINT(code, n, \ 448 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 449 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 450 451 452 /* 453 * We define the end marker as having a weight of -1 454 * to enable blacklisting of events using a counter bitmask 455 * of zero and thus a weight of zero. 456 * The end marker has a weight that cannot possibly be 457 * obtained from counting the bits in the bitmask. 458 */ 459 #define EVENT_CONSTRAINT_END { .weight = -1 } 460 461 /* 462 * Check for end marker with weight == -1 463 */ 464 #define for_each_event_constraint(e, c) \ 465 for ((e) = (c); (e)->weight != -1; (e)++) 466 467 /* 468 * Extra registers for specific events. 469 * 470 * Some events need large masks and require external MSRs. 471 * Those extra MSRs end up being shared for all events on 472 * a PMU and sometimes between PMU of sibling HT threads. 473 * In either case, the kernel needs to handle conflicting 474 * accesses to those extra, shared, regs. The data structure 475 * to manage those registers is stored in cpu_hw_event. 476 */ 477 struct extra_reg { 478 unsigned int event; 479 unsigned int msr; 480 u64 config_mask; 481 u64 valid_mask; 482 int idx; /* per_xxx->regs[] reg index */ 483 bool extra_msr_access; 484 }; 485 486 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 487 .event = (e), \ 488 .msr = (ms), \ 489 .config_mask = (m), \ 490 .valid_mask = (vm), \ 491 .idx = EXTRA_REG_##i, \ 492 .extra_msr_access = true, \ 493 } 494 495 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 496 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 497 498 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 499 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 500 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 501 502 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 503 INTEL_UEVENT_EXTRA_REG(c, \ 504 MSR_PEBS_LD_LAT_THRESHOLD, \ 505 0xffff, \ 506 LDLAT) 507 508 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 509 510 union perf_capabilities { 511 struct { 512 u64 lbr_format:6; 513 u64 pebs_trap:1; 514 u64 pebs_arch_reg:1; 515 u64 pebs_format:4; 516 u64 smm_freeze:1; 517 /* 518 * PMU supports separate counter range for writing 519 * values > 32bit. 520 */ 521 u64 full_width_write:1; 522 u64 pebs_baseline:1; 523 u64 pebs_metrics_available:1; 524 u64 pebs_output_pt_available:1; 525 }; 526 u64 capabilities; 527 }; 528 529 struct x86_pmu_quirk { 530 struct x86_pmu_quirk *next; 531 void (*func)(void); 532 }; 533 534 union x86_pmu_config { 535 struct { 536 u64 event:8, 537 umask:8, 538 usr:1, 539 os:1, 540 edge:1, 541 pc:1, 542 interrupt:1, 543 __reserved1:1, 544 en:1, 545 inv:1, 546 cmask:8, 547 event2:4, 548 __reserved2:4, 549 go:1, 550 ho:1; 551 } bits; 552 u64 value; 553 }; 554 555 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 556 557 enum { 558 x86_lbr_exclusive_lbr, 559 x86_lbr_exclusive_bts, 560 x86_lbr_exclusive_pt, 561 x86_lbr_exclusive_max, 562 }; 563 564 /* 565 * struct x86_pmu - generic x86 pmu 566 */ 567 struct x86_pmu { 568 /* 569 * Generic x86 PMC bits 570 */ 571 const char *name; 572 int version; 573 int (*handle_irq)(struct pt_regs *); 574 void (*disable_all)(void); 575 void (*enable_all)(int added); 576 void (*enable)(struct perf_event *); 577 void (*disable)(struct perf_event *); 578 void (*add)(struct perf_event *); 579 void (*del)(struct perf_event *); 580 void (*read)(struct perf_event *event); 581 int (*hw_config)(struct perf_event *event); 582 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 583 unsigned eventsel; 584 unsigned perfctr; 585 int (*addr_offset)(int index, bool eventsel); 586 int (*rdpmc_index)(int index); 587 u64 (*event_map)(int); 588 int max_events; 589 int num_counters; 590 int num_counters_fixed; 591 int cntval_bits; 592 u64 cntval_mask; 593 union { 594 unsigned long events_maskl; 595 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 596 }; 597 int events_mask_len; 598 int apic; 599 u64 max_period; 600 struct event_constraint * 601 (*get_event_constraints)(struct cpu_hw_events *cpuc, 602 int idx, 603 struct perf_event *event); 604 605 void (*put_event_constraints)(struct cpu_hw_events *cpuc, 606 struct perf_event *event); 607 608 void (*start_scheduling)(struct cpu_hw_events *cpuc); 609 610 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 611 612 void (*stop_scheduling)(struct cpu_hw_events *cpuc); 613 614 struct event_constraint *event_constraints; 615 struct x86_pmu_quirk *quirks; 616 int perfctr_second_write; 617 u64 (*limit_period)(struct perf_event *event, u64 l); 618 619 /* PMI handler bits */ 620 unsigned int late_ack :1, 621 counter_freezing :1; 622 /* 623 * sysfs attrs 624 */ 625 int attr_rdpmc_broken; 626 int attr_rdpmc; 627 struct attribute **format_attrs; 628 629 ssize_t (*events_sysfs_show)(char *page, u64 config); 630 const struct attribute_group **attr_update; 631 632 unsigned long attr_freeze_on_smi; 633 634 /* 635 * CPU Hotplug hooks 636 */ 637 int (*cpu_prepare)(int cpu); 638 void (*cpu_starting)(int cpu); 639 void (*cpu_dying)(int cpu); 640 void (*cpu_dead)(int cpu); 641 642 void (*check_microcode)(void); 643 void (*sched_task)(struct perf_event_context *ctx, 644 bool sched_in); 645 646 /* 647 * Intel Arch Perfmon v2+ 648 */ 649 u64 intel_ctrl; 650 union perf_capabilities intel_cap; 651 652 /* 653 * Intel DebugStore bits 654 */ 655 unsigned int bts :1, 656 bts_active :1, 657 pebs :1, 658 pebs_active :1, 659 pebs_broken :1, 660 pebs_prec_dist :1, 661 pebs_no_tlb :1, 662 pebs_no_isolation :1; 663 int pebs_record_size; 664 int pebs_buffer_size; 665 int max_pebs_events; 666 void (*drain_pebs)(struct pt_regs *regs); 667 struct event_constraint *pebs_constraints; 668 void (*pebs_aliases)(struct perf_event *event); 669 unsigned long large_pebs_flags; 670 u64 rtm_abort_event; 671 672 /* 673 * Intel LBR 674 */ 675 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ 676 int lbr_nr; /* hardware stack size */ 677 u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 678 const int *lbr_sel_map; /* lbr_select mappings */ 679 bool lbr_double_abort; /* duplicated lbr aborts */ 680 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 681 682 /* 683 * Intel PT/LBR/BTS are exclusive 684 */ 685 atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 686 687 /* 688 * perf task context (i.e. struct perf_event_context::task_ctx_data) 689 * switch helper to bridge calls from perf/core to perf/x86. 690 * See struct pmu::swap_task_ctx() usage for examples; 691 */ 692 void (*swap_task_ctx)(struct perf_event_context *prev, 693 struct perf_event_context *next); 694 695 /* 696 * AMD bits 697 */ 698 unsigned int amd_nb_constraints : 1; 699 u64 perf_ctr_pair_en; 700 701 /* 702 * Extra registers for events 703 */ 704 struct extra_reg *extra_regs; 705 unsigned int flags; 706 707 /* 708 * Intel host/guest support (KVM) 709 */ 710 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); 711 712 /* 713 * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 714 */ 715 int (*check_period) (struct perf_event *event, u64 period); 716 717 int (*aux_output_match) (struct perf_event *event); 718 }; 719 720 struct x86_perf_task_context { 721 u64 lbr_from[MAX_LBR_ENTRIES]; 722 u64 lbr_to[MAX_LBR_ENTRIES]; 723 u64 lbr_info[MAX_LBR_ENTRIES]; 724 int tos; 725 int valid_lbrs; 726 int lbr_callstack_users; 727 int lbr_stack_state; 728 int log_id; 729 }; 730 731 #define x86_add_quirk(func_) \ 732 do { \ 733 static struct x86_pmu_quirk __quirk __initdata = { \ 734 .func = func_, \ 735 }; \ 736 __quirk.next = x86_pmu.quirks; \ 737 x86_pmu.quirks = &__quirk; \ 738 } while (0) 739 740 /* 741 * x86_pmu flags 742 */ 743 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 744 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 745 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 746 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 747 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 748 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 749 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 750 751 #define EVENT_VAR(_id) event_attr_##_id 752 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 753 754 #define EVENT_ATTR(_name, _id) \ 755 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 756 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 757 .id = PERF_COUNT_HW_##_id, \ 758 .event_str = NULL, \ 759 }; 760 761 #define EVENT_ATTR_STR(_name, v, str) \ 762 static struct perf_pmu_events_attr event_attr_##v = { \ 763 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 764 .id = 0, \ 765 .event_str = str, \ 766 }; 767 768 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 769 static struct perf_pmu_events_ht_attr event_attr_##v = { \ 770 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 771 .id = 0, \ 772 .event_str_noht = noht, \ 773 .event_str_ht = ht, \ 774 } 775 776 struct pmu *x86_get_pmu(void); 777 extern struct x86_pmu x86_pmu __read_mostly; 778 779 static inline bool x86_pmu_has_lbr_callstack(void) 780 { 781 return x86_pmu.lbr_sel_map && 782 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 783 } 784 785 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 786 787 int x86_perf_event_set_period(struct perf_event *event); 788 789 /* 790 * Generalized hw caching related hw_event table, filled 791 * in on a per model basis. A value of 0 means 792 * 'not supported', -1 means 'hw_event makes no sense on 793 * this CPU', any other value means the raw hw_event 794 * ID. 795 */ 796 797 #define C(x) PERF_COUNT_HW_CACHE_##x 798 799 extern u64 __read_mostly hw_cache_event_ids 800 [PERF_COUNT_HW_CACHE_MAX] 801 [PERF_COUNT_HW_CACHE_OP_MAX] 802 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 803 extern u64 __read_mostly hw_cache_extra_regs 804 [PERF_COUNT_HW_CACHE_MAX] 805 [PERF_COUNT_HW_CACHE_OP_MAX] 806 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 807 808 u64 x86_perf_event_update(struct perf_event *event); 809 810 static inline unsigned int x86_pmu_config_addr(int index) 811 { 812 return x86_pmu.eventsel + (x86_pmu.addr_offset ? 813 x86_pmu.addr_offset(index, true) : index); 814 } 815 816 static inline unsigned int x86_pmu_event_addr(int index) 817 { 818 return x86_pmu.perfctr + (x86_pmu.addr_offset ? 819 x86_pmu.addr_offset(index, false) : index); 820 } 821 822 static inline int x86_pmu_rdpmc_index(int index) 823 { 824 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 825 } 826 827 int x86_add_exclusive(unsigned int what); 828 829 void x86_del_exclusive(unsigned int what); 830 831 int x86_reserve_hardware(void); 832 833 void x86_release_hardware(void); 834 835 int x86_pmu_max_precise(void); 836 837 void hw_perf_lbr_event_destroy(struct perf_event *event); 838 839 int x86_setup_perfctr(struct perf_event *event); 840 841 int x86_pmu_hw_config(struct perf_event *event); 842 843 void x86_pmu_disable_all(void); 844 845 static inline bool is_counter_pair(struct hw_perf_event *hwc) 846 { 847 return hwc->flags & PERF_X86_EVENT_PAIR; 848 } 849 850 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 851 u64 enable_mask) 852 { 853 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 854 855 if (hwc->extra_reg.reg) 856 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 857 858 /* 859 * Add enabled Merge event on next counter 860 * if large increment event being enabled on this counter 861 */ 862 if (is_counter_pair(hwc)) 863 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 864 865 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 866 } 867 868 void x86_pmu_enable_all(int added); 869 870 int perf_assign_events(struct event_constraint **constraints, int n, 871 int wmin, int wmax, int gpmax, int *assign); 872 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 873 874 void x86_pmu_stop(struct perf_event *event, int flags); 875 876 static inline void x86_pmu_disable_event(struct perf_event *event) 877 { 878 struct hw_perf_event *hwc = &event->hw; 879 880 wrmsrl(hwc->config_base, hwc->config); 881 882 if (is_counter_pair(hwc)) 883 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 884 } 885 886 void x86_pmu_enable_event(struct perf_event *event); 887 888 int x86_pmu_handle_irq(struct pt_regs *regs); 889 890 extern struct event_constraint emptyconstraint; 891 892 extern struct event_constraint unconstrained; 893 894 static inline bool kernel_ip(unsigned long ip) 895 { 896 #ifdef CONFIG_X86_32 897 return ip > PAGE_OFFSET; 898 #else 899 return (long)ip < 0; 900 #endif 901 } 902 903 /* 904 * Not all PMUs provide the right context information to place the reported IP 905 * into full context. Specifically segment registers are typically not 906 * supplied. 907 * 908 * Assuming the address is a linear address (it is for IBS), we fake the CS and 909 * vm86 mode using the known zero-based code segment and 'fix up' the registers 910 * to reflect this. 911 * 912 * Intel PEBS/LBR appear to typically provide the effective address, nothing 913 * much we can do about that but pray and treat it like a linear address. 914 */ 915 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 916 { 917 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 918 if (regs->flags & X86_VM_MASK) 919 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 920 regs->ip = ip; 921 } 922 923 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 924 ssize_t intel_event_sysfs_show(char *page, u64 config); 925 926 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 927 char *page); 928 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 929 char *page); 930 931 #ifdef CONFIG_CPU_SUP_AMD 932 933 int amd_pmu_init(void); 934 935 #else /* CONFIG_CPU_SUP_AMD */ 936 937 static inline int amd_pmu_init(void) 938 { 939 return 0; 940 } 941 942 #endif /* CONFIG_CPU_SUP_AMD */ 943 944 static inline int is_pebs_pt(struct perf_event *event) 945 { 946 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 947 } 948 949 #ifdef CONFIG_CPU_SUP_INTEL 950 951 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 952 { 953 struct hw_perf_event *hwc = &event->hw; 954 unsigned int hw_event, bts_event; 955 956 if (event->attr.freq) 957 return false; 958 959 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 960 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 961 962 return hw_event == bts_event && period == 1; 963 } 964 965 static inline bool intel_pmu_has_bts(struct perf_event *event) 966 { 967 struct hw_perf_event *hwc = &event->hw; 968 969 return intel_pmu_has_bts_period(event, hwc->sample_period); 970 } 971 972 int intel_pmu_save_and_restart(struct perf_event *event); 973 974 struct event_constraint * 975 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 976 struct perf_event *event); 977 978 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 979 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 980 981 int intel_pmu_init(void); 982 983 void init_debug_store_on_cpu(int cpu); 984 985 void fini_debug_store_on_cpu(int cpu); 986 987 void release_ds_buffers(void); 988 989 void reserve_ds_buffers(void); 990 991 extern struct event_constraint bts_constraint; 992 993 void intel_pmu_enable_bts(u64 config); 994 995 void intel_pmu_disable_bts(void); 996 997 int intel_pmu_drain_bts_buffer(void); 998 999 extern struct event_constraint intel_core2_pebs_event_constraints[]; 1000 1001 extern struct event_constraint intel_atom_pebs_event_constraints[]; 1002 1003 extern struct event_constraint intel_slm_pebs_event_constraints[]; 1004 1005 extern struct event_constraint intel_glm_pebs_event_constraints[]; 1006 1007 extern struct event_constraint intel_glp_pebs_event_constraints[]; 1008 1009 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1010 1011 extern struct event_constraint intel_westmere_pebs_event_constraints[]; 1012 1013 extern struct event_constraint intel_snb_pebs_event_constraints[]; 1014 1015 extern struct event_constraint intel_ivb_pebs_event_constraints[]; 1016 1017 extern struct event_constraint intel_hsw_pebs_event_constraints[]; 1018 1019 extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1020 1021 extern struct event_constraint intel_skl_pebs_event_constraints[]; 1022 1023 extern struct event_constraint intel_icl_pebs_event_constraints[]; 1024 1025 struct event_constraint *intel_pebs_constraints(struct perf_event *event); 1026 1027 void intel_pmu_pebs_add(struct perf_event *event); 1028 1029 void intel_pmu_pebs_del(struct perf_event *event); 1030 1031 void intel_pmu_pebs_enable(struct perf_event *event); 1032 1033 void intel_pmu_pebs_disable(struct perf_event *event); 1034 1035 void intel_pmu_pebs_enable_all(void); 1036 1037 void intel_pmu_pebs_disable_all(void); 1038 1039 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); 1040 1041 void intel_pmu_auto_reload_read(struct perf_event *event); 1042 1043 void intel_pmu_store_pebs_lbrs(struct pebs_lbr *lbr); 1044 1045 void intel_ds_init(void); 1046 1047 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 1048 struct perf_event_context *next); 1049 1050 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); 1051 1052 u64 lbr_from_signext_quirk_wr(u64 val); 1053 1054 void intel_pmu_lbr_reset(void); 1055 1056 void intel_pmu_lbr_add(struct perf_event *event); 1057 1058 void intel_pmu_lbr_del(struct perf_event *event); 1059 1060 void intel_pmu_lbr_enable_all(bool pmi); 1061 1062 void intel_pmu_lbr_disable_all(void); 1063 1064 void intel_pmu_lbr_read(void); 1065 1066 void intel_pmu_lbr_init_core(void); 1067 1068 void intel_pmu_lbr_init_nhm(void); 1069 1070 void intel_pmu_lbr_init_atom(void); 1071 1072 void intel_pmu_lbr_init_slm(void); 1073 1074 void intel_pmu_lbr_init_snb(void); 1075 1076 void intel_pmu_lbr_init_hsw(void); 1077 1078 void intel_pmu_lbr_init_skl(void); 1079 1080 void intel_pmu_lbr_init_knl(void); 1081 1082 void intel_pmu_pebs_data_source_nhm(void); 1083 1084 void intel_pmu_pebs_data_source_skl(bool pmem); 1085 1086 int intel_pmu_setup_lbr_filter(struct perf_event *event); 1087 1088 void intel_pt_interrupt(void); 1089 1090 int intel_bts_interrupt(void); 1091 1092 void intel_bts_enable_local(void); 1093 1094 void intel_bts_disable_local(void); 1095 1096 int p4_pmu_init(void); 1097 1098 int p6_pmu_init(void); 1099 1100 int knc_pmu_init(void); 1101 1102 static inline int is_ht_workaround_enabled(void) 1103 { 1104 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 1105 } 1106 1107 #else /* CONFIG_CPU_SUP_INTEL */ 1108 1109 static inline void reserve_ds_buffers(void) 1110 { 1111 } 1112 1113 static inline void release_ds_buffers(void) 1114 { 1115 } 1116 1117 static inline int intel_pmu_init(void) 1118 { 1119 return 0; 1120 } 1121 1122 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 1123 { 1124 return 0; 1125 } 1126 1127 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1128 { 1129 } 1130 1131 static inline int is_ht_workaround_enabled(void) 1132 { 1133 return 0; 1134 } 1135 #endif /* CONFIG_CPU_SUP_INTEL */ 1136