1 /* 2 * Performance events x86 architecture header 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 17 #include <asm/fpu/xstate.h> 18 #include <asm/intel_ds.h> 19 #include <asm/cpu.h> 20 21 /* To enable MSR tracing please use the generic trace points. */ 22 23 /* 24 * | NHM/WSM | SNB | 25 * register ------------------------------- 26 * | HT | no HT | HT | no HT | 27 *----------------------------------------- 28 * offcore | core | core | cpu | core | 29 * lbr_sel | core | core | cpu | core | 30 * ld_lat | cpu | core | cpu | core | 31 *----------------------------------------- 32 * 33 * Given that there is a small number of shared regs, 34 * we can pre-allocate their slot in the per-cpu 35 * per-core reg tables. 36 */ 37 enum extra_reg_type { 38 EXTRA_REG_NONE = -1, /* not used */ 39 40 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 41 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 42 EXTRA_REG_LBR = 2, /* lbr_select */ 43 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 44 EXTRA_REG_FE = 4, /* fe_* */ 45 46 EXTRA_REG_MAX /* number of entries needed */ 47 }; 48 49 struct event_constraint { 50 union { 51 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 52 u64 idxmsk64; 53 }; 54 u64 code; 55 u64 cmask; 56 int weight; 57 int overlap; 58 int flags; 59 unsigned int size; 60 }; 61 62 static inline bool constraint_match(struct event_constraint *c, u64 ecode) 63 { 64 return ((ecode & c->cmask) - c->code) <= (u64)c->size; 65 } 66 67 /* 68 * struct hw_perf_event.flags flags 69 */ 70 #define PERF_X86_EVENT_PEBS_LDLAT 0x00001 /* ld+ldlat data address sampling */ 71 #define PERF_X86_EVENT_PEBS_ST 0x00002 /* st data address sampling */ 72 #define PERF_X86_EVENT_PEBS_ST_HSW 0x00004 /* haswell style datala, store */ 73 #define PERF_X86_EVENT_PEBS_LD_HSW 0x00008 /* haswell style datala, load */ 74 #define PERF_X86_EVENT_PEBS_NA_HSW 0x00010 /* haswell style datala, unknown */ 75 #define PERF_X86_EVENT_EXCL 0x00020 /* HT exclusivity on counter */ 76 #define PERF_X86_EVENT_DYNAMIC 0x00040 /* dynamic alloc'd constraint */ 77 78 #define PERF_X86_EVENT_EXCL_ACCT 0x00100 /* accounted EXCL event */ 79 #define PERF_X86_EVENT_AUTO_RELOAD 0x00200 /* use PEBS auto-reload */ 80 #define PERF_X86_EVENT_LARGE_PEBS 0x00400 /* use large PEBS */ 81 #define PERF_X86_EVENT_PEBS_VIA_PT 0x00800 /* use PT buffer for PEBS */ 82 #define PERF_X86_EVENT_PAIR 0x01000 /* Large Increment per Cycle */ 83 #define PERF_X86_EVENT_LBR_SELECT 0x02000 /* Save/Restore MSR_LBR_SELECT */ 84 #define PERF_X86_EVENT_TOPDOWN 0x04000 /* Count Topdown slots/metrics events */ 85 #define PERF_X86_EVENT_PEBS_STLAT 0x08000 /* st+stlat data address sampling */ 86 #define PERF_X86_EVENT_AMD_BRS 0x10000 /* AMD Branch Sampling */ 87 #define PERF_X86_EVENT_PEBS_LAT_HYBRID 0x20000 /* ld and st lat for hybrid */ 88 89 static inline bool is_topdown_count(struct perf_event *event) 90 { 91 return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 92 } 93 94 static inline bool is_metric_event(struct perf_event *event) 95 { 96 u64 config = event->attr.config; 97 98 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 99 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 100 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 101 } 102 103 static inline bool is_slots_event(struct perf_event *event) 104 { 105 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 106 } 107 108 static inline bool is_topdown_event(struct perf_event *event) 109 { 110 return is_metric_event(event) || is_slots_event(event); 111 } 112 113 struct amd_nb { 114 int nb_id; /* NorthBridge id */ 115 int refcnt; /* reference count */ 116 struct perf_event *owners[X86_PMC_IDX_MAX]; 117 struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 118 }; 119 120 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 121 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 122 #define PEBS_OUTPUT_OFFSET 61 123 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 124 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 125 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 126 127 /* 128 * Flags PEBS can handle without an PMI. 129 * 130 * TID can only be handled by flushing at context switch. 131 * REGS_USER can be handled for events limited to ring 3. 132 * 133 */ 134 #define LARGE_PEBS_FLAGS \ 135 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 136 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 137 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 138 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 139 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 140 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \ 141 PERF_SAMPLE_WEIGHT_TYPE) 142 143 #define PEBS_GP_REGS \ 144 ((1ULL << PERF_REG_X86_AX) | \ 145 (1ULL << PERF_REG_X86_BX) | \ 146 (1ULL << PERF_REG_X86_CX) | \ 147 (1ULL << PERF_REG_X86_DX) | \ 148 (1ULL << PERF_REG_X86_DI) | \ 149 (1ULL << PERF_REG_X86_SI) | \ 150 (1ULL << PERF_REG_X86_SP) | \ 151 (1ULL << PERF_REG_X86_BP) | \ 152 (1ULL << PERF_REG_X86_IP) | \ 153 (1ULL << PERF_REG_X86_FLAGS) | \ 154 (1ULL << PERF_REG_X86_R8) | \ 155 (1ULL << PERF_REG_X86_R9) | \ 156 (1ULL << PERF_REG_X86_R10) | \ 157 (1ULL << PERF_REG_X86_R11) | \ 158 (1ULL << PERF_REG_X86_R12) | \ 159 (1ULL << PERF_REG_X86_R13) | \ 160 (1ULL << PERF_REG_X86_R14) | \ 161 (1ULL << PERF_REG_X86_R15)) 162 163 /* 164 * Per register state. 165 */ 166 struct er_account { 167 raw_spinlock_t lock; /* per-core: protect structure */ 168 u64 config; /* extra MSR config */ 169 u64 reg; /* extra MSR number */ 170 atomic_t ref; /* reference count */ 171 }; 172 173 /* 174 * Per core/cpu state 175 * 176 * Used to coordinate shared registers between HT threads or 177 * among events on a single PMU. 178 */ 179 struct intel_shared_regs { 180 struct er_account regs[EXTRA_REG_MAX]; 181 int refcnt; /* per-core: #HT threads */ 182 unsigned core_id; /* per-core: core id */ 183 }; 184 185 enum intel_excl_state_type { 186 INTEL_EXCL_UNUSED = 0, /* counter is unused */ 187 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 188 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 189 }; 190 191 struct intel_excl_states { 192 enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 193 bool sched_started; /* true if scheduling has started */ 194 }; 195 196 struct intel_excl_cntrs { 197 raw_spinlock_t lock; 198 199 struct intel_excl_states states[2]; 200 201 union { 202 u16 has_exclusive[2]; 203 u32 exclusive_present; 204 }; 205 206 int refcnt; /* per-core: #HT threads */ 207 unsigned core_id; /* per-core: core id */ 208 }; 209 210 struct x86_perf_task_context; 211 #define MAX_LBR_ENTRIES 32 212 213 enum { 214 LBR_FORMAT_32 = 0x00, 215 LBR_FORMAT_LIP = 0x01, 216 LBR_FORMAT_EIP = 0x02, 217 LBR_FORMAT_EIP_FLAGS = 0x03, 218 LBR_FORMAT_EIP_FLAGS2 = 0x04, 219 LBR_FORMAT_INFO = 0x05, 220 LBR_FORMAT_TIME = 0x06, 221 LBR_FORMAT_INFO2 = 0x07, 222 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2, 223 }; 224 225 enum { 226 X86_PERF_KFREE_SHARED = 0, 227 X86_PERF_KFREE_EXCL = 1, 228 X86_PERF_KFREE_MAX 229 }; 230 231 struct cpu_hw_events { 232 /* 233 * Generic x86 PMC bits 234 */ 235 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 236 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 237 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 238 int enabled; 239 240 int n_events; /* the # of events in the below arrays */ 241 int n_added; /* the # last events in the below arrays; 242 they've never been enabled yet */ 243 int n_txn; /* the # last events in the below arrays; 244 added in the current transaction */ 245 int n_txn_pair; 246 int n_txn_metric; 247 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 248 u64 tags[X86_PMC_IDX_MAX]; 249 250 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 251 struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 252 253 int n_excl; /* the number of exclusive events */ 254 255 unsigned int txn_flags; 256 int is_fake; 257 258 /* 259 * Intel DebugStore bits 260 */ 261 struct debug_store *ds; 262 void *ds_pebs_vaddr; 263 void *ds_bts_vaddr; 264 u64 pebs_enabled; 265 int n_pebs; 266 int n_large_pebs; 267 int n_pebs_via_pt; 268 int pebs_output; 269 270 /* Current super set of events hardware configuration */ 271 u64 pebs_data_cfg; 272 u64 active_pebs_data_cfg; 273 int pebs_record_size; 274 275 /* 276 * Intel LBR bits 277 */ 278 int lbr_users; 279 int lbr_pebs_users; 280 struct perf_branch_stack lbr_stack; 281 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 282 union { 283 struct er_account *lbr_sel; 284 struct er_account *lbr_ctl; 285 }; 286 u64 br_sel; 287 void *last_task_ctx; 288 int last_log_id; 289 int lbr_select; 290 void *lbr_xsave; 291 292 /* 293 * Intel host/guest exclude bits 294 */ 295 u64 intel_ctrl_guest_mask; 296 u64 intel_ctrl_host_mask; 297 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 298 299 /* 300 * Intel checkpoint mask 301 */ 302 u64 intel_cp_status; 303 304 /* 305 * manage shared (per-core, per-cpu) registers 306 * used on Intel NHM/WSM/SNB 307 */ 308 struct intel_shared_regs *shared_regs; 309 /* 310 * manage exclusive counter access between hyperthread 311 */ 312 struct event_constraint *constraint_list; /* in enable order */ 313 struct intel_excl_cntrs *excl_cntrs; 314 int excl_thread_id; /* 0 or 1 */ 315 316 /* 317 * SKL TSX_FORCE_ABORT shadow 318 */ 319 u64 tfa_shadow; 320 321 /* 322 * Perf Metrics 323 */ 324 /* number of accepted metrics events */ 325 int n_metric; 326 327 /* 328 * AMD specific bits 329 */ 330 struct amd_nb *amd_nb; 331 int brs_active; /* BRS is enabled */ 332 333 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 334 u64 perf_ctr_virt_mask; 335 int n_pair; /* Large increment events */ 336 337 void *kfree_on_online[X86_PERF_KFREE_MAX]; 338 339 struct pmu *pmu; 340 }; 341 342 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 343 { .idxmsk64 = (n) }, \ 344 .code = (c), \ 345 .size = (e) - (c), \ 346 .cmask = (m), \ 347 .weight = (w), \ 348 .overlap = (o), \ 349 .flags = f, \ 350 } 351 352 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 353 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 354 355 #define EVENT_CONSTRAINT(c, n, m) \ 356 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 357 358 /* 359 * The constraint_match() function only works for 'simple' event codes 360 * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 361 */ 362 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 363 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 364 365 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 366 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 367 0, PERF_X86_EVENT_EXCL) 368 369 /* 370 * The overlap flag marks event constraints with overlapping counter 371 * masks. This is the case if the counter mask of such an event is not 372 * a subset of any other counter mask of a constraint with an equal or 373 * higher weight, e.g.: 374 * 375 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 376 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 377 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 378 * 379 * The event scheduler may not select the correct counter in the first 380 * cycle because it needs to know which subsequent events will be 381 * scheduled. It may fail to schedule the events then. So we set the 382 * overlap flag for such constraints to give the scheduler a hint which 383 * events to select for counter rescheduling. 384 * 385 * Care must be taken as the rescheduling algorithm is O(n!) which 386 * will increase scheduling cycles for an over-committed system 387 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 388 * and its counter masks must be kept at a minimum. 389 */ 390 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 391 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 392 393 /* 394 * Constraint on the Event code. 395 */ 396 #define INTEL_EVENT_CONSTRAINT(c, n) \ 397 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 398 399 /* 400 * Constraint on a range of Event codes 401 */ 402 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 403 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 404 405 /* 406 * Constraint on the Event code + UMask + fixed-mask 407 * 408 * filter mask to validate fixed counter events. 409 * the following filters disqualify for fixed counters: 410 * - inv 411 * - edge 412 * - cnt-mask 413 * - in_tx 414 * - in_tx_checkpointed 415 * The other filters are supported by fixed counters. 416 * The any-thread option is supported starting with v3. 417 */ 418 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 419 #define FIXED_EVENT_CONSTRAINT(c, n) \ 420 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 421 422 /* 423 * The special metric counters do not actually exist. They are calculated from 424 * the combination of the FxCtr3 + MSR_PERF_METRICS. 425 * 426 * The special metric counters are mapped to a dummy offset for the scheduler. 427 * The sharing between multiple users of the same metric without multiplexing 428 * is not allowed, even though the hardware supports that in principle. 429 */ 430 431 #define METRIC_EVENT_CONSTRAINT(c, n) \ 432 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 433 INTEL_ARCH_EVENT_MASK) 434 435 /* 436 * Constraint on the Event code + UMask 437 */ 438 #define INTEL_UEVENT_CONSTRAINT(c, n) \ 439 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 440 441 /* Constraint on specific umask bit only + event */ 442 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 443 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 444 445 /* Like UEVENT_CONSTRAINT, but match flags too */ 446 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 447 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 448 449 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 450 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 451 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 452 453 #define INTEL_PLD_CONSTRAINT(c, n) \ 454 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 455 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 456 457 #define INTEL_PSD_CONSTRAINT(c, n) \ 458 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 459 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT) 460 461 #define INTEL_PST_CONSTRAINT(c, n) \ 462 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 463 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 464 465 #define INTEL_HYBRID_LAT_CONSTRAINT(c, n) \ 466 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 467 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID) 468 469 /* Event constraint, but match on all event flags too. */ 470 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 471 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 472 473 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 474 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 475 476 /* Check only flags, but allow all event/umask */ 477 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 478 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 479 480 /* Check flags and event code, and set the HSW store flag */ 481 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 482 __EVENT_CONSTRAINT(code, n, \ 483 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 484 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 485 486 /* Check flags and event code, and set the HSW load flag */ 487 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 488 __EVENT_CONSTRAINT(code, n, \ 489 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 490 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 491 492 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 493 __EVENT_CONSTRAINT_RANGE(code, end, n, \ 494 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 495 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 496 497 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 498 __EVENT_CONSTRAINT(code, n, \ 499 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 500 HWEIGHT(n), 0, \ 501 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 502 503 /* Check flags and event code/umask, and set the HSW store flag */ 504 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 505 __EVENT_CONSTRAINT(code, n, \ 506 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 507 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 508 509 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 510 __EVENT_CONSTRAINT(code, n, \ 511 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 512 HWEIGHT(n), 0, \ 513 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 514 515 /* Check flags and event code/umask, and set the HSW load flag */ 516 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 517 __EVENT_CONSTRAINT(code, n, \ 518 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 519 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 520 521 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 522 __EVENT_CONSTRAINT(code, n, \ 523 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 524 HWEIGHT(n), 0, \ 525 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 526 527 /* Check flags and event code/umask, and set the HSW N/A flag */ 528 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 529 __EVENT_CONSTRAINT(code, n, \ 530 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 531 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 532 533 534 /* 535 * We define the end marker as having a weight of -1 536 * to enable blacklisting of events using a counter bitmask 537 * of zero and thus a weight of zero. 538 * The end marker has a weight that cannot possibly be 539 * obtained from counting the bits in the bitmask. 540 */ 541 #define EVENT_CONSTRAINT_END { .weight = -1 } 542 543 /* 544 * Check for end marker with weight == -1 545 */ 546 #define for_each_event_constraint(e, c) \ 547 for ((e) = (c); (e)->weight != -1; (e)++) 548 549 /* 550 * Extra registers for specific events. 551 * 552 * Some events need large masks and require external MSRs. 553 * Those extra MSRs end up being shared for all events on 554 * a PMU and sometimes between PMU of sibling HT threads. 555 * In either case, the kernel needs to handle conflicting 556 * accesses to those extra, shared, regs. The data structure 557 * to manage those registers is stored in cpu_hw_event. 558 */ 559 struct extra_reg { 560 unsigned int event; 561 unsigned int msr; 562 u64 config_mask; 563 u64 valid_mask; 564 int idx; /* per_xxx->regs[] reg index */ 565 bool extra_msr_access; 566 }; 567 568 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 569 .event = (e), \ 570 .msr = (ms), \ 571 .config_mask = (m), \ 572 .valid_mask = (vm), \ 573 .idx = EXTRA_REG_##i, \ 574 .extra_msr_access = true, \ 575 } 576 577 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 578 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 579 580 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 581 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 582 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 583 584 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 585 INTEL_UEVENT_EXTRA_REG(c, \ 586 MSR_PEBS_LD_LAT_THRESHOLD, \ 587 0xffff, \ 588 LDLAT) 589 590 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 591 592 union perf_capabilities { 593 struct { 594 u64 lbr_format:6; 595 u64 pebs_trap:1; 596 u64 pebs_arch_reg:1; 597 u64 pebs_format:4; 598 u64 smm_freeze:1; 599 /* 600 * PMU supports separate counter range for writing 601 * values > 32bit. 602 */ 603 u64 full_width_write:1; 604 u64 pebs_baseline:1; 605 u64 perf_metrics:1; 606 u64 pebs_output_pt_available:1; 607 u64 anythread_deprecated:1; 608 }; 609 u64 capabilities; 610 }; 611 612 struct x86_pmu_quirk { 613 struct x86_pmu_quirk *next; 614 void (*func)(void); 615 }; 616 617 union x86_pmu_config { 618 struct { 619 u64 event:8, 620 umask:8, 621 usr:1, 622 os:1, 623 edge:1, 624 pc:1, 625 interrupt:1, 626 __reserved1:1, 627 en:1, 628 inv:1, 629 cmask:8, 630 event2:4, 631 __reserved2:4, 632 go:1, 633 ho:1; 634 } bits; 635 u64 value; 636 }; 637 638 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 639 640 enum { 641 x86_lbr_exclusive_lbr, 642 x86_lbr_exclusive_bts, 643 x86_lbr_exclusive_pt, 644 x86_lbr_exclusive_max, 645 }; 646 647 #define PERF_PEBS_DATA_SOURCE_MAX 0x10 648 649 struct x86_hybrid_pmu { 650 struct pmu pmu; 651 const char *name; 652 u8 cpu_type; 653 cpumask_t supported_cpus; 654 union perf_capabilities intel_cap; 655 u64 intel_ctrl; 656 int max_pebs_events; 657 int num_counters; 658 int num_counters_fixed; 659 struct event_constraint unconstrained; 660 661 u64 hw_cache_event_ids 662 [PERF_COUNT_HW_CACHE_MAX] 663 [PERF_COUNT_HW_CACHE_OP_MAX] 664 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 665 u64 hw_cache_extra_regs 666 [PERF_COUNT_HW_CACHE_MAX] 667 [PERF_COUNT_HW_CACHE_OP_MAX] 668 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 669 struct event_constraint *event_constraints; 670 struct event_constraint *pebs_constraints; 671 struct extra_reg *extra_regs; 672 673 unsigned int late_ack :1, 674 mid_ack :1, 675 enabled_ack :1; 676 677 u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX]; 678 }; 679 680 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) 681 { 682 return container_of(pmu, struct x86_hybrid_pmu, pmu); 683 } 684 685 extern struct static_key_false perf_is_hybrid; 686 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid) 687 688 #define hybrid(_pmu, _field) \ 689 (*({ \ 690 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \ 691 \ 692 if (is_hybrid() && (_pmu)) \ 693 __Fp = &hybrid_pmu(_pmu)->_field; \ 694 \ 695 __Fp; \ 696 })) 697 698 #define hybrid_var(_pmu, _var) \ 699 (*({ \ 700 typeof(&_var) __Fp = &_var; \ 701 \ 702 if (is_hybrid() && (_pmu)) \ 703 __Fp = &hybrid_pmu(_pmu)->_var; \ 704 \ 705 __Fp; \ 706 })) 707 708 #define hybrid_bit(_pmu, _field) \ 709 ({ \ 710 bool __Fp = x86_pmu._field; \ 711 \ 712 if (is_hybrid() && (_pmu)) \ 713 __Fp = hybrid_pmu(_pmu)->_field; \ 714 \ 715 __Fp; \ 716 }) 717 718 enum hybrid_pmu_type { 719 hybrid_big = 0x40, 720 hybrid_small = 0x20, 721 722 hybrid_big_small = hybrid_big | hybrid_small, 723 }; 724 725 #define X86_HYBRID_PMU_ATOM_IDX 0 726 #define X86_HYBRID_PMU_CORE_IDX 1 727 728 #define X86_HYBRID_NUM_PMUS 2 729 730 /* 731 * struct x86_pmu - generic x86 pmu 732 */ 733 struct x86_pmu { 734 /* 735 * Generic x86 PMC bits 736 */ 737 const char *name; 738 int version; 739 int (*handle_irq)(struct pt_regs *); 740 void (*disable_all)(void); 741 void (*enable_all)(int added); 742 void (*enable)(struct perf_event *); 743 void (*disable)(struct perf_event *); 744 void (*assign)(struct perf_event *event, int idx); 745 void (*add)(struct perf_event *); 746 void (*del)(struct perf_event *); 747 void (*read)(struct perf_event *event); 748 int (*hw_config)(struct perf_event *event); 749 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 750 unsigned eventsel; 751 unsigned perfctr; 752 int (*addr_offset)(int index, bool eventsel); 753 int (*rdpmc_index)(int index); 754 u64 (*event_map)(int); 755 int max_events; 756 int num_counters; 757 int num_counters_fixed; 758 int cntval_bits; 759 u64 cntval_mask; 760 union { 761 unsigned long events_maskl; 762 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 763 }; 764 int events_mask_len; 765 int apic; 766 u64 max_period; 767 struct event_constraint * 768 (*get_event_constraints)(struct cpu_hw_events *cpuc, 769 int idx, 770 struct perf_event *event); 771 772 void (*put_event_constraints)(struct cpu_hw_events *cpuc, 773 struct perf_event *event); 774 775 void (*start_scheduling)(struct cpu_hw_events *cpuc); 776 777 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 778 779 void (*stop_scheduling)(struct cpu_hw_events *cpuc); 780 781 struct event_constraint *event_constraints; 782 struct x86_pmu_quirk *quirks; 783 int perfctr_second_write; 784 u64 (*limit_period)(struct perf_event *event, u64 l); 785 786 /* PMI handler bits */ 787 unsigned int late_ack :1, 788 mid_ack :1, 789 enabled_ack :1; 790 /* 791 * sysfs attrs 792 */ 793 int attr_rdpmc_broken; 794 int attr_rdpmc; 795 struct attribute **format_attrs; 796 797 ssize_t (*events_sysfs_show)(char *page, u64 config); 798 const struct attribute_group **attr_update; 799 800 unsigned long attr_freeze_on_smi; 801 802 /* 803 * CPU Hotplug hooks 804 */ 805 int (*cpu_prepare)(int cpu); 806 void (*cpu_starting)(int cpu); 807 void (*cpu_dying)(int cpu); 808 void (*cpu_dead)(int cpu); 809 810 void (*check_microcode)(void); 811 void (*sched_task)(struct perf_event_context *ctx, 812 bool sched_in); 813 814 /* 815 * Intel Arch Perfmon v2+ 816 */ 817 u64 intel_ctrl; 818 union perf_capabilities intel_cap; 819 820 /* 821 * Intel DebugStore bits 822 */ 823 unsigned int bts :1, 824 bts_active :1, 825 pebs :1, 826 pebs_active :1, 827 pebs_broken :1, 828 pebs_prec_dist :1, 829 pebs_no_tlb :1, 830 pebs_no_isolation :1, 831 pebs_block :1, 832 pebs_ept :1; 833 int pebs_record_size; 834 int pebs_buffer_size; 835 int max_pebs_events; 836 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 837 struct event_constraint *pebs_constraints; 838 void (*pebs_aliases)(struct perf_event *event); 839 u64 (*pebs_latency_data)(struct perf_event *event, u64 status); 840 unsigned long large_pebs_flags; 841 u64 rtm_abort_event; 842 u64 pebs_capable; 843 844 /* 845 * Intel LBR 846 */ 847 unsigned int lbr_tos, lbr_from, lbr_to, 848 lbr_info, lbr_nr; /* LBR base regs and size */ 849 union { 850 u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 851 u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 852 }; 853 union { 854 const int *lbr_sel_map; /* lbr_select mappings */ 855 int *lbr_ctl_map; /* LBR_CTL mappings */ 856 }; 857 bool lbr_double_abort; /* duplicated lbr aborts */ 858 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 859 860 unsigned int lbr_has_info:1; 861 unsigned int lbr_has_tsx:1; 862 unsigned int lbr_from_flags:1; 863 unsigned int lbr_to_cycles:1; 864 865 /* 866 * Intel Architectural LBR CPUID Enumeration 867 */ 868 unsigned int lbr_depth_mask:8; 869 unsigned int lbr_deep_c_reset:1; 870 unsigned int lbr_lip:1; 871 unsigned int lbr_cpl:1; 872 unsigned int lbr_filter:1; 873 unsigned int lbr_call_stack:1; 874 unsigned int lbr_mispred:1; 875 unsigned int lbr_timed_lbr:1; 876 unsigned int lbr_br_type:1; 877 878 void (*lbr_reset)(void); 879 void (*lbr_read)(struct cpu_hw_events *cpuc); 880 void (*lbr_save)(void *ctx); 881 void (*lbr_restore)(void *ctx); 882 883 /* 884 * Intel PT/LBR/BTS are exclusive 885 */ 886 atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 887 888 /* 889 * Intel perf metrics 890 */ 891 int num_topdown_events; 892 u64 (*update_topdown_event)(struct perf_event *event); 893 int (*set_topdown_event_period)(struct perf_event *event); 894 895 /* 896 * perf task context (i.e. struct perf_event_context::task_ctx_data) 897 * switch helper to bridge calls from perf/core to perf/x86. 898 * See struct pmu::swap_task_ctx() usage for examples; 899 */ 900 void (*swap_task_ctx)(struct perf_event_context *prev, 901 struct perf_event_context *next); 902 903 /* 904 * AMD bits 905 */ 906 unsigned int amd_nb_constraints : 1; 907 u64 perf_ctr_pair_en; 908 909 /* 910 * Extra registers for events 911 */ 912 struct extra_reg *extra_regs; 913 unsigned int flags; 914 915 /* 916 * Intel host/guest support (KVM) 917 */ 918 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr, void *data); 919 920 /* 921 * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 922 */ 923 int (*check_period) (struct perf_event *event, u64 period); 924 925 int (*aux_output_match) (struct perf_event *event); 926 927 int (*filter_match)(struct perf_event *event); 928 /* 929 * Hybrid support 930 * 931 * Most PMU capabilities are the same among different hybrid PMUs. 932 * The global x86_pmu saves the architecture capabilities, which 933 * are available for all PMUs. The hybrid_pmu only includes the 934 * unique capabilities. 935 */ 936 int num_hybrid_pmus; 937 struct x86_hybrid_pmu *hybrid_pmu; 938 u8 (*get_hybrid_cpu_type) (void); 939 }; 940 941 struct x86_perf_task_context_opt { 942 int lbr_callstack_users; 943 int lbr_stack_state; 944 int log_id; 945 }; 946 947 struct x86_perf_task_context { 948 u64 lbr_sel; 949 int tos; 950 int valid_lbrs; 951 struct x86_perf_task_context_opt opt; 952 struct lbr_entry lbr[MAX_LBR_ENTRIES]; 953 }; 954 955 struct x86_perf_task_context_arch_lbr { 956 struct x86_perf_task_context_opt opt; 957 struct lbr_entry entries[]; 958 }; 959 960 /* 961 * Add padding to guarantee the 64-byte alignment of the state buffer. 962 * 963 * The structure is dynamically allocated. The size of the LBR state may vary 964 * based on the number of LBR registers. 965 * 966 * Do not put anything after the LBR state. 967 */ 968 struct x86_perf_task_context_arch_lbr_xsave { 969 struct x86_perf_task_context_opt opt; 970 971 union { 972 struct xregs_state xsave; 973 struct { 974 struct fxregs_state i387; 975 struct xstate_header header; 976 struct arch_lbr_state lbr; 977 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 978 }; 979 }; 980 981 #define x86_add_quirk(func_) \ 982 do { \ 983 static struct x86_pmu_quirk __quirk __initdata = { \ 984 .func = func_, \ 985 }; \ 986 __quirk.next = x86_pmu.quirks; \ 987 x86_pmu.quirks = &__quirk; \ 988 } while (0) 989 990 /* 991 * x86_pmu flags 992 */ 993 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 994 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 995 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 996 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 997 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 998 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 999 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 1000 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ 1001 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ 1002 1003 #define EVENT_VAR(_id) event_attr_##_id 1004 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 1005 1006 #define EVENT_ATTR(_name, _id) \ 1007 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 1008 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1009 .id = PERF_COUNT_HW_##_id, \ 1010 .event_str = NULL, \ 1011 }; 1012 1013 #define EVENT_ATTR_STR(_name, v, str) \ 1014 static struct perf_pmu_events_attr event_attr_##v = { \ 1015 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1016 .id = 0, \ 1017 .event_str = str, \ 1018 }; 1019 1020 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 1021 static struct perf_pmu_events_ht_attr event_attr_##v = { \ 1022 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 1023 .id = 0, \ 1024 .event_str_noht = noht, \ 1025 .event_str_ht = ht, \ 1026 } 1027 1028 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \ 1029 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \ 1030 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\ 1031 .id = 0, \ 1032 .event_str = str, \ 1033 .pmu_type = _pmu, \ 1034 } 1035 1036 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr) 1037 1038 #define FORMAT_ATTR_HYBRID(_name, _pmu) \ 1039 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\ 1040 .attr = __ATTR_RO(_name), \ 1041 .pmu_type = _pmu, \ 1042 } 1043 1044 struct pmu *x86_get_pmu(unsigned int cpu); 1045 extern struct x86_pmu x86_pmu __read_mostly; 1046 1047 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 1048 { 1049 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 1050 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 1051 1052 return &((struct x86_perf_task_context *)ctx)->opt; 1053 } 1054 1055 static inline bool x86_pmu_has_lbr_callstack(void) 1056 { 1057 return x86_pmu.lbr_sel_map && 1058 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 1059 } 1060 1061 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 1062 1063 int x86_perf_event_set_period(struct perf_event *event); 1064 1065 /* 1066 * Generalized hw caching related hw_event table, filled 1067 * in on a per model basis. A value of 0 means 1068 * 'not supported', -1 means 'hw_event makes no sense on 1069 * this CPU', any other value means the raw hw_event 1070 * ID. 1071 */ 1072 1073 #define C(x) PERF_COUNT_HW_CACHE_##x 1074 1075 extern u64 __read_mostly hw_cache_event_ids 1076 [PERF_COUNT_HW_CACHE_MAX] 1077 [PERF_COUNT_HW_CACHE_OP_MAX] 1078 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1079 extern u64 __read_mostly hw_cache_extra_regs 1080 [PERF_COUNT_HW_CACHE_MAX] 1081 [PERF_COUNT_HW_CACHE_OP_MAX] 1082 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1083 1084 u64 x86_perf_event_update(struct perf_event *event); 1085 1086 static inline unsigned int x86_pmu_config_addr(int index) 1087 { 1088 return x86_pmu.eventsel + (x86_pmu.addr_offset ? 1089 x86_pmu.addr_offset(index, true) : index); 1090 } 1091 1092 static inline unsigned int x86_pmu_event_addr(int index) 1093 { 1094 return x86_pmu.perfctr + (x86_pmu.addr_offset ? 1095 x86_pmu.addr_offset(index, false) : index); 1096 } 1097 1098 static inline int x86_pmu_rdpmc_index(int index) 1099 { 1100 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 1101 } 1102 1103 bool check_hw_exists(struct pmu *pmu, int num_counters, 1104 int num_counters_fixed); 1105 1106 int x86_add_exclusive(unsigned int what); 1107 1108 void x86_del_exclusive(unsigned int what); 1109 1110 int x86_reserve_hardware(void); 1111 1112 void x86_release_hardware(void); 1113 1114 int x86_pmu_max_precise(void); 1115 1116 void hw_perf_lbr_event_destroy(struct perf_event *event); 1117 1118 int x86_setup_perfctr(struct perf_event *event); 1119 1120 int x86_pmu_hw_config(struct perf_event *event); 1121 1122 void x86_pmu_disable_all(void); 1123 1124 static inline bool has_amd_brs(struct hw_perf_event *hwc) 1125 { 1126 return hwc->flags & PERF_X86_EVENT_AMD_BRS; 1127 } 1128 1129 static inline bool is_counter_pair(struct hw_perf_event *hwc) 1130 { 1131 return hwc->flags & PERF_X86_EVENT_PAIR; 1132 } 1133 1134 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 1135 u64 enable_mask) 1136 { 1137 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1138 1139 if (hwc->extra_reg.reg) 1140 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 1141 1142 /* 1143 * Add enabled Merge event on next counter 1144 * if large increment event being enabled on this counter 1145 */ 1146 if (is_counter_pair(hwc)) 1147 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 1148 1149 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 1150 } 1151 1152 void x86_pmu_enable_all(int added); 1153 1154 int perf_assign_events(struct event_constraint **constraints, int n, 1155 int wmin, int wmax, int gpmax, int *assign); 1156 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 1157 1158 void x86_pmu_stop(struct perf_event *event, int flags); 1159 1160 static inline void x86_pmu_disable_event(struct perf_event *event) 1161 { 1162 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1163 struct hw_perf_event *hwc = &event->hw; 1164 1165 wrmsrl(hwc->config_base, hwc->config & ~disable_mask); 1166 1167 if (is_counter_pair(hwc)) 1168 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 1169 } 1170 1171 void x86_pmu_enable_event(struct perf_event *event); 1172 1173 int x86_pmu_handle_irq(struct pt_regs *regs); 1174 1175 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed, 1176 u64 intel_ctrl); 1177 1178 void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu); 1179 1180 extern struct event_constraint emptyconstraint; 1181 1182 extern struct event_constraint unconstrained; 1183 1184 static inline bool kernel_ip(unsigned long ip) 1185 { 1186 #ifdef CONFIG_X86_32 1187 return ip > PAGE_OFFSET; 1188 #else 1189 return (long)ip < 0; 1190 #endif 1191 } 1192 1193 /* 1194 * Not all PMUs provide the right context information to place the reported IP 1195 * into full context. Specifically segment registers are typically not 1196 * supplied. 1197 * 1198 * Assuming the address is a linear address (it is for IBS), we fake the CS and 1199 * vm86 mode using the known zero-based code segment and 'fix up' the registers 1200 * to reflect this. 1201 * 1202 * Intel PEBS/LBR appear to typically provide the effective address, nothing 1203 * much we can do about that but pray and treat it like a linear address. 1204 */ 1205 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 1206 { 1207 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 1208 if (regs->flags & X86_VM_MASK) 1209 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 1210 regs->ip = ip; 1211 } 1212 1213 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 1214 ssize_t intel_event_sysfs_show(char *page, u64 config); 1215 1216 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1217 char *page); 1218 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1219 char *page); 1220 ssize_t events_hybrid_sysfs_show(struct device *dev, 1221 struct device_attribute *attr, 1222 char *page); 1223 1224 static inline bool fixed_counter_disabled(int i, struct pmu *pmu) 1225 { 1226 u64 intel_ctrl = hybrid(pmu, intel_ctrl); 1227 1228 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); 1229 } 1230 1231 #ifdef CONFIG_CPU_SUP_AMD 1232 1233 int amd_pmu_init(void); 1234 1235 #ifdef CONFIG_PERF_EVENTS_AMD_BRS 1236 int amd_brs_init(void); 1237 void amd_brs_disable(void); 1238 void amd_brs_enable(void); 1239 void amd_brs_enable_all(void); 1240 void amd_brs_disable_all(void); 1241 void amd_brs_drain(void); 1242 void amd_brs_lopwr_init(void); 1243 void amd_brs_disable_all(void); 1244 int amd_brs_setup_filter(struct perf_event *event); 1245 void amd_brs_reset(void); 1246 1247 static inline void amd_pmu_brs_add(struct perf_event *event) 1248 { 1249 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1250 1251 perf_sched_cb_inc(event->ctx->pmu); 1252 cpuc->lbr_users++; 1253 /* 1254 * No need to reset BRS because it is reset 1255 * on brs_enable() and it is saturating 1256 */ 1257 } 1258 1259 static inline void amd_pmu_brs_del(struct perf_event *event) 1260 { 1261 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1262 1263 cpuc->lbr_users--; 1264 WARN_ON_ONCE(cpuc->lbr_users < 0); 1265 1266 perf_sched_cb_dec(event->ctx->pmu); 1267 } 1268 1269 void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in); 1270 #else 1271 static inline int amd_brs_init(void) 1272 { 1273 return 0; 1274 } 1275 static inline void amd_brs_disable(void) {} 1276 static inline void amd_brs_enable(void) {} 1277 static inline void amd_brs_drain(void) {} 1278 static inline void amd_brs_lopwr_init(void) {} 1279 static inline void amd_brs_disable_all(void) {} 1280 static inline int amd_brs_setup_filter(struct perf_event *event) 1281 { 1282 return 0; 1283 } 1284 static inline void amd_brs_reset(void) {} 1285 1286 static inline void amd_pmu_brs_add(struct perf_event *event) 1287 { 1288 } 1289 1290 static inline void amd_pmu_brs_del(struct perf_event *event) 1291 { 1292 } 1293 1294 static inline void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in) 1295 { 1296 } 1297 1298 static inline void amd_brs_enable_all(void) 1299 { 1300 } 1301 1302 #endif 1303 1304 #else /* CONFIG_CPU_SUP_AMD */ 1305 1306 static inline int amd_pmu_init(void) 1307 { 1308 return 0; 1309 } 1310 1311 static inline int amd_brs_init(void) 1312 { 1313 return -EOPNOTSUPP; 1314 } 1315 1316 static inline void amd_brs_drain(void) 1317 { 1318 } 1319 1320 static inline void amd_brs_enable_all(void) 1321 { 1322 } 1323 1324 static inline void amd_brs_disable_all(void) 1325 { 1326 } 1327 #endif /* CONFIG_CPU_SUP_AMD */ 1328 1329 static inline int is_pebs_pt(struct perf_event *event) 1330 { 1331 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 1332 } 1333 1334 #ifdef CONFIG_CPU_SUP_INTEL 1335 1336 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 1337 { 1338 struct hw_perf_event *hwc = &event->hw; 1339 unsigned int hw_event, bts_event; 1340 1341 if (event->attr.freq) 1342 return false; 1343 1344 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 1345 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 1346 1347 return hw_event == bts_event && period == 1; 1348 } 1349 1350 static inline bool intel_pmu_has_bts(struct perf_event *event) 1351 { 1352 struct hw_perf_event *hwc = &event->hw; 1353 1354 return intel_pmu_has_bts_period(event, hwc->sample_period); 1355 } 1356 1357 static __always_inline void __intel_pmu_pebs_disable_all(void) 1358 { 1359 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 1360 } 1361 1362 static __always_inline void __intel_pmu_arch_lbr_disable(void) 1363 { 1364 wrmsrl(MSR_ARCH_LBR_CTL, 0); 1365 } 1366 1367 static __always_inline void __intel_pmu_lbr_disable(void) 1368 { 1369 u64 debugctl; 1370 1371 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1372 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1373 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1374 } 1375 1376 int intel_pmu_save_and_restart(struct perf_event *event); 1377 1378 struct event_constraint * 1379 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 1380 struct perf_event *event); 1381 1382 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1383 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 1384 1385 int intel_pmu_init(void); 1386 1387 void init_debug_store_on_cpu(int cpu); 1388 1389 void fini_debug_store_on_cpu(int cpu); 1390 1391 void release_ds_buffers(void); 1392 1393 void reserve_ds_buffers(void); 1394 1395 void release_lbr_buffers(void); 1396 1397 void reserve_lbr_buffers(void); 1398 1399 extern struct event_constraint bts_constraint; 1400 extern struct event_constraint vlbr_constraint; 1401 1402 void intel_pmu_enable_bts(u64 config); 1403 1404 void intel_pmu_disable_bts(void); 1405 1406 int intel_pmu_drain_bts_buffer(void); 1407 1408 u64 adl_latency_data_small(struct perf_event *event, u64 status); 1409 1410 extern struct event_constraint intel_core2_pebs_event_constraints[]; 1411 1412 extern struct event_constraint intel_atom_pebs_event_constraints[]; 1413 1414 extern struct event_constraint intel_slm_pebs_event_constraints[]; 1415 1416 extern struct event_constraint intel_glm_pebs_event_constraints[]; 1417 1418 extern struct event_constraint intel_glp_pebs_event_constraints[]; 1419 1420 extern struct event_constraint intel_grt_pebs_event_constraints[]; 1421 1422 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1423 1424 extern struct event_constraint intel_westmere_pebs_event_constraints[]; 1425 1426 extern struct event_constraint intel_snb_pebs_event_constraints[]; 1427 1428 extern struct event_constraint intel_ivb_pebs_event_constraints[]; 1429 1430 extern struct event_constraint intel_hsw_pebs_event_constraints[]; 1431 1432 extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1433 1434 extern struct event_constraint intel_skl_pebs_event_constraints[]; 1435 1436 extern struct event_constraint intel_icl_pebs_event_constraints[]; 1437 1438 extern struct event_constraint intel_spr_pebs_event_constraints[]; 1439 1440 struct event_constraint *intel_pebs_constraints(struct perf_event *event); 1441 1442 void intel_pmu_pebs_add(struct perf_event *event); 1443 1444 void intel_pmu_pebs_del(struct perf_event *event); 1445 1446 void intel_pmu_pebs_enable(struct perf_event *event); 1447 1448 void intel_pmu_pebs_disable(struct perf_event *event); 1449 1450 void intel_pmu_pebs_enable_all(void); 1451 1452 void intel_pmu_pebs_disable_all(void); 1453 1454 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); 1455 1456 void intel_pmu_auto_reload_read(struct perf_event *event); 1457 1458 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1459 1460 void intel_ds_init(void); 1461 1462 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 1463 struct perf_event_context *next); 1464 1465 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); 1466 1467 u64 lbr_from_signext_quirk_wr(u64 val); 1468 1469 void intel_pmu_lbr_reset(void); 1470 1471 void intel_pmu_lbr_reset_32(void); 1472 1473 void intel_pmu_lbr_reset_64(void); 1474 1475 void intel_pmu_lbr_add(struct perf_event *event); 1476 1477 void intel_pmu_lbr_del(struct perf_event *event); 1478 1479 void intel_pmu_lbr_enable_all(bool pmi); 1480 1481 void intel_pmu_lbr_disable_all(void); 1482 1483 void intel_pmu_lbr_read(void); 1484 1485 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1486 1487 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1488 1489 void intel_pmu_lbr_save(void *ctx); 1490 1491 void intel_pmu_lbr_restore(void *ctx); 1492 1493 void intel_pmu_lbr_init_core(void); 1494 1495 void intel_pmu_lbr_init_nhm(void); 1496 1497 void intel_pmu_lbr_init_atom(void); 1498 1499 void intel_pmu_lbr_init_slm(void); 1500 1501 void intel_pmu_lbr_init_snb(void); 1502 1503 void intel_pmu_lbr_init_hsw(void); 1504 1505 void intel_pmu_lbr_init_skl(void); 1506 1507 void intel_pmu_lbr_init_knl(void); 1508 1509 void intel_pmu_lbr_init(void); 1510 1511 void intel_pmu_arch_lbr_init(void); 1512 1513 void intel_pmu_pebs_data_source_nhm(void); 1514 1515 void intel_pmu_pebs_data_source_skl(bool pmem); 1516 1517 void intel_pmu_pebs_data_source_adl(void); 1518 1519 int intel_pmu_setup_lbr_filter(struct perf_event *event); 1520 1521 void intel_pt_interrupt(void); 1522 1523 int intel_bts_interrupt(void); 1524 1525 void intel_bts_enable_local(void); 1526 1527 void intel_bts_disable_local(void); 1528 1529 int p4_pmu_init(void); 1530 1531 int p6_pmu_init(void); 1532 1533 int knc_pmu_init(void); 1534 1535 static inline int is_ht_workaround_enabled(void) 1536 { 1537 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 1538 } 1539 1540 #else /* CONFIG_CPU_SUP_INTEL */ 1541 1542 static inline void reserve_ds_buffers(void) 1543 { 1544 } 1545 1546 static inline void release_ds_buffers(void) 1547 { 1548 } 1549 1550 static inline void release_lbr_buffers(void) 1551 { 1552 } 1553 1554 static inline void reserve_lbr_buffers(void) 1555 { 1556 } 1557 1558 static inline int intel_pmu_init(void) 1559 { 1560 return 0; 1561 } 1562 1563 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 1564 { 1565 return 0; 1566 } 1567 1568 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1569 { 1570 } 1571 1572 static inline int is_ht_workaround_enabled(void) 1573 { 1574 return 0; 1575 } 1576 #endif /* CONFIG_CPU_SUP_INTEL */ 1577 1578 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 1579 int zhaoxin_pmu_init(void); 1580 #else 1581 static inline int zhaoxin_pmu_init(void) 1582 { 1583 return 0; 1584 } 1585 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1586