1 /* 2 * Performance events x86 architecture header 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 17 #include <asm/intel_ds.h> 18 #include <asm/cpu.h> 19 20 /* To enable MSR tracing please use the generic trace points. */ 21 22 /* 23 * | NHM/WSM | SNB | 24 * register ------------------------------- 25 * | HT | no HT | HT | no HT | 26 *----------------------------------------- 27 * offcore | core | core | cpu | core | 28 * lbr_sel | core | core | cpu | core | 29 * ld_lat | cpu | core | cpu | core | 30 *----------------------------------------- 31 * 32 * Given that there is a small number of shared regs, 33 * we can pre-allocate their slot in the per-cpu 34 * per-core reg tables. 35 */ 36 enum extra_reg_type { 37 EXTRA_REG_NONE = -1, /* not used */ 38 39 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 40 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 41 EXTRA_REG_LBR = 2, /* lbr_select */ 42 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 43 EXTRA_REG_FE = 4, /* fe_* */ 44 45 EXTRA_REG_MAX /* number of entries needed */ 46 }; 47 48 struct event_constraint { 49 union { 50 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 51 u64 idxmsk64; 52 }; 53 u64 code; 54 u64 cmask; 55 int weight; 56 int overlap; 57 int flags; 58 unsigned int size; 59 }; 60 61 static inline bool constraint_match(struct event_constraint *c, u64 ecode) 62 { 63 return ((ecode & c->cmask) - c->code) <= (u64)c->size; 64 } 65 66 /* 67 * struct hw_perf_event.flags flags 68 */ 69 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ 70 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ 71 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ 72 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */ 73 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */ 74 #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */ 75 #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */ 76 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */ 77 #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */ 78 #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */ 79 #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */ 80 #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */ 81 #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */ 82 #define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */ 83 #define PERF_X86_EVENT_TOPDOWN 0x4000 /* Count Topdown slots/metrics events */ 84 #define PERF_X86_EVENT_PEBS_STLAT 0x8000 /* st+stlat data address sampling */ 85 86 static inline bool is_topdown_count(struct perf_event *event) 87 { 88 return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 89 } 90 91 static inline bool is_metric_event(struct perf_event *event) 92 { 93 u64 config = event->attr.config; 94 95 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 96 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 97 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 98 } 99 100 static inline bool is_slots_event(struct perf_event *event) 101 { 102 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 103 } 104 105 static inline bool is_topdown_event(struct perf_event *event) 106 { 107 return is_metric_event(event) || is_slots_event(event); 108 } 109 110 struct amd_nb { 111 int nb_id; /* NorthBridge id */ 112 int refcnt; /* reference count */ 113 struct perf_event *owners[X86_PMC_IDX_MAX]; 114 struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 115 }; 116 117 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 118 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 119 #define PEBS_OUTPUT_OFFSET 61 120 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 121 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 122 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 123 124 /* 125 * Flags PEBS can handle without an PMI. 126 * 127 * TID can only be handled by flushing at context switch. 128 * REGS_USER can be handled for events limited to ring 3. 129 * 130 */ 131 #define LARGE_PEBS_FLAGS \ 132 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 133 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 134 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 135 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 136 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 137 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE) 138 139 #define PEBS_GP_REGS \ 140 ((1ULL << PERF_REG_X86_AX) | \ 141 (1ULL << PERF_REG_X86_BX) | \ 142 (1ULL << PERF_REG_X86_CX) | \ 143 (1ULL << PERF_REG_X86_DX) | \ 144 (1ULL << PERF_REG_X86_DI) | \ 145 (1ULL << PERF_REG_X86_SI) | \ 146 (1ULL << PERF_REG_X86_SP) | \ 147 (1ULL << PERF_REG_X86_BP) | \ 148 (1ULL << PERF_REG_X86_IP) | \ 149 (1ULL << PERF_REG_X86_FLAGS) | \ 150 (1ULL << PERF_REG_X86_R8) | \ 151 (1ULL << PERF_REG_X86_R9) | \ 152 (1ULL << PERF_REG_X86_R10) | \ 153 (1ULL << PERF_REG_X86_R11) | \ 154 (1ULL << PERF_REG_X86_R12) | \ 155 (1ULL << PERF_REG_X86_R13) | \ 156 (1ULL << PERF_REG_X86_R14) | \ 157 (1ULL << PERF_REG_X86_R15)) 158 159 /* 160 * Per register state. 161 */ 162 struct er_account { 163 raw_spinlock_t lock; /* per-core: protect structure */ 164 u64 config; /* extra MSR config */ 165 u64 reg; /* extra MSR number */ 166 atomic_t ref; /* reference count */ 167 }; 168 169 /* 170 * Per core/cpu state 171 * 172 * Used to coordinate shared registers between HT threads or 173 * among events on a single PMU. 174 */ 175 struct intel_shared_regs { 176 struct er_account regs[EXTRA_REG_MAX]; 177 int refcnt; /* per-core: #HT threads */ 178 unsigned core_id; /* per-core: core id */ 179 }; 180 181 enum intel_excl_state_type { 182 INTEL_EXCL_UNUSED = 0, /* counter is unused */ 183 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 184 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 185 }; 186 187 struct intel_excl_states { 188 enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 189 bool sched_started; /* true if scheduling has started */ 190 }; 191 192 struct intel_excl_cntrs { 193 raw_spinlock_t lock; 194 195 struct intel_excl_states states[2]; 196 197 union { 198 u16 has_exclusive[2]; 199 u32 exclusive_present; 200 }; 201 202 int refcnt; /* per-core: #HT threads */ 203 unsigned core_id; /* per-core: core id */ 204 }; 205 206 struct x86_perf_task_context; 207 #define MAX_LBR_ENTRIES 32 208 209 enum { 210 LBR_FORMAT_32 = 0x00, 211 LBR_FORMAT_LIP = 0x01, 212 LBR_FORMAT_EIP = 0x02, 213 LBR_FORMAT_EIP_FLAGS = 0x03, 214 LBR_FORMAT_EIP_FLAGS2 = 0x04, 215 LBR_FORMAT_INFO = 0x05, 216 LBR_FORMAT_TIME = 0x06, 217 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME, 218 }; 219 220 enum { 221 X86_PERF_KFREE_SHARED = 0, 222 X86_PERF_KFREE_EXCL = 1, 223 X86_PERF_KFREE_MAX 224 }; 225 226 struct cpu_hw_events { 227 /* 228 * Generic x86 PMC bits 229 */ 230 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 231 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 232 int enabled; 233 234 int n_events; /* the # of events in the below arrays */ 235 int n_added; /* the # last events in the below arrays; 236 they've never been enabled yet */ 237 int n_txn; /* the # last events in the below arrays; 238 added in the current transaction */ 239 int n_txn_pair; 240 int n_txn_metric; 241 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 242 u64 tags[X86_PMC_IDX_MAX]; 243 244 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 245 struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 246 247 int n_excl; /* the number of exclusive events */ 248 249 unsigned int txn_flags; 250 int is_fake; 251 252 /* 253 * Intel DebugStore bits 254 */ 255 struct debug_store *ds; 256 void *ds_pebs_vaddr; 257 void *ds_bts_vaddr; 258 u64 pebs_enabled; 259 int n_pebs; 260 int n_large_pebs; 261 int n_pebs_via_pt; 262 int pebs_output; 263 264 /* Current super set of events hardware configuration */ 265 u64 pebs_data_cfg; 266 u64 active_pebs_data_cfg; 267 int pebs_record_size; 268 269 /* 270 * Intel LBR bits 271 */ 272 int lbr_users; 273 int lbr_pebs_users; 274 struct perf_branch_stack lbr_stack; 275 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 276 union { 277 struct er_account *lbr_sel; 278 struct er_account *lbr_ctl; 279 }; 280 u64 br_sel; 281 void *last_task_ctx; 282 int last_log_id; 283 int lbr_select; 284 void *lbr_xsave; 285 286 /* 287 * Intel host/guest exclude bits 288 */ 289 u64 intel_ctrl_guest_mask; 290 u64 intel_ctrl_host_mask; 291 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 292 293 /* 294 * Intel checkpoint mask 295 */ 296 u64 intel_cp_status; 297 298 /* 299 * manage shared (per-core, per-cpu) registers 300 * used on Intel NHM/WSM/SNB 301 */ 302 struct intel_shared_regs *shared_regs; 303 /* 304 * manage exclusive counter access between hyperthread 305 */ 306 struct event_constraint *constraint_list; /* in enable order */ 307 struct intel_excl_cntrs *excl_cntrs; 308 int excl_thread_id; /* 0 or 1 */ 309 310 /* 311 * SKL TSX_FORCE_ABORT shadow 312 */ 313 u64 tfa_shadow; 314 315 /* 316 * Perf Metrics 317 */ 318 /* number of accepted metrics events */ 319 int n_metric; 320 321 /* 322 * AMD specific bits 323 */ 324 struct amd_nb *amd_nb; 325 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 326 u64 perf_ctr_virt_mask; 327 int n_pair; /* Large increment events */ 328 329 void *kfree_on_online[X86_PERF_KFREE_MAX]; 330 331 struct pmu *pmu; 332 }; 333 334 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 335 { .idxmsk64 = (n) }, \ 336 .code = (c), \ 337 .size = (e) - (c), \ 338 .cmask = (m), \ 339 .weight = (w), \ 340 .overlap = (o), \ 341 .flags = f, \ 342 } 343 344 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 345 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 346 347 #define EVENT_CONSTRAINT(c, n, m) \ 348 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 349 350 /* 351 * The constraint_match() function only works for 'simple' event codes 352 * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 353 */ 354 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 355 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 356 357 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 358 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 359 0, PERF_X86_EVENT_EXCL) 360 361 /* 362 * The overlap flag marks event constraints with overlapping counter 363 * masks. This is the case if the counter mask of such an event is not 364 * a subset of any other counter mask of a constraint with an equal or 365 * higher weight, e.g.: 366 * 367 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 368 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 369 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 370 * 371 * The event scheduler may not select the correct counter in the first 372 * cycle because it needs to know which subsequent events will be 373 * scheduled. It may fail to schedule the events then. So we set the 374 * overlap flag for such constraints to give the scheduler a hint which 375 * events to select for counter rescheduling. 376 * 377 * Care must be taken as the rescheduling algorithm is O(n!) which 378 * will increase scheduling cycles for an over-committed system 379 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 380 * and its counter masks must be kept at a minimum. 381 */ 382 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 383 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 384 385 /* 386 * Constraint on the Event code. 387 */ 388 #define INTEL_EVENT_CONSTRAINT(c, n) \ 389 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 390 391 /* 392 * Constraint on a range of Event codes 393 */ 394 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 395 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 396 397 /* 398 * Constraint on the Event code + UMask + fixed-mask 399 * 400 * filter mask to validate fixed counter events. 401 * the following filters disqualify for fixed counters: 402 * - inv 403 * - edge 404 * - cnt-mask 405 * - in_tx 406 * - in_tx_checkpointed 407 * The other filters are supported by fixed counters. 408 * The any-thread option is supported starting with v3. 409 */ 410 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 411 #define FIXED_EVENT_CONSTRAINT(c, n) \ 412 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 413 414 /* 415 * The special metric counters do not actually exist. They are calculated from 416 * the combination of the FxCtr3 + MSR_PERF_METRICS. 417 * 418 * The special metric counters are mapped to a dummy offset for the scheduler. 419 * The sharing between multiple users of the same metric without multiplexing 420 * is not allowed, even though the hardware supports that in principle. 421 */ 422 423 #define METRIC_EVENT_CONSTRAINT(c, n) \ 424 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 425 INTEL_ARCH_EVENT_MASK) 426 427 /* 428 * Constraint on the Event code + UMask 429 */ 430 #define INTEL_UEVENT_CONSTRAINT(c, n) \ 431 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 432 433 /* Constraint on specific umask bit only + event */ 434 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 435 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 436 437 /* Like UEVENT_CONSTRAINT, but match flags too */ 438 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 439 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 440 441 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 442 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 443 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 444 445 #define INTEL_PLD_CONSTRAINT(c, n) \ 446 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 447 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 448 449 #define INTEL_PSD_CONSTRAINT(c, n) \ 450 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 451 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT) 452 453 #define INTEL_PST_CONSTRAINT(c, n) \ 454 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 455 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 456 457 /* Event constraint, but match on all event flags too. */ 458 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 459 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 460 461 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 462 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 463 464 /* Check only flags, but allow all event/umask */ 465 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 466 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 467 468 /* Check flags and event code, and set the HSW store flag */ 469 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 470 __EVENT_CONSTRAINT(code, n, \ 471 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 472 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 473 474 /* Check flags and event code, and set the HSW load flag */ 475 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 476 __EVENT_CONSTRAINT(code, n, \ 477 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 478 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 479 480 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 481 __EVENT_CONSTRAINT_RANGE(code, end, n, \ 482 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 483 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 484 485 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 486 __EVENT_CONSTRAINT(code, n, \ 487 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 488 HWEIGHT(n), 0, \ 489 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 490 491 /* Check flags and event code/umask, and set the HSW store flag */ 492 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 493 __EVENT_CONSTRAINT(code, n, \ 494 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 495 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 496 497 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 498 __EVENT_CONSTRAINT(code, n, \ 499 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 500 HWEIGHT(n), 0, \ 501 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 502 503 /* Check flags and event code/umask, and set the HSW load flag */ 504 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 505 __EVENT_CONSTRAINT(code, n, \ 506 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 507 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 508 509 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 510 __EVENT_CONSTRAINT(code, n, \ 511 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 512 HWEIGHT(n), 0, \ 513 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 514 515 /* Check flags and event code/umask, and set the HSW N/A flag */ 516 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 517 __EVENT_CONSTRAINT(code, n, \ 518 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 519 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 520 521 522 /* 523 * We define the end marker as having a weight of -1 524 * to enable blacklisting of events using a counter bitmask 525 * of zero and thus a weight of zero. 526 * The end marker has a weight that cannot possibly be 527 * obtained from counting the bits in the bitmask. 528 */ 529 #define EVENT_CONSTRAINT_END { .weight = -1 } 530 531 /* 532 * Check for end marker with weight == -1 533 */ 534 #define for_each_event_constraint(e, c) \ 535 for ((e) = (c); (e)->weight != -1; (e)++) 536 537 /* 538 * Extra registers for specific events. 539 * 540 * Some events need large masks and require external MSRs. 541 * Those extra MSRs end up being shared for all events on 542 * a PMU and sometimes between PMU of sibling HT threads. 543 * In either case, the kernel needs to handle conflicting 544 * accesses to those extra, shared, regs. The data structure 545 * to manage those registers is stored in cpu_hw_event. 546 */ 547 struct extra_reg { 548 unsigned int event; 549 unsigned int msr; 550 u64 config_mask; 551 u64 valid_mask; 552 int idx; /* per_xxx->regs[] reg index */ 553 bool extra_msr_access; 554 }; 555 556 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 557 .event = (e), \ 558 .msr = (ms), \ 559 .config_mask = (m), \ 560 .valid_mask = (vm), \ 561 .idx = EXTRA_REG_##i, \ 562 .extra_msr_access = true, \ 563 } 564 565 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 566 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 567 568 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 569 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 570 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 571 572 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 573 INTEL_UEVENT_EXTRA_REG(c, \ 574 MSR_PEBS_LD_LAT_THRESHOLD, \ 575 0xffff, \ 576 LDLAT) 577 578 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 579 580 union perf_capabilities { 581 struct { 582 u64 lbr_format:6; 583 u64 pebs_trap:1; 584 u64 pebs_arch_reg:1; 585 u64 pebs_format:4; 586 u64 smm_freeze:1; 587 /* 588 * PMU supports separate counter range for writing 589 * values > 32bit. 590 */ 591 u64 full_width_write:1; 592 u64 pebs_baseline:1; 593 u64 perf_metrics:1; 594 u64 pebs_output_pt_available:1; 595 u64 anythread_deprecated:1; 596 }; 597 u64 capabilities; 598 }; 599 600 struct x86_pmu_quirk { 601 struct x86_pmu_quirk *next; 602 void (*func)(void); 603 }; 604 605 union x86_pmu_config { 606 struct { 607 u64 event:8, 608 umask:8, 609 usr:1, 610 os:1, 611 edge:1, 612 pc:1, 613 interrupt:1, 614 __reserved1:1, 615 en:1, 616 inv:1, 617 cmask:8, 618 event2:4, 619 __reserved2:4, 620 go:1, 621 ho:1; 622 } bits; 623 u64 value; 624 }; 625 626 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 627 628 enum { 629 x86_lbr_exclusive_lbr, 630 x86_lbr_exclusive_bts, 631 x86_lbr_exclusive_pt, 632 x86_lbr_exclusive_max, 633 }; 634 635 struct x86_hybrid_pmu { 636 struct pmu pmu; 637 const char *name; 638 u8 cpu_type; 639 cpumask_t supported_cpus; 640 union perf_capabilities intel_cap; 641 u64 intel_ctrl; 642 int max_pebs_events; 643 int num_counters; 644 int num_counters_fixed; 645 struct event_constraint unconstrained; 646 647 u64 hw_cache_event_ids 648 [PERF_COUNT_HW_CACHE_MAX] 649 [PERF_COUNT_HW_CACHE_OP_MAX] 650 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 651 u64 hw_cache_extra_regs 652 [PERF_COUNT_HW_CACHE_MAX] 653 [PERF_COUNT_HW_CACHE_OP_MAX] 654 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 655 struct event_constraint *event_constraints; 656 struct event_constraint *pebs_constraints; 657 struct extra_reg *extra_regs; 658 }; 659 660 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) 661 { 662 return container_of(pmu, struct x86_hybrid_pmu, pmu); 663 } 664 665 extern struct static_key_false perf_is_hybrid; 666 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid) 667 668 #define hybrid(_pmu, _field) \ 669 (*({ \ 670 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \ 671 \ 672 if (is_hybrid() && (_pmu)) \ 673 __Fp = &hybrid_pmu(_pmu)->_field; \ 674 \ 675 __Fp; \ 676 })) 677 678 #define hybrid_var(_pmu, _var) \ 679 (*({ \ 680 typeof(&_var) __Fp = &_var; \ 681 \ 682 if (is_hybrid() && (_pmu)) \ 683 __Fp = &hybrid_pmu(_pmu)->_var; \ 684 \ 685 __Fp; \ 686 })) 687 688 enum hybrid_pmu_type { 689 hybrid_big = 0x40, 690 hybrid_small = 0x20, 691 692 hybrid_big_small = hybrid_big | hybrid_small, 693 }; 694 695 #define X86_HYBRID_PMU_ATOM_IDX 0 696 #define X86_HYBRID_PMU_CORE_IDX 1 697 698 #define X86_HYBRID_NUM_PMUS 2 699 700 /* 701 * struct x86_pmu - generic x86 pmu 702 */ 703 struct x86_pmu { 704 /* 705 * Generic x86 PMC bits 706 */ 707 const char *name; 708 int version; 709 int (*handle_irq)(struct pt_regs *); 710 void (*disable_all)(void); 711 void (*enable_all)(int added); 712 void (*enable)(struct perf_event *); 713 void (*disable)(struct perf_event *); 714 void (*add)(struct perf_event *); 715 void (*del)(struct perf_event *); 716 void (*read)(struct perf_event *event); 717 int (*hw_config)(struct perf_event *event); 718 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 719 unsigned eventsel; 720 unsigned perfctr; 721 int (*addr_offset)(int index, bool eventsel); 722 int (*rdpmc_index)(int index); 723 u64 (*event_map)(int); 724 int max_events; 725 int num_counters; 726 int num_counters_fixed; 727 int cntval_bits; 728 u64 cntval_mask; 729 union { 730 unsigned long events_maskl; 731 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 732 }; 733 int events_mask_len; 734 int apic; 735 u64 max_period; 736 struct event_constraint * 737 (*get_event_constraints)(struct cpu_hw_events *cpuc, 738 int idx, 739 struct perf_event *event); 740 741 void (*put_event_constraints)(struct cpu_hw_events *cpuc, 742 struct perf_event *event); 743 744 void (*start_scheduling)(struct cpu_hw_events *cpuc); 745 746 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 747 748 void (*stop_scheduling)(struct cpu_hw_events *cpuc); 749 750 struct event_constraint *event_constraints; 751 struct x86_pmu_quirk *quirks; 752 int perfctr_second_write; 753 u64 (*limit_period)(struct perf_event *event, u64 l); 754 755 /* PMI handler bits */ 756 unsigned int late_ack :1, 757 enabled_ack :1; 758 /* 759 * sysfs attrs 760 */ 761 int attr_rdpmc_broken; 762 int attr_rdpmc; 763 struct attribute **format_attrs; 764 765 ssize_t (*events_sysfs_show)(char *page, u64 config); 766 const struct attribute_group **attr_update; 767 768 unsigned long attr_freeze_on_smi; 769 770 /* 771 * CPU Hotplug hooks 772 */ 773 int (*cpu_prepare)(int cpu); 774 void (*cpu_starting)(int cpu); 775 void (*cpu_dying)(int cpu); 776 void (*cpu_dead)(int cpu); 777 778 void (*check_microcode)(void); 779 void (*sched_task)(struct perf_event_context *ctx, 780 bool sched_in); 781 782 /* 783 * Intel Arch Perfmon v2+ 784 */ 785 u64 intel_ctrl; 786 union perf_capabilities intel_cap; 787 788 /* 789 * Intel DebugStore bits 790 */ 791 unsigned int bts :1, 792 bts_active :1, 793 pebs :1, 794 pebs_active :1, 795 pebs_broken :1, 796 pebs_prec_dist :1, 797 pebs_no_tlb :1, 798 pebs_no_isolation :1, 799 pebs_block :1; 800 int pebs_record_size; 801 int pebs_buffer_size; 802 int max_pebs_events; 803 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 804 struct event_constraint *pebs_constraints; 805 void (*pebs_aliases)(struct perf_event *event); 806 unsigned long large_pebs_flags; 807 u64 rtm_abort_event; 808 809 /* 810 * Intel LBR 811 */ 812 unsigned int lbr_tos, lbr_from, lbr_to, 813 lbr_info, lbr_nr; /* LBR base regs and size */ 814 union { 815 u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 816 u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 817 }; 818 union { 819 const int *lbr_sel_map; /* lbr_select mappings */ 820 int *lbr_ctl_map; /* LBR_CTL mappings */ 821 }; 822 bool lbr_double_abort; /* duplicated lbr aborts */ 823 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 824 825 /* 826 * Intel Architectural LBR CPUID Enumeration 827 */ 828 unsigned int lbr_depth_mask:8; 829 unsigned int lbr_deep_c_reset:1; 830 unsigned int lbr_lip:1; 831 unsigned int lbr_cpl:1; 832 unsigned int lbr_filter:1; 833 unsigned int lbr_call_stack:1; 834 unsigned int lbr_mispred:1; 835 unsigned int lbr_timed_lbr:1; 836 unsigned int lbr_br_type:1; 837 838 void (*lbr_reset)(void); 839 void (*lbr_read)(struct cpu_hw_events *cpuc); 840 void (*lbr_save)(void *ctx); 841 void (*lbr_restore)(void *ctx); 842 843 /* 844 * Intel PT/LBR/BTS are exclusive 845 */ 846 atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 847 848 /* 849 * Intel perf metrics 850 */ 851 int num_topdown_events; 852 u64 (*update_topdown_event)(struct perf_event *event); 853 int (*set_topdown_event_period)(struct perf_event *event); 854 855 /* 856 * perf task context (i.e. struct perf_event_context::task_ctx_data) 857 * switch helper to bridge calls from perf/core to perf/x86. 858 * See struct pmu::swap_task_ctx() usage for examples; 859 */ 860 void (*swap_task_ctx)(struct perf_event_context *prev, 861 struct perf_event_context *next); 862 863 /* 864 * AMD bits 865 */ 866 unsigned int amd_nb_constraints : 1; 867 u64 perf_ctr_pair_en; 868 869 /* 870 * Extra registers for events 871 */ 872 struct extra_reg *extra_regs; 873 unsigned int flags; 874 875 /* 876 * Intel host/guest support (KVM) 877 */ 878 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); 879 880 /* 881 * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 882 */ 883 int (*check_period) (struct perf_event *event, u64 period); 884 885 int (*aux_output_match) (struct perf_event *event); 886 887 int (*filter_match)(struct perf_event *event); 888 /* 889 * Hybrid support 890 * 891 * Most PMU capabilities are the same among different hybrid PMUs. 892 * The global x86_pmu saves the architecture capabilities, which 893 * are available for all PMUs. The hybrid_pmu only includes the 894 * unique capabilities. 895 */ 896 int num_hybrid_pmus; 897 struct x86_hybrid_pmu *hybrid_pmu; 898 u8 (*get_hybrid_cpu_type) (void); 899 }; 900 901 struct x86_perf_task_context_opt { 902 int lbr_callstack_users; 903 int lbr_stack_state; 904 int log_id; 905 }; 906 907 struct x86_perf_task_context { 908 u64 lbr_sel; 909 int tos; 910 int valid_lbrs; 911 struct x86_perf_task_context_opt opt; 912 struct lbr_entry lbr[MAX_LBR_ENTRIES]; 913 }; 914 915 struct x86_perf_task_context_arch_lbr { 916 struct x86_perf_task_context_opt opt; 917 struct lbr_entry entries[]; 918 }; 919 920 /* 921 * Add padding to guarantee the 64-byte alignment of the state buffer. 922 * 923 * The structure is dynamically allocated. The size of the LBR state may vary 924 * based on the number of LBR registers. 925 * 926 * Do not put anything after the LBR state. 927 */ 928 struct x86_perf_task_context_arch_lbr_xsave { 929 struct x86_perf_task_context_opt opt; 930 931 union { 932 struct xregs_state xsave; 933 struct { 934 struct fxregs_state i387; 935 struct xstate_header header; 936 struct arch_lbr_state lbr; 937 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 938 }; 939 }; 940 941 #define x86_add_quirk(func_) \ 942 do { \ 943 static struct x86_pmu_quirk __quirk __initdata = { \ 944 .func = func_, \ 945 }; \ 946 __quirk.next = x86_pmu.quirks; \ 947 x86_pmu.quirks = &__quirk; \ 948 } while (0) 949 950 /* 951 * x86_pmu flags 952 */ 953 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 954 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 955 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 956 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 957 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 958 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 959 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 960 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ 961 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ 962 963 #define EVENT_VAR(_id) event_attr_##_id 964 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 965 966 #define EVENT_ATTR(_name, _id) \ 967 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 968 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 969 .id = PERF_COUNT_HW_##_id, \ 970 .event_str = NULL, \ 971 }; 972 973 #define EVENT_ATTR_STR(_name, v, str) \ 974 static struct perf_pmu_events_attr event_attr_##v = { \ 975 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 976 .id = 0, \ 977 .event_str = str, \ 978 }; 979 980 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 981 static struct perf_pmu_events_ht_attr event_attr_##v = { \ 982 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 983 .id = 0, \ 984 .event_str_noht = noht, \ 985 .event_str_ht = ht, \ 986 } 987 988 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \ 989 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \ 990 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\ 991 .id = 0, \ 992 .event_str = str, \ 993 .pmu_type = _pmu, \ 994 } 995 996 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr) 997 998 #define FORMAT_ATTR_HYBRID(_name, _pmu) \ 999 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\ 1000 .attr = __ATTR_RO(_name), \ 1001 .pmu_type = _pmu, \ 1002 } 1003 1004 struct pmu *x86_get_pmu(unsigned int cpu); 1005 extern struct x86_pmu x86_pmu __read_mostly; 1006 1007 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 1008 { 1009 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 1010 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 1011 1012 return &((struct x86_perf_task_context *)ctx)->opt; 1013 } 1014 1015 static inline bool x86_pmu_has_lbr_callstack(void) 1016 { 1017 return x86_pmu.lbr_sel_map && 1018 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 1019 } 1020 1021 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 1022 1023 int x86_perf_event_set_period(struct perf_event *event); 1024 1025 /* 1026 * Generalized hw caching related hw_event table, filled 1027 * in on a per model basis. A value of 0 means 1028 * 'not supported', -1 means 'hw_event makes no sense on 1029 * this CPU', any other value means the raw hw_event 1030 * ID. 1031 */ 1032 1033 #define C(x) PERF_COUNT_HW_CACHE_##x 1034 1035 extern u64 __read_mostly hw_cache_event_ids 1036 [PERF_COUNT_HW_CACHE_MAX] 1037 [PERF_COUNT_HW_CACHE_OP_MAX] 1038 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1039 extern u64 __read_mostly hw_cache_extra_regs 1040 [PERF_COUNT_HW_CACHE_MAX] 1041 [PERF_COUNT_HW_CACHE_OP_MAX] 1042 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1043 1044 u64 x86_perf_event_update(struct perf_event *event); 1045 1046 static inline unsigned int x86_pmu_config_addr(int index) 1047 { 1048 return x86_pmu.eventsel + (x86_pmu.addr_offset ? 1049 x86_pmu.addr_offset(index, true) : index); 1050 } 1051 1052 static inline unsigned int x86_pmu_event_addr(int index) 1053 { 1054 return x86_pmu.perfctr + (x86_pmu.addr_offset ? 1055 x86_pmu.addr_offset(index, false) : index); 1056 } 1057 1058 static inline int x86_pmu_rdpmc_index(int index) 1059 { 1060 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 1061 } 1062 1063 bool check_hw_exists(struct pmu *pmu, int num_counters, 1064 int num_counters_fixed); 1065 1066 int x86_add_exclusive(unsigned int what); 1067 1068 void x86_del_exclusive(unsigned int what); 1069 1070 int x86_reserve_hardware(void); 1071 1072 void x86_release_hardware(void); 1073 1074 int x86_pmu_max_precise(void); 1075 1076 void hw_perf_lbr_event_destroy(struct perf_event *event); 1077 1078 int x86_setup_perfctr(struct perf_event *event); 1079 1080 int x86_pmu_hw_config(struct perf_event *event); 1081 1082 void x86_pmu_disable_all(void); 1083 1084 static inline bool is_counter_pair(struct hw_perf_event *hwc) 1085 { 1086 return hwc->flags & PERF_X86_EVENT_PAIR; 1087 } 1088 1089 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 1090 u64 enable_mask) 1091 { 1092 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1093 1094 if (hwc->extra_reg.reg) 1095 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 1096 1097 /* 1098 * Add enabled Merge event on next counter 1099 * if large increment event being enabled on this counter 1100 */ 1101 if (is_counter_pair(hwc)) 1102 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 1103 1104 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 1105 } 1106 1107 void x86_pmu_enable_all(int added); 1108 1109 int perf_assign_events(struct event_constraint **constraints, int n, 1110 int wmin, int wmax, int gpmax, int *assign); 1111 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 1112 1113 void x86_pmu_stop(struct perf_event *event, int flags); 1114 1115 static inline void x86_pmu_disable_event(struct perf_event *event) 1116 { 1117 struct hw_perf_event *hwc = &event->hw; 1118 1119 wrmsrl(hwc->config_base, hwc->config); 1120 1121 if (is_counter_pair(hwc)) 1122 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 1123 } 1124 1125 void x86_pmu_enable_event(struct perf_event *event); 1126 1127 int x86_pmu_handle_irq(struct pt_regs *regs); 1128 1129 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed, 1130 u64 intel_ctrl); 1131 1132 void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu); 1133 1134 extern struct event_constraint emptyconstraint; 1135 1136 extern struct event_constraint unconstrained; 1137 1138 static inline bool kernel_ip(unsigned long ip) 1139 { 1140 #ifdef CONFIG_X86_32 1141 return ip > PAGE_OFFSET; 1142 #else 1143 return (long)ip < 0; 1144 #endif 1145 } 1146 1147 /* 1148 * Not all PMUs provide the right context information to place the reported IP 1149 * into full context. Specifically segment registers are typically not 1150 * supplied. 1151 * 1152 * Assuming the address is a linear address (it is for IBS), we fake the CS and 1153 * vm86 mode using the known zero-based code segment and 'fix up' the registers 1154 * to reflect this. 1155 * 1156 * Intel PEBS/LBR appear to typically provide the effective address, nothing 1157 * much we can do about that but pray and treat it like a linear address. 1158 */ 1159 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 1160 { 1161 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 1162 if (regs->flags & X86_VM_MASK) 1163 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 1164 regs->ip = ip; 1165 } 1166 1167 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 1168 ssize_t intel_event_sysfs_show(char *page, u64 config); 1169 1170 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1171 char *page); 1172 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1173 char *page); 1174 ssize_t events_hybrid_sysfs_show(struct device *dev, 1175 struct device_attribute *attr, 1176 char *page); 1177 1178 static inline bool fixed_counter_disabled(int i, struct pmu *pmu) 1179 { 1180 u64 intel_ctrl = hybrid(pmu, intel_ctrl); 1181 1182 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); 1183 } 1184 1185 #ifdef CONFIG_CPU_SUP_AMD 1186 1187 int amd_pmu_init(void); 1188 1189 #else /* CONFIG_CPU_SUP_AMD */ 1190 1191 static inline int amd_pmu_init(void) 1192 { 1193 return 0; 1194 } 1195 1196 #endif /* CONFIG_CPU_SUP_AMD */ 1197 1198 static inline int is_pebs_pt(struct perf_event *event) 1199 { 1200 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 1201 } 1202 1203 #ifdef CONFIG_CPU_SUP_INTEL 1204 1205 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 1206 { 1207 struct hw_perf_event *hwc = &event->hw; 1208 unsigned int hw_event, bts_event; 1209 1210 if (event->attr.freq) 1211 return false; 1212 1213 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 1214 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 1215 1216 return hw_event == bts_event && period == 1; 1217 } 1218 1219 static inline bool intel_pmu_has_bts(struct perf_event *event) 1220 { 1221 struct hw_perf_event *hwc = &event->hw; 1222 1223 return intel_pmu_has_bts_period(event, hwc->sample_period); 1224 } 1225 1226 int intel_pmu_save_and_restart(struct perf_event *event); 1227 1228 struct event_constraint * 1229 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 1230 struct perf_event *event); 1231 1232 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1233 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 1234 1235 int intel_pmu_init(void); 1236 1237 void init_debug_store_on_cpu(int cpu); 1238 1239 void fini_debug_store_on_cpu(int cpu); 1240 1241 void release_ds_buffers(void); 1242 1243 void reserve_ds_buffers(void); 1244 1245 void release_lbr_buffers(void); 1246 1247 extern struct event_constraint bts_constraint; 1248 extern struct event_constraint vlbr_constraint; 1249 1250 void intel_pmu_enable_bts(u64 config); 1251 1252 void intel_pmu_disable_bts(void); 1253 1254 int intel_pmu_drain_bts_buffer(void); 1255 1256 extern struct event_constraint intel_core2_pebs_event_constraints[]; 1257 1258 extern struct event_constraint intel_atom_pebs_event_constraints[]; 1259 1260 extern struct event_constraint intel_slm_pebs_event_constraints[]; 1261 1262 extern struct event_constraint intel_glm_pebs_event_constraints[]; 1263 1264 extern struct event_constraint intel_glp_pebs_event_constraints[]; 1265 1266 extern struct event_constraint intel_grt_pebs_event_constraints[]; 1267 1268 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1269 1270 extern struct event_constraint intel_westmere_pebs_event_constraints[]; 1271 1272 extern struct event_constraint intel_snb_pebs_event_constraints[]; 1273 1274 extern struct event_constraint intel_ivb_pebs_event_constraints[]; 1275 1276 extern struct event_constraint intel_hsw_pebs_event_constraints[]; 1277 1278 extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1279 1280 extern struct event_constraint intel_skl_pebs_event_constraints[]; 1281 1282 extern struct event_constraint intel_icl_pebs_event_constraints[]; 1283 1284 extern struct event_constraint intel_spr_pebs_event_constraints[]; 1285 1286 struct event_constraint *intel_pebs_constraints(struct perf_event *event); 1287 1288 void intel_pmu_pebs_add(struct perf_event *event); 1289 1290 void intel_pmu_pebs_del(struct perf_event *event); 1291 1292 void intel_pmu_pebs_enable(struct perf_event *event); 1293 1294 void intel_pmu_pebs_disable(struct perf_event *event); 1295 1296 void intel_pmu_pebs_enable_all(void); 1297 1298 void intel_pmu_pebs_disable_all(void); 1299 1300 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); 1301 1302 void intel_pmu_auto_reload_read(struct perf_event *event); 1303 1304 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1305 1306 void intel_ds_init(void); 1307 1308 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 1309 struct perf_event_context *next); 1310 1311 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); 1312 1313 u64 lbr_from_signext_quirk_wr(u64 val); 1314 1315 void intel_pmu_lbr_reset(void); 1316 1317 void intel_pmu_lbr_reset_32(void); 1318 1319 void intel_pmu_lbr_reset_64(void); 1320 1321 void intel_pmu_lbr_add(struct perf_event *event); 1322 1323 void intel_pmu_lbr_del(struct perf_event *event); 1324 1325 void intel_pmu_lbr_enable_all(bool pmi); 1326 1327 void intel_pmu_lbr_disable_all(void); 1328 1329 void intel_pmu_lbr_read(void); 1330 1331 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1332 1333 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1334 1335 void intel_pmu_lbr_save(void *ctx); 1336 1337 void intel_pmu_lbr_restore(void *ctx); 1338 1339 void intel_pmu_lbr_init_core(void); 1340 1341 void intel_pmu_lbr_init_nhm(void); 1342 1343 void intel_pmu_lbr_init_atom(void); 1344 1345 void intel_pmu_lbr_init_slm(void); 1346 1347 void intel_pmu_lbr_init_snb(void); 1348 1349 void intel_pmu_lbr_init_hsw(void); 1350 1351 void intel_pmu_lbr_init_skl(void); 1352 1353 void intel_pmu_lbr_init_knl(void); 1354 1355 void intel_pmu_arch_lbr_init(void); 1356 1357 void intel_pmu_pebs_data_source_nhm(void); 1358 1359 void intel_pmu_pebs_data_source_skl(bool pmem); 1360 1361 int intel_pmu_setup_lbr_filter(struct perf_event *event); 1362 1363 void intel_pt_interrupt(void); 1364 1365 int intel_bts_interrupt(void); 1366 1367 void intel_bts_enable_local(void); 1368 1369 void intel_bts_disable_local(void); 1370 1371 int p4_pmu_init(void); 1372 1373 int p6_pmu_init(void); 1374 1375 int knc_pmu_init(void); 1376 1377 static inline int is_ht_workaround_enabled(void) 1378 { 1379 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 1380 } 1381 1382 #else /* CONFIG_CPU_SUP_INTEL */ 1383 1384 static inline void reserve_ds_buffers(void) 1385 { 1386 } 1387 1388 static inline void release_ds_buffers(void) 1389 { 1390 } 1391 1392 static inline void release_lbr_buffers(void) 1393 { 1394 } 1395 1396 static inline int intel_pmu_init(void) 1397 { 1398 return 0; 1399 } 1400 1401 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 1402 { 1403 return 0; 1404 } 1405 1406 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1407 { 1408 } 1409 1410 static inline int is_ht_workaround_enabled(void) 1411 { 1412 return 0; 1413 } 1414 #endif /* CONFIG_CPU_SUP_INTEL */ 1415 1416 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 1417 int zhaoxin_pmu_init(void); 1418 #else 1419 static inline int zhaoxin_pmu_init(void) 1420 { 1421 return 0; 1422 } 1423 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1424