1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/perf_event.h> 3 #include <linux/sysfs.h> 4 #include <linux/nospec.h> 5 #include <asm/intel-family.h> 6 #include "probe.h" 7 8 enum perf_msr_id { 9 PERF_MSR_TSC = 0, 10 PERF_MSR_APERF = 1, 11 PERF_MSR_MPERF = 2, 12 PERF_MSR_PPERF = 3, 13 PERF_MSR_SMI = 4, 14 PERF_MSR_PTSC = 5, 15 PERF_MSR_IRPERF = 6, 16 PERF_MSR_THERM = 7, 17 PERF_MSR_EVENT_MAX, 18 }; 19 20 static bool test_aperfmperf(int idx, void *data) 21 { 22 return boot_cpu_has(X86_FEATURE_APERFMPERF); 23 } 24 25 static bool test_ptsc(int idx, void *data) 26 { 27 return boot_cpu_has(X86_FEATURE_PTSC); 28 } 29 30 static bool test_irperf(int idx, void *data) 31 { 32 return boot_cpu_has(X86_FEATURE_IRPERF); 33 } 34 35 static bool test_therm_status(int idx, void *data) 36 { 37 return boot_cpu_has(X86_FEATURE_DTHERM); 38 } 39 40 static bool test_intel(int idx, void *data) 41 { 42 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || 43 boot_cpu_data.x86 != 6) 44 return false; 45 46 switch (boot_cpu_data.x86_model) { 47 case INTEL_FAM6_NEHALEM: 48 case INTEL_FAM6_NEHALEM_G: 49 case INTEL_FAM6_NEHALEM_EP: 50 case INTEL_FAM6_NEHALEM_EX: 51 52 case INTEL_FAM6_WESTMERE: 53 case INTEL_FAM6_WESTMERE_EP: 54 case INTEL_FAM6_WESTMERE_EX: 55 56 case INTEL_FAM6_SANDYBRIDGE: 57 case INTEL_FAM6_SANDYBRIDGE_X: 58 59 case INTEL_FAM6_IVYBRIDGE: 60 case INTEL_FAM6_IVYBRIDGE_X: 61 62 case INTEL_FAM6_HASWELL: 63 case INTEL_FAM6_HASWELL_X: 64 case INTEL_FAM6_HASWELL_L: 65 case INTEL_FAM6_HASWELL_G: 66 67 case INTEL_FAM6_BROADWELL: 68 case INTEL_FAM6_BROADWELL_D: 69 case INTEL_FAM6_BROADWELL_G: 70 case INTEL_FAM6_BROADWELL_X: 71 72 case INTEL_FAM6_ATOM_SILVERMONT: 73 case INTEL_FAM6_ATOM_SILVERMONT_D: 74 case INTEL_FAM6_ATOM_AIRMONT: 75 76 case INTEL_FAM6_ATOM_GOLDMONT: 77 case INTEL_FAM6_ATOM_GOLDMONT_D: 78 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 79 case INTEL_FAM6_ATOM_TREMONT_D: 80 case INTEL_FAM6_ATOM_TREMONT: 81 case INTEL_FAM6_ATOM_TREMONT_L: 82 83 case INTEL_FAM6_XEON_PHI_KNL: 84 case INTEL_FAM6_XEON_PHI_KNM: 85 if (idx == PERF_MSR_SMI) 86 return true; 87 break; 88 89 case INTEL_FAM6_SKYLAKE_L: 90 case INTEL_FAM6_SKYLAKE: 91 case INTEL_FAM6_SKYLAKE_X: 92 case INTEL_FAM6_KABYLAKE_L: 93 case INTEL_FAM6_KABYLAKE: 94 case INTEL_FAM6_COMETLAKE_L: 95 case INTEL_FAM6_COMETLAKE: 96 case INTEL_FAM6_ICELAKE_L: 97 case INTEL_FAM6_ICELAKE: 98 case INTEL_FAM6_ICELAKE_X: 99 case INTEL_FAM6_ICELAKE_D: 100 case INTEL_FAM6_TIGERLAKE_L: 101 case INTEL_FAM6_TIGERLAKE: 102 case INTEL_FAM6_ROCKETLAKE: 103 case INTEL_FAM6_ALDERLAKE: 104 case INTEL_FAM6_ALDERLAKE_L: 105 if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) 106 return true; 107 break; 108 } 109 110 return false; 111 } 112 113 PMU_EVENT_ATTR_STRING(tsc, attr_tsc, "event=0x00" ); 114 PMU_EVENT_ATTR_STRING(aperf, attr_aperf, "event=0x01" ); 115 PMU_EVENT_ATTR_STRING(mperf, attr_mperf, "event=0x02" ); 116 PMU_EVENT_ATTR_STRING(pperf, attr_pperf, "event=0x03" ); 117 PMU_EVENT_ATTR_STRING(smi, attr_smi, "event=0x04" ); 118 PMU_EVENT_ATTR_STRING(ptsc, attr_ptsc, "event=0x05" ); 119 PMU_EVENT_ATTR_STRING(irperf, attr_irperf, "event=0x06" ); 120 PMU_EVENT_ATTR_STRING(cpu_thermal_margin, attr_therm, "event=0x07" ); 121 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot, attr_therm_snap, "1" ); 122 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit, attr_therm_unit, "C" ); 123 124 static unsigned long msr_mask; 125 126 PMU_EVENT_GROUP(events, aperf); 127 PMU_EVENT_GROUP(events, mperf); 128 PMU_EVENT_GROUP(events, pperf); 129 PMU_EVENT_GROUP(events, smi); 130 PMU_EVENT_GROUP(events, ptsc); 131 PMU_EVENT_GROUP(events, irperf); 132 133 static struct attribute *attrs_therm[] = { 134 &attr_therm.attr.attr, 135 &attr_therm_snap.attr.attr, 136 &attr_therm_unit.attr.attr, 137 NULL, 138 }; 139 140 static struct attribute_group group_therm = { 141 .name = "events", 142 .attrs = attrs_therm, 143 }; 144 145 static struct perf_msr msr[] = { 146 [PERF_MSR_TSC] = { .no_check = true, }, 147 [PERF_MSR_APERF] = { MSR_IA32_APERF, &group_aperf, test_aperfmperf, }, 148 [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &group_mperf, test_aperfmperf, }, 149 [PERF_MSR_PPERF] = { MSR_PPERF, &group_pperf, test_intel, }, 150 [PERF_MSR_SMI] = { MSR_SMI_COUNT, &group_smi, test_intel, }, 151 [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &group_ptsc, test_ptsc, }, 152 [PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &group_irperf, test_irperf, }, 153 [PERF_MSR_THERM] = { MSR_IA32_THERM_STATUS, &group_therm, test_therm_status, }, 154 }; 155 156 static struct attribute *events_attrs[] = { 157 &attr_tsc.attr.attr, 158 NULL, 159 }; 160 161 static struct attribute_group events_attr_group = { 162 .name = "events", 163 .attrs = events_attrs, 164 }; 165 166 PMU_FORMAT_ATTR(event, "config:0-63"); 167 static struct attribute *format_attrs[] = { 168 &format_attr_event.attr, 169 NULL, 170 }; 171 static struct attribute_group format_attr_group = { 172 .name = "format", 173 .attrs = format_attrs, 174 }; 175 176 static const struct attribute_group *attr_groups[] = { 177 &events_attr_group, 178 &format_attr_group, 179 NULL, 180 }; 181 182 static const struct attribute_group *attr_update[] = { 183 &group_aperf, 184 &group_mperf, 185 &group_pperf, 186 &group_smi, 187 &group_ptsc, 188 &group_irperf, 189 &group_therm, 190 NULL, 191 }; 192 193 static int msr_event_init(struct perf_event *event) 194 { 195 u64 cfg = event->attr.config; 196 197 if (event->attr.type != event->pmu->type) 198 return -ENOENT; 199 200 /* unsupported modes and filters */ 201 if (event->attr.sample_period) /* no sampling */ 202 return -EINVAL; 203 204 if (cfg >= PERF_MSR_EVENT_MAX) 205 return -EINVAL; 206 207 cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX); 208 209 if (!(msr_mask & (1 << cfg))) 210 return -EINVAL; 211 212 event->hw.idx = -1; 213 event->hw.event_base = msr[cfg].msr; 214 event->hw.config = cfg; 215 216 return 0; 217 } 218 219 static inline u64 msr_read_counter(struct perf_event *event) 220 { 221 u64 now; 222 223 if (event->hw.event_base) 224 rdmsrl(event->hw.event_base, now); 225 else 226 now = rdtsc_ordered(); 227 228 return now; 229 } 230 231 static void msr_event_update(struct perf_event *event) 232 { 233 u64 prev, now; 234 s64 delta; 235 236 /* Careful, an NMI might modify the previous event value: */ 237 again: 238 prev = local64_read(&event->hw.prev_count); 239 now = msr_read_counter(event); 240 241 if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev) 242 goto again; 243 244 delta = now - prev; 245 if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) { 246 delta = sign_extend64(delta, 31); 247 local64_add(delta, &event->count); 248 } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) { 249 /* If valid, extract digital readout, otherwise set to -1: */ 250 now = now & (1ULL << 31) ? (now >> 16) & 0x3f : -1; 251 local64_set(&event->count, now); 252 } else { 253 local64_add(delta, &event->count); 254 } 255 } 256 257 static void msr_event_start(struct perf_event *event, int flags) 258 { 259 u64 now = msr_read_counter(event); 260 261 local64_set(&event->hw.prev_count, now); 262 } 263 264 static void msr_event_stop(struct perf_event *event, int flags) 265 { 266 msr_event_update(event); 267 } 268 269 static void msr_event_del(struct perf_event *event, int flags) 270 { 271 msr_event_stop(event, PERF_EF_UPDATE); 272 } 273 274 static int msr_event_add(struct perf_event *event, int flags) 275 { 276 if (flags & PERF_EF_START) 277 msr_event_start(event, flags); 278 279 return 0; 280 } 281 282 static struct pmu pmu_msr = { 283 .task_ctx_nr = perf_sw_context, 284 .attr_groups = attr_groups, 285 .event_init = msr_event_init, 286 .add = msr_event_add, 287 .del = msr_event_del, 288 .start = msr_event_start, 289 .stop = msr_event_stop, 290 .read = msr_event_update, 291 .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 292 .attr_update = attr_update, 293 }; 294 295 static int __init msr_init(void) 296 { 297 if (!boot_cpu_has(X86_FEATURE_TSC)) { 298 pr_cont("no MSR PMU driver.\n"); 299 return 0; 300 } 301 302 msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL); 303 304 perf_pmu_register(&pmu_msr, "msr", -1); 305 306 return 0; 307 } 308 device_initcall(msr_init); 309