1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/perf_event.h> 3 #include <linux/sysfs.h> 4 #include <linux/nospec.h> 5 #include <asm/intel-family.h> 6 #include "probe.h" 7 8 enum perf_msr_id { 9 PERF_MSR_TSC = 0, 10 PERF_MSR_APERF = 1, 11 PERF_MSR_MPERF = 2, 12 PERF_MSR_PPERF = 3, 13 PERF_MSR_SMI = 4, 14 PERF_MSR_PTSC = 5, 15 PERF_MSR_IRPERF = 6, 16 PERF_MSR_THERM = 7, 17 PERF_MSR_EVENT_MAX, 18 }; 19 20 static bool test_aperfmperf(int idx, void *data) 21 { 22 return boot_cpu_has(X86_FEATURE_APERFMPERF); 23 } 24 25 static bool test_ptsc(int idx, void *data) 26 { 27 return boot_cpu_has(X86_FEATURE_PTSC); 28 } 29 30 static bool test_irperf(int idx, void *data) 31 { 32 return boot_cpu_has(X86_FEATURE_IRPERF); 33 } 34 35 static bool test_therm_status(int idx, void *data) 36 { 37 return boot_cpu_has(X86_FEATURE_DTHERM); 38 } 39 40 static bool test_intel(int idx, void *data) 41 { 42 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || 43 boot_cpu_data.x86 != 6) 44 return false; 45 46 switch (boot_cpu_data.x86_model) { 47 case INTEL_FAM6_NEHALEM: 48 case INTEL_FAM6_NEHALEM_G: 49 case INTEL_FAM6_NEHALEM_EP: 50 case INTEL_FAM6_NEHALEM_EX: 51 52 case INTEL_FAM6_WESTMERE: 53 case INTEL_FAM6_WESTMERE_EP: 54 case INTEL_FAM6_WESTMERE_EX: 55 56 case INTEL_FAM6_SANDYBRIDGE: 57 case INTEL_FAM6_SANDYBRIDGE_X: 58 59 case INTEL_FAM6_IVYBRIDGE: 60 case INTEL_FAM6_IVYBRIDGE_X: 61 62 case INTEL_FAM6_HASWELL: 63 case INTEL_FAM6_HASWELL_X: 64 case INTEL_FAM6_HASWELL_L: 65 case INTEL_FAM6_HASWELL_G: 66 67 case INTEL_FAM6_BROADWELL: 68 case INTEL_FAM6_BROADWELL_D: 69 case INTEL_FAM6_BROADWELL_G: 70 case INTEL_FAM6_BROADWELL_X: 71 case INTEL_FAM6_SAPPHIRERAPIDS_X: 72 73 case INTEL_FAM6_ATOM_SILVERMONT: 74 case INTEL_FAM6_ATOM_SILVERMONT_D: 75 case INTEL_FAM6_ATOM_AIRMONT: 76 77 case INTEL_FAM6_ATOM_GOLDMONT: 78 case INTEL_FAM6_ATOM_GOLDMONT_D: 79 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 80 case INTEL_FAM6_ATOM_TREMONT_D: 81 case INTEL_FAM6_ATOM_TREMONT: 82 case INTEL_FAM6_ATOM_TREMONT_L: 83 84 case INTEL_FAM6_XEON_PHI_KNL: 85 case INTEL_FAM6_XEON_PHI_KNM: 86 if (idx == PERF_MSR_SMI) 87 return true; 88 break; 89 90 case INTEL_FAM6_SKYLAKE_L: 91 case INTEL_FAM6_SKYLAKE: 92 case INTEL_FAM6_SKYLAKE_X: 93 case INTEL_FAM6_KABYLAKE_L: 94 case INTEL_FAM6_KABYLAKE: 95 case INTEL_FAM6_COMETLAKE_L: 96 case INTEL_FAM6_COMETLAKE: 97 case INTEL_FAM6_ICELAKE_L: 98 case INTEL_FAM6_ICELAKE: 99 case INTEL_FAM6_ICELAKE_X: 100 case INTEL_FAM6_ICELAKE_D: 101 case INTEL_FAM6_TIGERLAKE_L: 102 case INTEL_FAM6_TIGERLAKE: 103 case INTEL_FAM6_ROCKETLAKE: 104 case INTEL_FAM6_ALDERLAKE: 105 case INTEL_FAM6_ALDERLAKE_L: 106 case INTEL_FAM6_ALDERLAKE_N: 107 case INTEL_FAM6_RAPTORLAKE: 108 case INTEL_FAM6_RAPTORLAKE_P: 109 case INTEL_FAM6_RAPTORLAKE_S: 110 if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) 111 return true; 112 break; 113 } 114 115 return false; 116 } 117 118 PMU_EVENT_ATTR_STRING(tsc, attr_tsc, "event=0x00" ); 119 PMU_EVENT_ATTR_STRING(aperf, attr_aperf, "event=0x01" ); 120 PMU_EVENT_ATTR_STRING(mperf, attr_mperf, "event=0x02" ); 121 PMU_EVENT_ATTR_STRING(pperf, attr_pperf, "event=0x03" ); 122 PMU_EVENT_ATTR_STRING(smi, attr_smi, "event=0x04" ); 123 PMU_EVENT_ATTR_STRING(ptsc, attr_ptsc, "event=0x05" ); 124 PMU_EVENT_ATTR_STRING(irperf, attr_irperf, "event=0x06" ); 125 PMU_EVENT_ATTR_STRING(cpu_thermal_margin, attr_therm, "event=0x07" ); 126 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot, attr_therm_snap, "1" ); 127 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit, attr_therm_unit, "C" ); 128 129 static unsigned long msr_mask; 130 131 PMU_EVENT_GROUP(events, aperf); 132 PMU_EVENT_GROUP(events, mperf); 133 PMU_EVENT_GROUP(events, pperf); 134 PMU_EVENT_GROUP(events, smi); 135 PMU_EVENT_GROUP(events, ptsc); 136 PMU_EVENT_GROUP(events, irperf); 137 138 static struct attribute *attrs_therm[] = { 139 &attr_therm.attr.attr, 140 &attr_therm_snap.attr.attr, 141 &attr_therm_unit.attr.attr, 142 NULL, 143 }; 144 145 static struct attribute_group group_therm = { 146 .name = "events", 147 .attrs = attrs_therm, 148 }; 149 150 static struct perf_msr msr[] = { 151 [PERF_MSR_TSC] = { .no_check = true, }, 152 [PERF_MSR_APERF] = { MSR_IA32_APERF, &group_aperf, test_aperfmperf, }, 153 [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &group_mperf, test_aperfmperf, }, 154 [PERF_MSR_PPERF] = { MSR_PPERF, &group_pperf, test_intel, }, 155 [PERF_MSR_SMI] = { MSR_SMI_COUNT, &group_smi, test_intel, }, 156 [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &group_ptsc, test_ptsc, }, 157 [PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &group_irperf, test_irperf, }, 158 [PERF_MSR_THERM] = { MSR_IA32_THERM_STATUS, &group_therm, test_therm_status, }, 159 }; 160 161 static struct attribute *events_attrs[] = { 162 &attr_tsc.attr.attr, 163 NULL, 164 }; 165 166 static struct attribute_group events_attr_group = { 167 .name = "events", 168 .attrs = events_attrs, 169 }; 170 171 PMU_FORMAT_ATTR(event, "config:0-63"); 172 static struct attribute *format_attrs[] = { 173 &format_attr_event.attr, 174 NULL, 175 }; 176 static struct attribute_group format_attr_group = { 177 .name = "format", 178 .attrs = format_attrs, 179 }; 180 181 static const struct attribute_group *attr_groups[] = { 182 &events_attr_group, 183 &format_attr_group, 184 NULL, 185 }; 186 187 static const struct attribute_group *attr_update[] = { 188 &group_aperf, 189 &group_mperf, 190 &group_pperf, 191 &group_smi, 192 &group_ptsc, 193 &group_irperf, 194 &group_therm, 195 NULL, 196 }; 197 198 static int msr_event_init(struct perf_event *event) 199 { 200 u64 cfg = event->attr.config; 201 202 if (event->attr.type != event->pmu->type) 203 return -ENOENT; 204 205 /* unsupported modes and filters */ 206 if (event->attr.sample_period) /* no sampling */ 207 return -EINVAL; 208 209 if (cfg >= PERF_MSR_EVENT_MAX) 210 return -EINVAL; 211 212 cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX); 213 214 if (!(msr_mask & (1 << cfg))) 215 return -EINVAL; 216 217 event->hw.idx = -1; 218 event->hw.event_base = msr[cfg].msr; 219 event->hw.config = cfg; 220 221 return 0; 222 } 223 224 static inline u64 msr_read_counter(struct perf_event *event) 225 { 226 u64 now; 227 228 if (event->hw.event_base) 229 rdmsrl(event->hw.event_base, now); 230 else 231 now = rdtsc_ordered(); 232 233 return now; 234 } 235 236 static void msr_event_update(struct perf_event *event) 237 { 238 u64 prev, now; 239 s64 delta; 240 241 /* Careful, an NMI might modify the previous event value: */ 242 again: 243 prev = local64_read(&event->hw.prev_count); 244 now = msr_read_counter(event); 245 246 if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev) 247 goto again; 248 249 delta = now - prev; 250 if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) { 251 delta = sign_extend64(delta, 31); 252 local64_add(delta, &event->count); 253 } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) { 254 /* If valid, extract digital readout, otherwise set to -1: */ 255 now = now & (1ULL << 31) ? (now >> 16) & 0x3f : -1; 256 local64_set(&event->count, now); 257 } else { 258 local64_add(delta, &event->count); 259 } 260 } 261 262 static void msr_event_start(struct perf_event *event, int flags) 263 { 264 u64 now = msr_read_counter(event); 265 266 local64_set(&event->hw.prev_count, now); 267 } 268 269 static void msr_event_stop(struct perf_event *event, int flags) 270 { 271 msr_event_update(event); 272 } 273 274 static void msr_event_del(struct perf_event *event, int flags) 275 { 276 msr_event_stop(event, PERF_EF_UPDATE); 277 } 278 279 static int msr_event_add(struct perf_event *event, int flags) 280 { 281 if (flags & PERF_EF_START) 282 msr_event_start(event, flags); 283 284 return 0; 285 } 286 287 static struct pmu pmu_msr = { 288 .task_ctx_nr = perf_sw_context, 289 .attr_groups = attr_groups, 290 .event_init = msr_event_init, 291 .add = msr_event_add, 292 .del = msr_event_del, 293 .start = msr_event_start, 294 .stop = msr_event_stop, 295 .read = msr_event_update, 296 .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 297 .attr_update = attr_update, 298 }; 299 300 static int __init msr_init(void) 301 { 302 if (!boot_cpu_has(X86_FEATURE_TSC)) { 303 pr_cont("no MSR PMU driver.\n"); 304 return 0; 305 } 306 307 msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL); 308 309 perf_pmu_register(&pmu_msr, "msr", -1); 310 311 return 0; 312 } 313 device_initcall(msr_init); 314