1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/perf_event.h> 3 #include <linux/sysfs.h> 4 #include <linux/nospec.h> 5 #include <asm/intel-family.h> 6 #include "probe.h" 7 8 enum perf_msr_id { 9 PERF_MSR_TSC = 0, 10 PERF_MSR_APERF = 1, 11 PERF_MSR_MPERF = 2, 12 PERF_MSR_PPERF = 3, 13 PERF_MSR_SMI = 4, 14 PERF_MSR_PTSC = 5, 15 PERF_MSR_IRPERF = 6, 16 PERF_MSR_THERM = 7, 17 PERF_MSR_EVENT_MAX, 18 }; 19 20 static bool test_aperfmperf(int idx, void *data) 21 { 22 return boot_cpu_has(X86_FEATURE_APERFMPERF); 23 } 24 25 static bool test_ptsc(int idx, void *data) 26 { 27 return boot_cpu_has(X86_FEATURE_PTSC); 28 } 29 30 static bool test_irperf(int idx, void *data) 31 { 32 return boot_cpu_has(X86_FEATURE_IRPERF); 33 } 34 35 static bool test_therm_status(int idx, void *data) 36 { 37 return boot_cpu_has(X86_FEATURE_DTHERM); 38 } 39 40 static bool test_intel(int idx, void *data) 41 { 42 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || 43 boot_cpu_data.x86 != 6) 44 return false; 45 46 switch (boot_cpu_data.x86_model) { 47 case INTEL_FAM6_NEHALEM: 48 case INTEL_FAM6_NEHALEM_G: 49 case INTEL_FAM6_NEHALEM_EP: 50 case INTEL_FAM6_NEHALEM_EX: 51 52 case INTEL_FAM6_WESTMERE: 53 case INTEL_FAM6_WESTMERE_EP: 54 case INTEL_FAM6_WESTMERE_EX: 55 56 case INTEL_FAM6_SANDYBRIDGE: 57 case INTEL_FAM6_SANDYBRIDGE_X: 58 59 case INTEL_FAM6_IVYBRIDGE: 60 case INTEL_FAM6_IVYBRIDGE_X: 61 62 case INTEL_FAM6_HASWELL: 63 case INTEL_FAM6_HASWELL_X: 64 case INTEL_FAM6_HASWELL_L: 65 case INTEL_FAM6_HASWELL_G: 66 67 case INTEL_FAM6_BROADWELL: 68 case INTEL_FAM6_BROADWELL_D: 69 case INTEL_FAM6_BROADWELL_G: 70 case INTEL_FAM6_BROADWELL_X: 71 case INTEL_FAM6_SAPPHIRERAPIDS_X: 72 case INTEL_FAM6_EMERALDRAPIDS_X: 73 74 case INTEL_FAM6_ATOM_SILVERMONT: 75 case INTEL_FAM6_ATOM_SILVERMONT_D: 76 case INTEL_FAM6_ATOM_AIRMONT: 77 78 case INTEL_FAM6_ATOM_GOLDMONT: 79 case INTEL_FAM6_ATOM_GOLDMONT_D: 80 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 81 case INTEL_FAM6_ATOM_TREMONT_D: 82 case INTEL_FAM6_ATOM_TREMONT: 83 case INTEL_FAM6_ATOM_TREMONT_L: 84 85 case INTEL_FAM6_XEON_PHI_KNL: 86 case INTEL_FAM6_XEON_PHI_KNM: 87 if (idx == PERF_MSR_SMI) 88 return true; 89 break; 90 91 case INTEL_FAM6_SKYLAKE_L: 92 case INTEL_FAM6_SKYLAKE: 93 case INTEL_FAM6_SKYLAKE_X: 94 case INTEL_FAM6_KABYLAKE_L: 95 case INTEL_FAM6_KABYLAKE: 96 case INTEL_FAM6_COMETLAKE_L: 97 case INTEL_FAM6_COMETLAKE: 98 case INTEL_FAM6_ICELAKE_L: 99 case INTEL_FAM6_ICELAKE: 100 case INTEL_FAM6_ICELAKE_X: 101 case INTEL_FAM6_ICELAKE_D: 102 case INTEL_FAM6_TIGERLAKE_L: 103 case INTEL_FAM6_TIGERLAKE: 104 case INTEL_FAM6_ROCKETLAKE: 105 case INTEL_FAM6_ALDERLAKE: 106 case INTEL_FAM6_ALDERLAKE_L: 107 case INTEL_FAM6_ALDERLAKE_N: 108 case INTEL_FAM6_RAPTORLAKE: 109 case INTEL_FAM6_RAPTORLAKE_P: 110 case INTEL_FAM6_RAPTORLAKE_S: 111 case INTEL_FAM6_METEORLAKE: 112 case INTEL_FAM6_METEORLAKE_L: 113 if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) 114 return true; 115 break; 116 } 117 118 return false; 119 } 120 121 PMU_EVENT_ATTR_STRING(tsc, attr_tsc, "event=0x00" ); 122 PMU_EVENT_ATTR_STRING(aperf, attr_aperf, "event=0x01" ); 123 PMU_EVENT_ATTR_STRING(mperf, attr_mperf, "event=0x02" ); 124 PMU_EVENT_ATTR_STRING(pperf, attr_pperf, "event=0x03" ); 125 PMU_EVENT_ATTR_STRING(smi, attr_smi, "event=0x04" ); 126 PMU_EVENT_ATTR_STRING(ptsc, attr_ptsc, "event=0x05" ); 127 PMU_EVENT_ATTR_STRING(irperf, attr_irperf, "event=0x06" ); 128 PMU_EVENT_ATTR_STRING(cpu_thermal_margin, attr_therm, "event=0x07" ); 129 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot, attr_therm_snap, "1" ); 130 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit, attr_therm_unit, "C" ); 131 132 static unsigned long msr_mask; 133 134 PMU_EVENT_GROUP(events, aperf); 135 PMU_EVENT_GROUP(events, mperf); 136 PMU_EVENT_GROUP(events, pperf); 137 PMU_EVENT_GROUP(events, smi); 138 PMU_EVENT_GROUP(events, ptsc); 139 PMU_EVENT_GROUP(events, irperf); 140 141 static struct attribute *attrs_therm[] = { 142 &attr_therm.attr.attr, 143 &attr_therm_snap.attr.attr, 144 &attr_therm_unit.attr.attr, 145 NULL, 146 }; 147 148 static struct attribute_group group_therm = { 149 .name = "events", 150 .attrs = attrs_therm, 151 }; 152 153 static struct perf_msr msr[] = { 154 [PERF_MSR_TSC] = { .no_check = true, }, 155 [PERF_MSR_APERF] = { MSR_IA32_APERF, &group_aperf, test_aperfmperf, }, 156 [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &group_mperf, test_aperfmperf, }, 157 [PERF_MSR_PPERF] = { MSR_PPERF, &group_pperf, test_intel, }, 158 [PERF_MSR_SMI] = { MSR_SMI_COUNT, &group_smi, test_intel, }, 159 [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &group_ptsc, test_ptsc, }, 160 [PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &group_irperf, test_irperf, }, 161 [PERF_MSR_THERM] = { MSR_IA32_THERM_STATUS, &group_therm, test_therm_status, }, 162 }; 163 164 static struct attribute *events_attrs[] = { 165 &attr_tsc.attr.attr, 166 NULL, 167 }; 168 169 static struct attribute_group events_attr_group = { 170 .name = "events", 171 .attrs = events_attrs, 172 }; 173 174 PMU_FORMAT_ATTR(event, "config:0-63"); 175 static struct attribute *format_attrs[] = { 176 &format_attr_event.attr, 177 NULL, 178 }; 179 static struct attribute_group format_attr_group = { 180 .name = "format", 181 .attrs = format_attrs, 182 }; 183 184 static const struct attribute_group *attr_groups[] = { 185 &events_attr_group, 186 &format_attr_group, 187 NULL, 188 }; 189 190 static const struct attribute_group *attr_update[] = { 191 &group_aperf, 192 &group_mperf, 193 &group_pperf, 194 &group_smi, 195 &group_ptsc, 196 &group_irperf, 197 &group_therm, 198 NULL, 199 }; 200 201 static int msr_event_init(struct perf_event *event) 202 { 203 u64 cfg = event->attr.config; 204 205 if (event->attr.type != event->pmu->type) 206 return -ENOENT; 207 208 /* unsupported modes and filters */ 209 if (event->attr.sample_period) /* no sampling */ 210 return -EINVAL; 211 212 if (cfg >= PERF_MSR_EVENT_MAX) 213 return -EINVAL; 214 215 cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX); 216 217 if (!(msr_mask & (1 << cfg))) 218 return -EINVAL; 219 220 event->hw.idx = -1; 221 event->hw.event_base = msr[cfg].msr; 222 event->hw.config = cfg; 223 224 return 0; 225 } 226 227 static inline u64 msr_read_counter(struct perf_event *event) 228 { 229 u64 now; 230 231 if (event->hw.event_base) 232 rdmsrl(event->hw.event_base, now); 233 else 234 now = rdtsc_ordered(); 235 236 return now; 237 } 238 239 static void msr_event_update(struct perf_event *event) 240 { 241 u64 prev, now; 242 s64 delta; 243 244 /* Careful, an NMI might modify the previous event value: */ 245 again: 246 prev = local64_read(&event->hw.prev_count); 247 now = msr_read_counter(event); 248 249 if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev) 250 goto again; 251 252 delta = now - prev; 253 if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) { 254 delta = sign_extend64(delta, 31); 255 local64_add(delta, &event->count); 256 } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) { 257 /* If valid, extract digital readout, otherwise set to -1: */ 258 now = now & (1ULL << 31) ? (now >> 16) & 0x3f : -1; 259 local64_set(&event->count, now); 260 } else { 261 local64_add(delta, &event->count); 262 } 263 } 264 265 static void msr_event_start(struct perf_event *event, int flags) 266 { 267 u64 now = msr_read_counter(event); 268 269 local64_set(&event->hw.prev_count, now); 270 } 271 272 static void msr_event_stop(struct perf_event *event, int flags) 273 { 274 msr_event_update(event); 275 } 276 277 static void msr_event_del(struct perf_event *event, int flags) 278 { 279 msr_event_stop(event, PERF_EF_UPDATE); 280 } 281 282 static int msr_event_add(struct perf_event *event, int flags) 283 { 284 if (flags & PERF_EF_START) 285 msr_event_start(event, flags); 286 287 return 0; 288 } 289 290 static struct pmu pmu_msr = { 291 .task_ctx_nr = perf_sw_context, 292 .attr_groups = attr_groups, 293 .event_init = msr_event_init, 294 .add = msr_event_add, 295 .del = msr_event_del, 296 .start = msr_event_start, 297 .stop = msr_event_stop, 298 .read = msr_event_update, 299 .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 300 .attr_update = attr_update, 301 }; 302 303 static int __init msr_init(void) 304 { 305 if (!boot_cpu_has(X86_FEATURE_TSC)) { 306 pr_cont("no MSR PMU driver.\n"); 307 return 0; 308 } 309 310 msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL); 311 312 perf_pmu_register(&pmu_msr, "msr", -1); 313 314 return 0; 315 } 316 device_initcall(msr_init); 317