1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/perf_event.h> 3 #include <linux/nospec.h> 4 #include <asm/intel-family.h> 5 6 enum perf_msr_id { 7 PERF_MSR_TSC = 0, 8 PERF_MSR_APERF = 1, 9 PERF_MSR_MPERF = 2, 10 PERF_MSR_PPERF = 3, 11 PERF_MSR_SMI = 4, 12 PERF_MSR_PTSC = 5, 13 PERF_MSR_IRPERF = 6, 14 PERF_MSR_THERM = 7, 15 PERF_MSR_THERM_SNAP = 8, 16 PERF_MSR_THERM_UNIT = 9, 17 PERF_MSR_EVENT_MAX, 18 }; 19 20 static bool test_aperfmperf(int idx) 21 { 22 return boot_cpu_has(X86_FEATURE_APERFMPERF); 23 } 24 25 static bool test_ptsc(int idx) 26 { 27 return boot_cpu_has(X86_FEATURE_PTSC); 28 } 29 30 static bool test_irperf(int idx) 31 { 32 return boot_cpu_has(X86_FEATURE_IRPERF); 33 } 34 35 static bool test_therm_status(int idx) 36 { 37 return boot_cpu_has(X86_FEATURE_DTHERM); 38 } 39 40 static bool test_intel(int idx) 41 { 42 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || 43 boot_cpu_data.x86 != 6) 44 return false; 45 46 switch (boot_cpu_data.x86_model) { 47 case INTEL_FAM6_NEHALEM: 48 case INTEL_FAM6_NEHALEM_G: 49 case INTEL_FAM6_NEHALEM_EP: 50 case INTEL_FAM6_NEHALEM_EX: 51 52 case INTEL_FAM6_WESTMERE: 53 case INTEL_FAM6_WESTMERE_EP: 54 case INTEL_FAM6_WESTMERE_EX: 55 56 case INTEL_FAM6_SANDYBRIDGE: 57 case INTEL_FAM6_SANDYBRIDGE_X: 58 59 case INTEL_FAM6_IVYBRIDGE: 60 case INTEL_FAM6_IVYBRIDGE_X: 61 62 case INTEL_FAM6_HASWELL_CORE: 63 case INTEL_FAM6_HASWELL_X: 64 case INTEL_FAM6_HASWELL_ULT: 65 case INTEL_FAM6_HASWELL_GT3E: 66 67 case INTEL_FAM6_BROADWELL_CORE: 68 case INTEL_FAM6_BROADWELL_XEON_D: 69 case INTEL_FAM6_BROADWELL_GT3E: 70 case INTEL_FAM6_BROADWELL_X: 71 72 case INTEL_FAM6_ATOM_SILVERMONT: 73 case INTEL_FAM6_ATOM_SILVERMONT_X: 74 case INTEL_FAM6_ATOM_AIRMONT: 75 76 case INTEL_FAM6_ATOM_GOLDMONT: 77 case INTEL_FAM6_ATOM_GOLDMONT_X: 78 79 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 80 81 case INTEL_FAM6_XEON_PHI_KNL: 82 case INTEL_FAM6_XEON_PHI_KNM: 83 if (idx == PERF_MSR_SMI) 84 return true; 85 break; 86 87 case INTEL_FAM6_SKYLAKE_MOBILE: 88 case INTEL_FAM6_SKYLAKE_DESKTOP: 89 case INTEL_FAM6_SKYLAKE_X: 90 case INTEL_FAM6_KABYLAKE_MOBILE: 91 case INTEL_FAM6_KABYLAKE_DESKTOP: 92 case INTEL_FAM6_ICELAKE_MOBILE: 93 if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) 94 return true; 95 break; 96 } 97 98 return false; 99 } 100 101 struct perf_msr { 102 u64 msr; 103 struct perf_pmu_events_attr *attr; 104 bool (*test)(int idx); 105 }; 106 107 PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00" ); 108 PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01" ); 109 PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02" ); 110 PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03" ); 111 PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04" ); 112 PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05" ); 113 PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06" ); 114 PMU_EVENT_ATTR_STRING(cpu_thermal_margin, evattr_therm, "event=0x07" ); 115 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot, evattr_therm_snap, "1" ); 116 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit, evattr_therm_unit, "C" ); 117 118 static struct perf_msr msr[] = { 119 [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, }, 120 [PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, }, 121 [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, }, 122 [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, }, 123 [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, }, 124 [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &evattr_ptsc, test_ptsc, }, 125 [PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &evattr_irperf, test_irperf, }, 126 [PERF_MSR_THERM] = { MSR_IA32_THERM_STATUS, &evattr_therm, test_therm_status, }, 127 [PERF_MSR_THERM_SNAP] = { MSR_IA32_THERM_STATUS, &evattr_therm_snap, test_therm_status, }, 128 [PERF_MSR_THERM_UNIT] = { MSR_IA32_THERM_STATUS, &evattr_therm_unit, test_therm_status, }, 129 }; 130 131 static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = { 132 NULL, 133 }; 134 135 static struct attribute_group events_attr_group = { 136 .name = "events", 137 .attrs = events_attrs, 138 }; 139 140 PMU_FORMAT_ATTR(event, "config:0-63"); 141 static struct attribute *format_attrs[] = { 142 &format_attr_event.attr, 143 NULL, 144 }; 145 static struct attribute_group format_attr_group = { 146 .name = "format", 147 .attrs = format_attrs, 148 }; 149 150 static const struct attribute_group *attr_groups[] = { 151 &events_attr_group, 152 &format_attr_group, 153 NULL, 154 }; 155 156 static int msr_event_init(struct perf_event *event) 157 { 158 u64 cfg = event->attr.config; 159 160 if (event->attr.type != event->pmu->type) 161 return -ENOENT; 162 163 /* unsupported modes and filters */ 164 if (event->attr.sample_period) /* no sampling */ 165 return -EINVAL; 166 167 if (cfg >= PERF_MSR_EVENT_MAX) 168 return -EINVAL; 169 170 cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX); 171 172 if (!msr[cfg].attr) 173 return -EINVAL; 174 175 event->hw.idx = -1; 176 event->hw.event_base = msr[cfg].msr; 177 event->hw.config = cfg; 178 179 return 0; 180 } 181 182 static inline u64 msr_read_counter(struct perf_event *event) 183 { 184 u64 now; 185 186 if (event->hw.event_base) 187 rdmsrl(event->hw.event_base, now); 188 else 189 now = rdtsc_ordered(); 190 191 return now; 192 } 193 194 static void msr_event_update(struct perf_event *event) 195 { 196 u64 prev, now; 197 s64 delta; 198 199 /* Careful, an NMI might modify the previous event value: */ 200 again: 201 prev = local64_read(&event->hw.prev_count); 202 now = msr_read_counter(event); 203 204 if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev) 205 goto again; 206 207 delta = now - prev; 208 if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) { 209 delta = sign_extend64(delta, 31); 210 local64_add(delta, &event->count); 211 } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) { 212 /* If valid, extract digital readout, otherwise set to -1: */ 213 now = now & (1ULL << 31) ? (now >> 16) & 0x3f : -1; 214 local64_set(&event->count, now); 215 } else { 216 local64_add(delta, &event->count); 217 } 218 } 219 220 static void msr_event_start(struct perf_event *event, int flags) 221 { 222 u64 now = msr_read_counter(event); 223 224 local64_set(&event->hw.prev_count, now); 225 } 226 227 static void msr_event_stop(struct perf_event *event, int flags) 228 { 229 msr_event_update(event); 230 } 231 232 static void msr_event_del(struct perf_event *event, int flags) 233 { 234 msr_event_stop(event, PERF_EF_UPDATE); 235 } 236 237 static int msr_event_add(struct perf_event *event, int flags) 238 { 239 if (flags & PERF_EF_START) 240 msr_event_start(event, flags); 241 242 return 0; 243 } 244 245 static struct pmu pmu_msr = { 246 .task_ctx_nr = perf_sw_context, 247 .attr_groups = attr_groups, 248 .event_init = msr_event_init, 249 .add = msr_event_add, 250 .del = msr_event_del, 251 .start = msr_event_start, 252 .stop = msr_event_stop, 253 .read = msr_event_update, 254 .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 255 }; 256 257 static int __init msr_init(void) 258 { 259 int i, j = 0; 260 261 if (!boot_cpu_has(X86_FEATURE_TSC)) { 262 pr_cont("no MSR PMU driver.\n"); 263 return 0; 264 } 265 266 /* Probe the MSRs. */ 267 for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) { 268 u64 val; 269 270 /* Virt sucks; you cannot tell if a R/O MSR is present :/ */ 271 if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val)) 272 msr[i].attr = NULL; 273 } 274 275 /* List remaining MSRs in the sysfs attrs. */ 276 for (i = 0; i < PERF_MSR_EVENT_MAX; i++) { 277 if (msr[i].attr) 278 events_attrs[j++] = &msr[i].attr->attr.attr; 279 } 280 events_attrs[j] = NULL; 281 282 perf_pmu_register(&pmu_msr, "msr", -1); 283 284 return 0; 285 } 286 device_initcall(msr_init); 287